CN1324705C - Integrated circuit capable of avoiding bolt-lock effect - Google Patents
Integrated circuit capable of avoiding bolt-lock effect Download PDFInfo
- Publication number
- CN1324705C CN1324705C CNB2004100046228A CN200410004622A CN1324705C CN 1324705 C CN1324705 C CN 1324705C CN B2004100046228 A CNB2004100046228 A CN B2004100046228A CN 200410004622 A CN200410004622 A CN 200410004622A CN 1324705 C CN1324705 C CN 1324705C
- Authority
- CN
- China
- Prior art keywords
- latch
- diode
- joint sheet
- shunt diode
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000694 effects Effects 0.000 title abstract description 5
- 230000003071 parasitic effect Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 31
- 230000001681 protective effect Effects 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000024241 parasitism Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000000977 initiatory effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to an integrated circuit capable of avoiding a bolt-lock effect. The integrated circuit capable of avoiding a bolt-lock effect comprises an interior circuit, at least one ESD protection component, at least one driving area, at least one first shunting diode, at least one second shunting diode and a ferrule, wherein the interior circuit which is arranged on a base board contains at least one parasitic SCR structure; the ESD protection component and the driving area which are arranged on the base board are coupled with an engaging pad; the first shunting diode is provided with an anode for coupling with the engaging pad, and a cathode for coupling a first voltage source; the second shunting diode is provided with a cathode for coupling with the engaging pad, and an anode for coupling with a second voltage source; distances among the first shunting diode, the second shunting diode, the interior circuit, and the ESD protection component and the driving area which are connected to the engaging pad are not less than 150 micrometers; the ferrule is used for surrounding the first shunting diode and the second shunting diode.
Description
Technical field
The present invention relates to a kind of integrated circuit, particularly a kind of integrated circuit of avoiding latch-up.
Background technology
Latch-up (latchup) is a reliability issues very important among the CMOS IC, is a kind of by parasitic PNPN (thyristor, SCR) the formed low impedance state of structure conducting.Because when latch-up takes place, have a low parallel impedance between power line and the ground, therefore, a large amount of power line electric currents will be present between the power line.If this electric current does not have confined words, this will cause logic error, circuit erroneous action, or IC produced non-response injury.Unfortunately, because the P+ of PMOS, the NWELL of NMOS, P substrate, N+ will form the structure of PNPN SCR, and will generate this parasitic SCR structure in the CMOS technology.
There are many factors will cause the latch-up of CMOS, yet, the most tangible is exactly IC when operation, the substrate current that is produced by hot carrier (hot-carrier) effect, and/or the forward current of the parasitic diode that is caused by the interference (noise) that comes across on the joint sheet (pad).
The substrate current that most of latch-up is produced is to inject via the 14 formed parasitic diode Dp of Electrostatic Discharge protective circuit on the chip, as shown in fig. 1.Parasitic SCR structure 12 is because parasitic p+/nwe11/p-sub and the transistorized conducting of nwe11/psub/n+ and conducting.And if across the voltage vbe of base-emitter junction greater than 0.7v, these two transistors can conductings, and this voltage is to depend on the ohmically voltage drop of well/sub (IR drop).Therefore, in order to prevent the generation of latch-up, must reduce the dead resistance or the transistorized gain of parasitic pnp/npn of well region/substrate.
The traditional solution and the shortcoming thereof of latch-up:
1, prevents latch-up by technology, extension (epitaxial) type CMOS can provide the dead resistance of a less well region/substrate, and trench isolations and SOI can dwindle the transistorized coupling effect of parasitic NPN/PNP, so it can be used for and prevents latch-up.Yet this technology can increase process complexity and manufacturing cost.
2, prevent latch-up by topology, protective ring (guard ring) is a kind of the most frequently used method, increases the latch-up resistance, also can be to doing uncoupling between the parasitic two-carrier transistor, and can in the CMOS internal circuit, produce before the latch-up, assemble the carrier that is injected into.Or say, the current potential contact (well/sub pickup contact) of increase well region/substrate and minimizing assembly doped region contact the distance between (pickup contact) with current potential, also can reduce the parasitic resistance that can increase the well region/substrate of latch-up ability.Yet they can account for the wafer layout area, and increase the size of chip, and under the specified arrangement restriction, add protective ring or increase current potential contact (pickup contacts) and can have any problem.In addition, another kind of method is to increase the distance export/go between injector (i/o injector) and internal circuit, yet this will increase the size of entire chip widely, and regular meeting is limited in the use the time.
3, prevent latch-up by circuit engineering, in No. 5942932, United States Patent (USP) that shen proposed, a latch-up circuit for detecting is proposed, variation in order to the voltage level that records well region/substrate (well/sub), and when latch-up takes place, activate and retract its original level in order to voltage level with well region/substrate.The method still can increase circuit complexity and arrangement space.
Therefore, the means of defence that needs a reality and be easy to realize near internal circuit, can't add protective ring or increase the current potential contact in particular cases, reduces the generation of latch-up.
Summary of the invention
In view of this, primary and foremost purpose of the present invention is to be to provide a kind of integrated circuit of avoiding latch-up, triggers the influence power in source by dwindling latch-up, and reduces the generation of latch-up.
For reaching above-mentioned purpose, the invention provides a kind of integrated circuit of avoiding latch-up.In this circuit, an internal circuit is arranged on the substrate, contains at least one parasitic SCR structure.At least one esd protection assembly and active area are arranged at and are coupled to this joint sheet on this substrate; At least one first shunt diode has an anode and couples this joint sheet, and a negative electrode couples one first voltage source.At least one second shunt diode; have a negative electrode and couple this joint sheet; and one anode couple one second voltage source, and first, second shunt diode and internal circuit, and the esd protection assembly and the distance between the active area that are connected to joint sheet are not less than 150 microns.One protective ring is in order to around first, second shunt diode.
The invention has the advantages that: improved the accurate position of the triggering that causes latch-up, therefore reduced the chance that latch-up takes place.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the schematic diagram of existing integrated circuit.
Fig. 2 is a schematic diagram of avoiding the integrated circuit of latch-up of the present invention.
Embodiment
There are many factors can cause the latch-up of CMOS, yet, the most tangible when being exactly the IC operation, the substrate current that produces by hot carrier effect, and/or the forward current of the parasitic diode that is caused by the interference (noise) that comes across on the joint sheet (pad).And the substrate current that most of latch-up produced is to inject via the formed parasitic diode of Electrostatic Discharge protective circuit on the chip.
The present invention uses the passive method of forbidding parasitic SCR conducting unlike prior art, prevents the generation of latch-up.Spirit of the present invention is to be not change under the layout of original internal circuit and esd protection assembly, by increasing the shunt paths of shunt diode as substrate current, triggers the influence power in source to dwindle latch-up, and then reduces the chance that latch-up takes place.
Be in order to the method for avoiding internal circuit to produce latch-up of the present invention to be described among Fig. 2.The present invention is on the substrate 26 with an internal circuit 20, active area 18, first external circuit 24 and esd protection assembly 14, and shunt diode (D1, D2) is set; Wherein shunt diode (D1, D2) and internal circuit 20 and the active area 18 and the distance between the esd protection assembly 14 (for example: X1, X2) that are connected to joint sheet 16 are not less than 150 microns.When an overcurrent comes across joint sheet 16; shunt diode (D1, D2) is as an extra current path; so as to reducing the substrate current that is injected by esd protection assembly 14 effectively, therefore avoid causing the latch-up of parasitic SCR structure 12 in the internal circuit.
In the present invention, it is before latch-up takes place that definition " triggers accurate position ", is injected into the accurate position of maximum current of internal circuit 20 by joint sheet 16.Moreover according to Kirchhoff's law, when there be (D1, D2) in shunt diode, the electric current that is injected on joint sheet 16 can be shared with shunt diode (D1, D2) by esd protection assembly 14.So the substrate current that is injected into internal circuit 20 by esd protection assembly 14 will reduce effectively, the accurate position of triggering of promptly causing latch-up is that the number along with shunt diode increases and improves.In other words, the present invention has improved the accurate position of the triggering that causes latch-up, has therefore reduced the chance that latch-up takes place.
And in the present invention, shunt diode (D1, D2) can be arranged on joint sheet 16 free space at a distance, even near the arrangement space joint sheet 16 is not enough, and can't increase under the special case of protective ring, still can reduce the chance that latch-up takes place.
In addition, shunt diode (D1, D2) is in normal circuit not conducting of operating time, and conducting when noise or overshoot/undershoot voltage come across joint sheet 16.In the present invention, shunt diode (D1, D2) is one to have two-step diffusion (double-diffused-drain) structure to increase the low-voltage diode (diode) or the high voltage diode (diode) of breakdown voltage.Or say that shunt diode (D1, D2) can be one and adds esd protection assembly 14 formed parasitic diodes, for example have grounded-grid, suspension joint or connect NMOS, the PMOS transistor of a RC circuit.Be adjacent to the latch-up of parasitic SCR in first external circuit 24 of shunt diode (D1, D2) for fear of initiation, the distance X 3 that first external circuit that is not connected to joint sheet 16 on shunt diode (D1, D2) and the substrate is 24 will surpass 80 microns (μ m).
In addition, be to use a suitable protective ring 22 around shunt diode (D1, D2) among the present invention.Because the existence of protective ring 22 by the carrier that shunt diode (D1, D2) injects, before the latch-up of another parasitic SCR, will be assembled and be removed near they may cause.Under situation about having around protective ring 22, be adjacent to the latch-up of parasitic SCR in first external circuit 24 of shunt diode (D1, D2) for fear of initiation, the distance that first external circuit that is not connected to joint sheet 16 on shunt diode (D1, D2) and the substrate is 24 will surpass 40 microns (μ m) at least.
As shown in Figure 2, a kind of integrated circuit of avoiding latch-up of the present invention.In this integrated circuit, an internal circuit 20 is arranged on the substrate 26, contains a parasitic SCR structure 12.Esd protection assembly 14 and active area 18 are arranged on this substrate 26, and are coupled to joint sheet 16.The first shunt diode D1 has an anode electric property coupling joint sheet 16, and a negative electrode electric property coupling one first voltage source V dd.The second shunt diode D2; has a negative electrode electric property coupling joint sheet 16; and one anode couple one second voltage source V ss, and first, second shunt diode D1, D2 and internal circuit 20 and the esd protection assembly 14 and the distance between the active area 18 (X1, X2) that are connected to joint sheet 16 are not less than 150 microns (μ m).One protective ring 22, be around first, second shunt diode D1, D2, be used to the carrier that shunt diode (D1, D2) injects, cause before the latch-up of another parasitic SCR in one first external circuit 24, assemble and remove the carrier that injects by shunt diode (D1, D2).Wherein shunt diode (D1, D2) can be (double-diffused-drain) structure that has two-step diffusion to increase the low pressure diode or the high-voltage diode of breakdown voltage.Perhaps, shunt diode (D1, D2) can be one and adds esd protection assembly 14 formed parasitic diodes, for example has grounded-grid, suspension joint or connects NMOS, the PMOS of a RC circuit.Be adjacent to the latch-up of parasitic SCR in first external circuit 24 of shunt diode (D1, D2) for fear of initiation, the distance X 3 that first external circuit that is not connected to joint sheet 16 on shunt diode (D1, D2) and the substrate is 24 will surpass 40 microns (μ m).
According to Kirchhoff's law,, can share with shunt diode (D1, D2) by esd protection assembly 14 when shunt diode (D1, D2) when existing, the electric current that on joint sheet 16, is injected into.So the substrate current that is injected into internal circuit 20 by esd protection assembly 14 will reduce effectively, the accurate position of triggering of promptly causing latch-up is that the number along with shunt diode increases and improves.In other words, the present invention has improved the accurate position of the triggering that causes latch-up, has therefore reduced the chance that latch-up takes place.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (9)
1, a kind of integrated circuit of avoiding latch-up is characterized in that comprising:
One internal circuit is arranged on the substrate, contains at least one parasitic SCR structure;
At least one active area is arranged on this substrate, is coupled to a joint sheet; And
At least one shunt diode couples this joint sheet, and this shunt diode and this internal circuit and the distance that is connected between the active area of this joint sheet are not less than 150 microns; Wherein this shunt diode as a shunt paths, produces latch-up so as to avoiding this parasitism SCR structure when a big electric current comes across this joint sheet.
2, the integrated circuit of avoiding latch-up according to claim 1, it is characterized in that: comprise that more one first external circuit is arranged on this substrate, be not connected, and the distance between this shunt diode and this first external circuit is not less than 80 microns with this joint sheet.
3, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: more comprise a protective ring, around this shunt diode.
4, the integrated circuit of avoiding latch-up according to claim 3, it is characterized in that: comprise that more one first external circuit is arranged on this substrate, be not connected, and the distance between this shunt diode and this first external circuit is not less than 40 microns with this joint sheet.
5, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: wherein this shunt diode is one to have the diode of two-step diffusion structure.
6, the integrated circuit of avoiding latch-up according to claim 1 is characterized in that: wherein this shunt diode is a parasitic diode.
7, a kind of integrated circuit of avoiding latch-up is characterized in that comprising:
One internal circuit is arranged on the substrate, contains at least one parasitic SCR structure;
At least one esd protection assembly is arranged on this substrate, and is coupled to a joint sheet;
At least one active area is arranged on this substrate, couples this joint sheet;
At least one first shunt diode has an anode and couples this joint sheet, and a negative electrode couples one first voltage source;
At least one second shunt diode, have a negative electrode and couple this joint sheet, and one anode couple one second voltage source, and this first, second shunt diode and this internal circuit and the esd protection assembly and the distance between the active area that are connected to this joint sheet are not less than 150 microns; And
One protective ring is around above-mentioned first, second shunt diode.
8, the integrated circuit of avoiding latch-up according to claim 7, it is characterized in that: comprise that more at least one first external circuit is arranged on this substrate, and be not connected with this joint sheet, the distance between this first, second shunt diode and this first external circuit is not less than 40 microns.
9, the integrated circuit of avoiding latch-up according to claim 7 is characterized in that: wherein this first, second shunt diode respectively is one to have the diode of two-step diffusion structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100046228A CN1324705C (en) | 2004-02-20 | 2004-02-20 | Integrated circuit capable of avoiding bolt-lock effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100046228A CN1324705C (en) | 2004-02-20 | 2004-02-20 | Integrated circuit capable of avoiding bolt-lock effect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1658392A CN1658392A (en) | 2005-08-24 |
| CN1324705C true CN1324705C (en) | 2007-07-04 |
Family
ID=35007746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100046228A Expired - Lifetime CN1324705C (en) | 2004-02-20 | 2004-02-20 | Integrated circuit capable of avoiding bolt-lock effect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1324705C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037748B (en) * | 2014-06-18 | 2016-08-31 | 电子科技大学 | A kind of anti-breech lock for ESD triggers circuit |
| CN107331662B (en) * | 2017-07-28 | 2018-10-23 | 深圳市汇春科技股份有限公司 | A kind of ESD protection circuit and structure based on CMOS technology |
| CN110501589A (en) * | 2019-08-14 | 2019-11-26 | 中国科学院近代物理研究所 | A kind of simulation of ASIC latch and protection system and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1132937A (en) * | 1995-04-06 | 1996-10-09 | 财团法人工业技术研究院 | Electrostatic discharge protection circuit for integrated circuit |
| US5591992A (en) * | 1991-03-28 | 1997-01-07 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| US20020089017A1 (en) * | 2001-01-05 | 2002-07-11 | Lai Chun Hsiang | Electostatic discharge protection circuit coupled on I/O pad |
| CN1378281A (en) * | 2001-04-04 | 2002-11-06 | 华邦电子股份有限公司 | Silicon controlled rectifier and method for realising static discharging protection and locking resisting |
-
2004
- 2004-02-20 CN CNB2004100046228A patent/CN1324705C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591992A (en) * | 1991-03-28 | 1997-01-07 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| CN1132937A (en) * | 1995-04-06 | 1996-10-09 | 财团法人工业技术研究院 | Electrostatic discharge protection circuit for integrated circuit |
| US20020089017A1 (en) * | 2001-01-05 | 2002-07-11 | Lai Chun Hsiang | Electostatic discharge protection circuit coupled on I/O pad |
| CN1378281A (en) * | 2001-04-04 | 2002-11-06 | 华邦电子股份有限公司 | Silicon controlled rectifier and method for realising static discharging protection and locking resisting |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1658392A (en) | 2005-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8049250B2 (en) | Circuit and method for power clamp triggered dual SCR ESD protection | |
| US7868387B2 (en) | Low leakage protection device | |
| KR100240872B1 (en) | Electrostatic discharge circuit and integrated circuit having the same | |
| US5572394A (en) | CMOS on-chip four-LVTSCR ESD protection scheme | |
| JP2022517016A (en) | Electrical overload protection with low leakage current for high voltage tolerant high speed interfaces | |
| US6858901B2 (en) | ESD protection circuit with high substrate-triggering efficiency | |
| US20030042498A1 (en) | Method of forming a substrate-triggered SCR device in CMOS technology | |
| US10930641B2 (en) | Series connected ESD protection circuit | |
| EP3404713B1 (en) | Electrostatic discharge (esd) protection device and method for operating an esd protection device | |
| US20180247927A1 (en) | Device and method for electrostatic discharge (esd) protection | |
| Ker et al. | Latchup-free ESD protection design with complementary substrate-triggered SCR devices | |
| KR100258276B1 (en) | An esd structure that employs a schottky-barrier to reduce the likelihood of latch up | |
| US20180247928A1 (en) | Electrostatic discharge (esd) protection device and method for operating an esd protection device | |
| CN102208412B (en) | SCR structure used for ESD protection of integrated circuit output stage | |
| CN1324705C (en) | Integrated circuit capable of avoiding bolt-lock effect | |
| CN113838847B (en) | Bidirectional DCSCR device for low-voltage ESD protection | |
| US7221027B2 (en) | Latchup prevention method for integrated circuits and device using the same | |
| US6680838B2 (en) | Electrostatic discharge protection circuit | |
| CN100438018C (en) | Static discharge protective circuit and method for double carrier complementary metal oxide semiconductor | |
| CN1322586C (en) | Electrostatic discharge protection device for high-voltage integrated circuit | |
| CN116093104B (en) | Electrostatic and surge protection circuit applied to direct current/direct current conversion chip | |
| CN100338769C (en) | Electrostatic discharge protector adapted for overhigh or overlow input voltage threshold | |
| CN116207094B (en) | Electrostatic and surge protection circuit applied to high-speed transmission interface chip | |
| CN114664815B (en) | High-maintenance-voltage TVS discrete device with embedded NPN structure | |
| Rebello et al. | Systematic Study of Grounded N-Well Latchup in 55nm Technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070704 |
|
| CX01 | Expiry of patent term |