CN1324662C - Method for etching side wall and method for forming semiconductor structure - Google Patents
Method for etching side wall and method for forming semiconductor structure Download PDFInfo
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- CN1324662C CN1324662C CNB200310101461XA CN200310101461A CN1324662C CN 1324662 C CN1324662 C CN 1324662C CN B200310101461X A CNB200310101461X A CN B200310101461XA CN 200310101461 A CN200310101461 A CN 200310101461A CN 1324662 C CN1324662 C CN 1324662C
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Abstract
The present invention provides a method for etching side walls and a method for forming semiconductor structures, wherein the method for etching side walls provides a substrate with a groove first, and the opening, the side wall and the bottom of the groove are provided with stuffing; then by means of a reaction between anti-etching agent and the stuffing at the bottom of the groove, the stuffing on the opening and the side wall of the groove is removed to leave the stuffing at the bottom of the groove. In the reaction between the anti-etching agent and the stuffing at the bottom of the groove, the stuffing at the bottom of the groove is mainly used to form air bubbles, wherein the air bubbles are formed by means of turning the substrate reversely and immersing the substrate into etching agent. The present invention can remove matter which seals the opening of the groove, but can not remove the matter at the bottom of the groove in order to fill the groove completely.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, particularly relate to a kind of method of etching sidewall, a kind of engraving method that fills up in the groove step, and a kind of method that in substrate, forms semiconductor structure by shallow trench isolation from preparation process with groove.
Background technology
In the preparation process of semiconductor device, integrated circuit structure normally exists with a kind of structure of multilayer.At first on basalis, the transistor unit that will have the diffusion region is formed on the silicon base; In follow-up formed other layer, interconnective metal wire can be patterned and be electrically connected to transistor unit to define the device with required function, is then kept apart with dielectric materials such as silicon dioxide between the conductive layer that is patterned and other conductive layer.These dielectric materials constitute the insulating barrier and the basalis of sandwich construction basically.As used herein " substrate " this noun comprises a basic substrate such as a semiconductor silicon wafer, and the basalis of any sandwich construction.
Form in the preparation process of structure in substrate, groove normally is formed in a kind of material layer, on silicon base, metallic substrates or dielectric substrate layer, and can insert other material in the groove.(shallow trench isolation, preparation process STI) is an example, the active region that groove installs as transistor or memory cell etc. in order to definition with shallow channel isolation area.The groove that is formed on substrate is in order to isolate a zone, and this zone finally forms a device after doping.Usually can be received in another kind of dielectric material or the metal material different in the groove with substrate.
Please refer to Figure 1A-Fig. 1 C, Figure 1A-Fig. 1 C shows the formation method of known STI.
Please refer to Figure 1A, a substrate 10 at first is provided, be formed with a groove 12 at semiconductor-based the end 10, be formed with a pad oxide 14 and a nitration case 16 in the substrate 10 in regular turn, groove 12 passes pad oxide 14 and nitration case 16 and gos deep into substrate 10.Wherein, substrate 10 can be silicon base 10 semiconductor wafers such as grade; Nitration case 16 for example is a silicon nitride layer.In the preparation process of follow-up structure, only the related preparation process at sti structure describes, and can't disclose all steps and accompanying drawing, also can be to all structures and all detailed description of function.
Please refer to Figure 1B, Figure 1B shows the next procedure of the formation STI preparation process shown in Figure 1A.In Figure 1B, groove 12 is formed with a lining 18, and lining 18 for example is oxide layer or other material layer that is formed at the groove inboard, and lining 18 can determine whether forming as required.
Please refer to Fig. 1 C, form a filler layer 20 on nitration case 16 and groove 12, filler layer 20 can fill up groove 12.Filler layer 20 for example is oxide layer or metal level, utilize tetraethyl orthosilicate (tetraethylorthosilicate, TEOS) and high-density plasma (high density plasma, HDP) silicon dioxide layer of Xing Chenging is as material, (chemical vapor deposition, method CVD) forms by chemical vapour deposition (CVD).
Then, with the filler layer 20 of substrate 10 tops, nitration case 16, and pad oxide 14 10 remove in regular turn, the fillers that only stay in the groove 12 carry out in order to subsequent preparation process.
Insert the method for filler in substrate 10 in the formed groove 12, available general technique known is carried out.With the STI preparation process is example, can utilize the method for CVD that dielectric material or electric conducting material are inserted in the groove 12.Because the cause of groove 12 landform, the material in the groove 12 can be deposited in the opening portion of groove 12 and hinder groove 12 to be filled.
Please refer to Fig. 2 A, Fig. 2 A is the drawings in detail that shows the substrate 10 with groove 12, and groove is formed with filler layer 20 12 inner branches.The formation method is at first to go up in groove 12 surfaces to form a lining 18, and inserts a filler layer 20 in groove 12.Shown in Fig. 2 A, because the cause of filler layer 20, opening 22 parts of groove 12 can become comparatively narrow.Continuing the deposition action of filler layer 20 possibly can't fill up groove 12, produces unacceptable space for preventing situation and filler layer 20 that groove 12 takes place not exclusively to fill up, needs a step that additionally opening 22 is enlarged usually.
Please refer to Fig. 2 B, Fig. 2 B has shown that the filler layer 20 in the groove 12 can be formed with space 24 when the extra step that opening 22 is enlarged is not carried out.In general, dry etching steps often is used to remove the material that makes opening 22 narrow, so that filling step can be proceeded.Yet when the material of etched trench sidewall and groove opening 22, the material that is formed at groove 12 bottoms also can be removed.Therefore, dry ecthing is not can improve maybe to promote the Perfected process that groove fills up.
Along with the preparation process development of technology, the continuous downsizing of the size of assembly and becoming increasingly complex, thus the size of groove also become narrow, when causing groove in filling up the step of groove, not filled up fully as yet, groove opening is closed, and makes the unwanted space of the inner formation of groove.Therefore, propose a kind of engraving method that groove fills up step that is used for herein, solve the space problem of groove inside, and the material of channel bottom is removed, to allow groove be filled up fully.
Summary of the invention
The object of the present invention is to provide a kind of method of etching sidewall and the method for formation semiconductor structure, can improve groove structure or profile, but can not remove the channel bottom material and can not form the space.
For achieving the above object, the invention provides a kind of method of etching sidewall, comprise the following steps: to provide the semiconductor substrate, this semiconductor-based end, have a groove, and be formed with a packed layer on this semiconductor-based end, this packed layer to small part is inserted in this groove; Reverse at this semiconductor-based end; And this semiconductor-based end that will reverse be soaked into an etchant, remove and to be positioned at the opening of this groove and this packed layer on the sidewall.
This etchant comprises hydrofluoric acid, hydrogen peroxide, phosphoric acid or the hydrochloric acid of dilution and the mixture of nitric acid.
This packed layer comprises dielectric layer, conductive layer or metal level.
This dielectric layer comprises tetraethyl orthosilicate layer, silicon dioxide layer, boron-phosphorosilicate glass layer or high-density plasma oxide layer.
This conductive layer comprises polysilicon layer.
This metal level is tungsten metal level, aluminum metal layer, copper metal layer or the metal level of admiring.
The method that forms this packed layer is chemical vapour deposition (CVD) or plasma-assisted chemical vapour deposition.
The present invention also provides a kind of method of etching sidewall, comprises the following steps: to provide a substrate, and this substrate has a groove, and is provided with a packed layer along opening, sidewall and the bottom of this groove; And remove the opening of this groove and this packed layer on the sidewall, and do not remove this packed layer that is positioned at this channel bottom.
Remove the opening of this groove and this packed layer on the sidewall and the method at this packed layer of this channel bottom do not removed is the reaction that prevents between this packed layer of an etchant and this channel bottom.
The method that prevents the reaction between this packed layer of this etchant and this channel bottom is for forming bubble in this channel bottom.
This etchant comprises hydrofluoric acid, hydrogen peroxide, phosphoric acid or the hydrochloric acid of dilution and the mixture of nitric acid, and this packed layer is dielectric layer, conductive layer or metal level.
This dielectric layer comprises tetraethyl orthosilicate layer, silicon dioxide layer, boron-phosphorosilicate glass layer or high-density plasma oxide layer.
This conductive layer comprises polysilicon layer.
This metal level comprises tungsten metal level, aluminum metal layer, copper metal layer or the metal level of admiring.
The present invention also provides a kind of method that forms semiconductor structure, this semiconductor structure is from preparation process by shallow trench isolation, be formed in the substrate with a groove, comprise the following steps: in this substrate, to reach and form a packed layer in this groove, this packed layer to small part is filled up this groove, this packed layer is formed on the sidewall of this groove, and this groove that is formed with this packed layer has a groove opening; This packed layer of etching is removed the packed layer on this groove opening and this trenched side-wall, but does not remove this packed layer that is arranged at this channel bottom; And an extra encapsulant layer is set in this substrate, this groove is filled up fully.
The engraving method of this packed layer is for to cause bubble to carry out in this channel bottom, and this packed layer of this channel bottom prevents etched by this bubble.
Be soaked in the etchant by this packed layer of counter-rotating and this packed layer that will reverse and carry out etching.
This etchant is hydrofluoric acid, hydrogen peroxide, phosphoric acid or the hydrochloric acid of dilution and the mixture of nitric acid.
This packed layer comprises dielectric layer, conductive layer or metal level.
This dielectric layer comprises silicic acid tetrem vinegar layer, silicon dioxide layer, boron-phosphorosilicate glass layer or high-density plasma oxide layer.
That is to say that according to above-mentioned purpose, the method for etching sidewall provided by the invention comprises the following steps: to provide the semiconductor substrate, the semiconductor-based end, have a groove, and be formed with a packed layer at semiconductor-based the end, and packed layer to small part is inserted in the groove; Reverse at the semiconductor-based end; And the semiconductor-based end that will reverse, is soaked into an etchant and is positioned at the opening of groove and the packed layer on the sidewall with removal.
According to above-mentioned purpose, the method for the etching sidewall that the present invention provides again comprises the following steps: to provide a substrate, and substrate has a groove, and is provided with a packed layer along opening, sidewall and the bottom of groove; And remove the opening of groove and the packed layer on the sidewall, and do not remove the packed layer that is positioned at channel bottom.In an embodiment of the present invention, the packed layer of trenched side-wall and groove opening remove step, can avoid etchant and channel bottom the packed layer reaction and with its removal.In an embodiment of the present invention, be to avoid the packed layer of channel bottom to be removed by preventing that at channel bottom generation bubble the packed layer of etchant and channel bottom from reacting.
According to above-mentioned purpose, what the present invention provided in addition forms the method for semiconductor structure by shallow trench isolation in the substrate with groove from preparation process, comprise the following steps: in substrate, to reach and form a packed layer in the groove, packed layer to small part is filled up groove, packed layer is formed on the sidewall of groove, and the groove that is formed with packed layer has a groove opening; The etching packed layer to be removing the packed layer on groove opening and the trenched side-wall, but do not remove the packed layer that is arranged at channel bottom; And an extra packed layer is set in substrate, so that groove is filled up fully.In an embodiment of the present invention, the removal step of packed layer is included in channel bottom and forms a bubble, and this bubble can avoid the packed layer of channel bottom to be removed.In the present embodiment, the removal step of packed layer comprises a step with the substrate counter-rotating, and the substrate of counter-rotating is soaked in the etchant.
The present invention has several advantages and actually has a use, one of them significant advantage is can remove the material that causes the groove opening sealing, but can not remove the material of channel bottom, but the semiconductor structure that follow-up also manufacturing dimension is dwindled and integrated level is higher, and the packed layer of deposition is increased.Embodiment is described as described in the present invention; when the packed layer of channel bottom is protected; can carry out in the middle of the groove opening and the etching step of the packed layer of the trenched side-wall of part, and follow-uply continue to finish with the whole step of filling up of groove and can in groove, not form the space.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A shows known shallow channel isolation area preparation process;
Figure 1B shows the next step shown in Figure 1A;
Fig. 1 C is shown in and forms a packed layer on the nitration case, and packed layer can be inserted groove;
Fig. 2 A shows that one has the details drawing of substrate that part forms the groove of packed layer;
Fig. 2 B shows when not carrying out additional programs with the expansion groove opening, the interstitial situation of packed layer meeting;
Fig. 3 A shows the formation method of a substrate of the present invention;
Fig. 3 B shows the method for etching part packed layer of the present invention;
Fig. 3 C shows the substrate through the etching part packed layer of the present invention;
Fig. 4 shows that of the present invention one carries out the operational flowchart of etched trench opening of the present invention and sidewall.
Wherein, description of reference numerals is as follows:
10～substrate; 12～groove; 14～pad oxide; 16～nitration case; 18～lining;
20～filler layer; 22～opening; 100～substrate; 110～groove; 112～barrier layer;
114～part deposits packed layer; 116～opening; 118～etchant; 120～bubble.
Embodiment
Below provide several embodiment and conjunction with figs. so that method provided by the present invention to be described.
As mentioned above, in the manufacture method of semiconductor structure, groove or breach (gap) for example are shallow channel isolation areas etc., are defined usually to be formed in the middle of the substrate.Groove described in the present embodiment comprises the structure of breach, interconnect, hole and other similar type.Therefore groove, breach, interconnect, hole or other similarly are formed at the structure of substrate, the method that is provided among also applicable the present invention.
The material of the substrate that is provided for example is silicon or any other dielectric material, fills up another kind of different material such as any other dielectric material, polysilicon or metal etc. in the groove.In filling up the step of groove, the material of inserting groove generally all can be accumulated in the sidewall and the opening of groove, so that groove can't be filled up or form hole fully.Embodiments of the invention provide a kind of etched trench midway isostructural method, wherein are not removed and make groove can be filled follow-up at the packed layer of channel bottom.
In one embodiment of this invention, provide a substrate with semiconductor structures such as grooves; Wherein, these grooves can have lining, and substrate surface is formed with nitration case, barrier layer, and the sandwich construction of other similar material.To form a trench fill layer, trench fill layer to small part is formed in the substrate, and the trench fill layer can fill up groove by the chemical vapour deposition (CVD) step; Wherein, the trench fill layer for example be tetraethyl orthosilicate (tetraethylorthosilicate, TEOS), the boron-phosphorosilicate glass layer (borophosphosilicateglass, BPSG), silicon dioxide layer (SiO
2), high-density plasma (high density plasma, HDP) dielectric layer material such as oxide layer, perhaps polysilicon layer, tungsten metal level, copper metal layer, aluminum metal layer, and conductive layer such as the metal level of admiring.
In the present embodiment, at least the part groove in insert the trench fill layer after, substrate is soaked into one fills in the groove of etchant react so that the trench fill layer can touch etchant.The substrate meeting is inverted, so that the opening surface that makes groove is to etchant, and substrate is soaked in the etchant.Trench fill layer near the opening of groove or breach and the opening the sidewall promptly can be removed.The material of channel bottom can be protected by bubble, enters in the groove of the substrate after the counter-rotating to stop etchant.Etchant can select trench fill layer and barrier layer are had the material of preferable selection etching ratio, as hydrofluoric acid (HF), the phosphoric acid (H of dilution
3PO
4), hydrogen peroxide (H
2O
2) or hydrochloric acid (HCL) and nitric acid (HNO
3) mixture etc.
Please refer to Fig. 3 A, Fig. 3 A shows a substrate 100 provided by the present invention, wherein, is formed with a groove 110 in the substrate 100.Groove 110 is formed by the method for generally using in the semiconductor fabrication process, for example the shallow channel isolation area preparation process.One barrier layer 112 is formed in the groove 110, and some deposition packed layer 114 fills up groove 110 parts.As shown in the figure, after the formation part deposits packed layer 114, can find to be accompanied by in the groove 110 space and produce, and can be deposited in the opening 116 at groove 110 tops.
After partly depositing packed layer 114 with for example chemical vapour deposition (CVD) or plasma-assisted chemical vapour deposition, then, part is deposited packed layer 114 carry out etching step, enter groove opening 116 passages and do not having complete filling groove 110 under the situation in space with increase.
Because when utilizing chemical vapour deposition (CVD) or other semiconductor fabrication process to come deposition materials, have some little spaces or unessential space.And herein, unacceptable space is meant that the structure that can cause finishing produces defective, can flaw be arranged because of these spaces in the material.In the present embodiment, can be protected and unaffected at the material of channel bottom, and the material of the sidewall on the opening of groove and groove top can be etched, so that follow-up filler can fill up groove fully.
Please refer to Fig. 3 B, Fig. 3 B shows part deposition packed layer 114 etched steps of the present invention.After being inverted, substrate 100 is soaked in the middle of the etchant 118.Suitable etchant is decided on the etched material of want, and the selection etching ratio between palpus consideration and barrier layer, lining or substrate, as mixture of hydrofluoric acid, hydrogen peroxide, phosphoric acid or hydrochloric acid and nitric acid etc., other is known the etchant that this operator thinks fit and also can.In the present embodiment, the substrate 100 after the counter-rotating is placed in the etchant 118, to allow part deposition packed layer 114 contact with etchant 118.After part deposits packed layer 114 and etchant 118 contacts, can produce reaction, make part deposition packed layer 114 etched.
In the middle of the groove 110 of substrate 100, there is a bubble 120 to produce the material of protecting channel bottom.Shown in Fig. 3 B, substrate 100 is inverted, so the bottom of groove 110 can be positioned at the upper area of the substrate 100 after the counter-rotating, and is positioned at opposite edge with the opening 116 of groove 110.With reference to figure 3A, opening 116 is open in the context by the surface of substrate 110 again, and groove 110 extends in the substrate 100 to increase space or space.When reversing as substrate 100 is shown in Fig. 3 B and being soaked in the etchant, space in the groove 110 or the air in the space can form bubble 120 in the part etched with the bottom that prevents groove 110.
In the present embodiment, bubble 120 can be protected not etched dose of 118 etchings of material of groove 110 bottoms.Because etchant 118 can influence the cause that part deposits packed layer 114, the opening 116 of groove 110 and near the filler on the sidewall of opening 116 can be etched helping filler enter groove 110 smoothly, and the filler of groove 110 bottoms keeps not being subjected to etching and thickness during with original deposition is identical.The deposition step of the follow-up filler of proceeding can allow groove 110 be filled up fully and not have the space.
Please refer to Fig. 3 C, Fig. 3 C shows the substrate 100 behind the etching part deposition packed layer of the present invention.To remove in the substrate 100 self etching agent 118, and counter-rotating is returned.Because the cause of bubble 120 protections is arranged, groove 110 bottoms have packed layer 114 and stay.The filler of groove opening 116 and groove 110 upper portion side wall can be etched removing, so that filler can be entered smoothly in the middle of the groove.The follow-up deposition step that carries out can allow filler fill up groove 110 fully and not have the space to exist.
Please refer to Fig. 4, Fig. 4 shows that of the present invention one carries out the operational flowchart of etched trench opening of the present invention and sidewall.This method is begun to carry out by operating procedure 152, at first provides a substrate to carry out the semiconductor fabrication process.As mentioned above, this substrate can be the basalis of a basalis or sandwich construction, and is formed with a groove in the substrate, is provided with packed layer in the groove and fills up groove with part, and such groove for example is that the semiconductor fabrication process with shallow channel isolation area is formed.In general, groove can be formed in the substrate certainly, and substrate for example is silicon, dielectric material or metal etc.Packed layer can be deposited in the substrate usually, and inserts in the groove, and method can utilize chemical vapour deposition (CVD) to carry out.Packed layer can be any material that suits the requirements, and can be TEOS, SiO
2, dielectric materials such as BPSG, HDP, perhaps electric conducting material such as polysilicon, or metal materials such as tungsten, aluminium, copper and titanium.When filler was deposited in the substrate and insert in the groove, the opening part of groove can narrow down because filler is deposited in sidewall and slot wedge.
Next this method carry out step 154, utilizes the reaction of an etchant and packed layer.If be formed with barrier layer in the groove, just select to compare packed layer and have the high etchant of selecting the etching ratio with barrier layer.In the present embodiment, packed layer partly is deposited in the substrate, and inserts in the middle of the groove, and the opening part of groove narrows down because filler is deposited in sidewall and slot wedge.If continue the deposition step of filler, will cause packed layer to form the space and make groove and can't be filled up fully because of the cause that groove opening is closed; Therefore, utilize an etchant to come filler is carried out etching, and make filler enter the groove medial region smoothly to avoid unnecessary space.Concerning filler, comparing the etchant with high selection etching ratio with barrier layer or base material for example is as hydrofluoric acid, hydrogen peroxide, phosphoric acid or the hydrochloric acid of dilution and the mixture of nitric acid etc.
Then, carry out step 156, with the substrate counter-rotating so that substrate surface down, and substrate is soaked in the etchant.This has the substrate meeting counter-rotating of groove and is soaked in the middle of the etchant, so that etchant contacts with filler and reacts.Because channel shaped is formed in intrabasement cause, when substrate was reversed and is soaked into etchant, air can form bubble at channel bottom.Bubble can stop etchant to contact with the filler of channel bottom, does not make the filler of channel bottom etched and maintain the original state.
Carry out step 158, will remove in the agent of substrate self etching to continue follow-up semiconductor fabrication process.In the present embodiment, ensuing preparation process comprises and follow-uply deposits packed layer on the filler that channel bottom stays.In this mode, groove can be filled up and do not had the space fully.After the agent of substrate self etching is removed, promptly finish the step of this method.
In summary, the invention provides a kind of method of etching sidewall, a kind of engraving method in filling up the step of groove, and form the method for semiconductor structure in a kind of substrate that has groove by shallow trench isolation from preparation process.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is when being as the criterion with accompanying claims.
Claims (8)
1. method that forms semiconductor structure, this semiconductor structure be by shallow trench isolation from preparation process, be formed in the substrate with a groove, it is characterized in that comprising the following steps:
The semiconductor substrate is provided, and this semiconductor-based end, have a groove;
Form a packed layer in this substrate and in this groove, this packed layer to small part is inserted this groove, and this packed layer is formed on the sidewall of this groove, and this groove that is formed with this packed layer has a groove opening;
Reverse at this semiconductor-based end; And
This semiconductor-based end of counter-rotating, be soaked into an etchant, form the etched bubble of this packed layer that prevents this channel bottom, be positioned at the opening of this groove and this packed layer on the sidewall with removal.
2. the method for formation semiconductor structure as claimed in claim 1 is characterized in that this etchant is hydrofluoric acid, hydrogen peroxide, phosphoric acid or the hydrochloric acid of dilution and the mixture of nitric acid.
3. the method for formation semiconductor structure as claimed in claim 1 is characterized in that this packed layer comprises dielectric layer, conductive layer or metal level.
4. the method for formation semiconductor structure as claimed in claim 3 is characterized in that this dielectric layer comprises tetraethyl orthosilicate layer, silicon dioxide layer, boron-phosphorosilicate glass layer or high-density plasma oxide layer.
5. the method for formation semiconductor structure as claimed in claim 3 is characterized in that this conductive layer comprises polysilicon layer.
6. the method for formation semiconductor structure as claimed in claim 3 is characterized in that this metal level is tungsten metal level, aluminum metal layer, copper metal layer or titanium coating.
7. the method for formation semiconductor structure as claimed in claim 1, the method that it is characterized in that forming this packed layer is chemical vapour deposition (CVD) or plasma-assisted chemical vapour deposition.
8. the method for formation semiconductor structure as claimed in claim 1 is characterized in that this method also comprises after described removal is positioned at the step of the opening of this groove and this packed layer on the sidewall:
In this substrate and in this groove, proceed the step of filler, filled up fully up to this groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200310101461XA CN1324662C (en) | 2003-10-20 | 2003-10-20 | Method for etching side wall and method for forming semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200310101461XA CN1324662C (en) | 2003-10-20 | 2003-10-20 | Method for etching side wall and method for forming semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
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| CN1610073A CN1610073A (en) | 2005-04-27 |
| CN1324662C true CN1324662C (en) | 2007-07-04 |
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| CNB200310101461XA Expired - Fee Related CN1324662C (en) | 2003-10-20 | 2003-10-20 | Method for etching side wall and method for forming semiconductor structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106122A (en) * | 1982-12-10 | 1984-06-19 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| US5419809A (en) * | 1993-02-01 | 1995-05-30 | Sony Corporation | Dry etching method |
| EP1049146A2 (en) * | 1999-04-30 | 2000-11-02 | Applied Materials, Inc. | Method and apparatus for forming an inlaid capacitor in a semiconductor wafer |
-
2003
- 2003-10-20 CN CNB200310101461XA patent/CN1324662C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106122A (en) * | 1982-12-10 | 1984-06-19 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| US5419809A (en) * | 1993-02-01 | 1995-05-30 | Sony Corporation | Dry etching method |
| EP1049146A2 (en) * | 1999-04-30 | 2000-11-02 | Applied Materials, Inc. | Method and apparatus for forming an inlaid capacitor in a semiconductor wafer |
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| CN1610073A (en) | 2005-04-27 |
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