CN1322978A

CN1322978A - Computer system

Info

Publication number: CN1322978A
Application number: CN 00108307
Authority: CN
Inventors: 龚绍祖; 郑志铨; 刘纯芝; 陈益昌
Original assignee: Compal Electronics Inc
Current assignee: Compal Electronics Inc
Priority date: 2000-05-11
Filing date: 2000-05-11
Publication date: 2001-11-21
Anticipated expiration: 2020-05-11
Also published as: CN1131471C

Abstract

The computer system comprising CPU, power supply, memory and job monitoring circuit. The job monitoring circuit has a M/IO signal line for monitoring the job load of CPU and storing the monitoring result into job load register to form corresponding parameter. When the job load of CPU is found altered by the job monitoring circuit, the job regulating program in the memory sends out interrupt command to call BIOS service, which regulates the working voltage of CPU or changes the working internal frequency according to the parameter in the job load register.

Description

Computer system

The present invention relates to save in a kind of computing machine the method for power supply, be particularly related to a kind of can be via monitoring central processing unit work load frequently (internal clock frequency) or its internal work voltage in its work of dynamic adjustments, to reach the computer system of power saving purpose.

In computing machine, especially portable computer now, the method for various power source plannings and saving is suggested to be used for saving power supply one after another or makes the service time of battery can be longer.For example: monitor situation that video screen uses, monitor the situation of hard disk running or after not using after a while, make computing machine enter the power down mode of " rest ", in some computing machine, the method for frequently carrying out power saving with in the work of adjusting central processing unit is arranged also.Since when central processing unit when frequently carrying out data processing or program execution in than the work of low speed, required power supply is less, the power supply of adding in the central processing unit to be consumed accounts for a sizable ratio in the whole computer system, therefore when power supply in the battery soon ran out of, can yet be regarded as when central processing unit is worked with frequency in the lower work, prolongation was used or the good method of the duration of runs.And,, therefore also be unlikely to allow the user feel inconvenience even its central processing unit is still with running frequently in the lower work and is in very at a high speed for most computing machine now.

The method major part of carrying out the battery saving mode setting now in computer system is to be undertaken by a power management routines, usually can (Basic Input Output System BIOS) or via operating system (Operating System) carries out this power management routines via basic output loading routine.All must set relevant province's electrical quantity in above-mentioned two situations by the user, yet, setting does not want to take the trouble most of user more for this kind, therefore tend to the processing speed of central processing unit is set in the most at a high speed, thus, particularly for portable computer, the problem that power supply can't be supplied for a long time more shape is serious.

Therefore, fundamental purpose of the present invention is to provide a kind of device that can monitor the central processing unit work load automatically, work load via the monitoring central processing unit comes frequency in its work of corresponding adjustment, to reduce the electric energy that central processing unit was consumed and to solve the above problems.

For realizing described purpose, the invention provides a kind of computer system, it includes: a central processing unit, with frequency deal with data or executive routine in the predetermined work, this central processing unit also can receive the operating voltage of a preset range and change frequency in its work; One power supply unit is electrically connected on this central processing unit, and provides this central processing unit required operating voltage in the mode that can dynamically adjust; One storer is electrically connected on this central processing unit with storage data or program.This storer also comprises a work adjustment program and can be executed in this central processing unit; One work supervisory circuit is electrically connected on this central processing unit, and to monitor the work load of this central processing unit, this work supervisory circuit also comprises a work load register, to deposit the corresponding parameter of the present work load of this central processing unit of expression; Wherein this work is adjusted program and can dynamically be adjusted the operating voltage that provides to this central processing unit via this power supply unit, or according to the parameter in this work load register with in the work that changes this central processing unit frequently.

Fig. 1 is the functional block diagram of computer system of the present invention.

Fig. 2 is the hypothesis figure of the time dependent work load of central processing unit of computer system of the present invention.

With reference to Fig. 1, Fig. 1 is the functional block diagram of computer system of the present invention.Computer system of the present invention consists predominantly of a central processing unit (CPU) 10, one clock generator (clock) 16, one power supply unit (power regulator) 18, storer (Memory) 36, one work supervisory circuits (activity monitoring circuit) 50 and bus logic circuit (Bus logic circuitry) 30.

Central processing unit 10 is according to frequently carrying out data processing or program execution in the work, clock generator 16 produces the clock of fixed frequency to offer frequency in the central processing unit 10 generation work, power supply unit 18 mainly provides central processing unit 10 its needed operating voltage, storer 36 is used for storing data or program, 50 of supervisory circuits of work are used for monitoring the present work load of central processing unit 10, and generation corresponding parameter value, foundation for frequency in the work of adjusting central processing unit 10, bus logic circuit 30 is to be used for setting up writing to each other of 50 of central processing unit 10 and storer 36 and work supervisory circuits, in the storer 36 and include a work adjustment program (CPU activity adijustingprogram) 40, come central processing unit 10 is done dynamically adjustment with monitoring parameter according to 50 pairs of central processing units of work supervisory circuit, 10 present work loads.Each element in the computer system of the present invention is specified in down.

Central processing unit 10, can be as AMD K6-2 series or central processing unit at the same level, the built-in function that it has the interior frequency of its work of adjustment or receives the operating voltage of a preset range, in the central processing unit 10 and include many registers, wherein have two kinds to be with the present invention closely related person to be arranged: one is voltage affirmation register (voltage identification register, VID register) 12, another is a clock multiplier register (clock multiplier register) 14.

Clock generator (clock) 16 is electrically connected on central processing unit 10, so that the clock of central processing unit 10 1 fixed frequencies to be provided, the frequency of clock generator 16 clock that produces can be again via after the frequency multiplication of a certain multiple to provide in the required work of central processing unit 10 frequently, this frequency multiplication numerical value then is to be stored in the clock multiplier register 14, therefore, by the frequency multiplication numerical value that changes in the clock multiplier register 14, central processing unit 10 can change frequency in its work.

Voltage line (CPU I/O voltage line) 20 and central processing unit principal voltage line (CPU core voltage line) 22 are exported/gone into to 18 of power supply units to provide power supply to central processing unit 10 via central processing unit.The voltage line 20 fixing voltage level that provides is exported/gone into to central processing unit, and central processing unit 10 is linked up with this voltage level and its outer member; And the voltage level that central processing unit principal voltage line 22 is provided is by selected in a plurality of predetermined voltage levels, and these predetermined voltage levels all are 10 operating voltage that can accept and use of central processing unit in a certain preset range, and central processing unit 10 promptly is used for the communication of its inner member with one of them voltage level.In addition, the voltage level that central processing unit principal voltage line 22 is provided is to confirm that register 12 makes alterations by the voltage in the central processing unit 10, that is to say, voltage is confirmed also can store a corresponding voltage affirmation value in the register 12, be worth to select the voltage level of central processing unit principal voltage line 22 through voltage affirmation thus, power supply unit 18 also has an input link to be connected to voltage to confirm register 12.

When central processing unit 10 frequently carries out data processing or program in the work of higher speed when carrying out, required voltage level is higher, when central processing unit was carried out frequently to carry out data processing or program in than the work of low speed, required voltage level was lower, and therefore the power supply that is consumed is less.When central processing unit 10 be in the lighter period of work load and can be with lower voltage level work so that when saving power supply, the frequency multiplication numerical value that is stored in the clock multiplier register 14 can be reduced earlier, therefore pollakicoprosis and then reduces in the work of central processing unit 10, then, voltage confirms that institute's stored voltage affirmation value also can be changed in the register 12, so that power supply unit 18 can and then reduce via the voltage level of central processing unit principal voltage line 22 provides to central processing unit 10.And the frequency multiplication numerical value in the clock multiplier register 14 and voltage confirm that voltage affirmation value in the register 12 all is to adjust program 40 by the work in the central processing unit 10 of being executed in to send instruction and change.

Central processing unit 10 comprises several bus lines 34 in addition and is electrically connected to bus logic circuit 30.With regard to 80 * 86 type central processing units or its product more of new generation now, great majority all possess one storer are arranged/I/O port status signal lines (M/IO signal wire) 24, and can link up wherein logical signal state with address bus, the logic state of M/IO signal wire 24 can show the action whether central processing unit 10 is read and write over against storer 36 or I/O port.The address area of central processing unit 10 mainly contains two parts: the one, and to the part of storer, the one, to the part of I/O device.Duplicate though the read-write motion that many outputs are gone into only is simple memory data,, be not, as the register in the setting image displaying card or the control action of relevant disk drive yet also have much as duplicating of image frame.Show according to data, there is the work load of high correlation, common central processing unit heavier between whether the work load of central processing unit and M/IO signal are triggered, the M/IO signal wire is in storer with regard to more often being triggered and reads state, and therefore the state that is triggered by monitoring M/IO signal wire just becomes one of important method of weighing the central processing unit work load.

As mentioned above, M/IO signal wire 24 can remain on logic high or low level two states, when central processing unit 10 when carrying out the access action of relevant storer, M/IO signal wire 24 is in wherein a kind of state, and when central processing unit 10 when carrying out the relevant action of exporting/going into, 24 of M/IO signal wires can be in another kind of state, therefore the present invention is in order to learn the time dependent work load situation of central processing unit, and the state that utilizes monitoring M/IO signal wire to be triggered just becomes a kind of easy mode.Therefore, M/IO signal wire 24 also is electrically connected with work supervisory circuit 50 via a resistance 42 simultaneously, so that the supervisory circuit 50 of working can be monitored the present work load of central processing unit 10 via M/IO signal wire 24.

Include a resistor capacitor circuit (RC circuit) and an embedded controller (embedded controller) 26 in the work supervisory circuit 50.Resistor capacitor circuit is to be connected in series to earth terminal with an electric capacity 44 by a resistance 42 to form, 26 of embedded controllers comprise an analog-digital converter (A/D converter) 28 and one work load register (CPU activity register) 29, and are electrically connected between resistance 42 and the electric capacity 44.Resistor capacitor circuit in the work supervisory circuit 50 mainly is in order to do average to the logic level state of M/IO signal wire 24 in one period schedule time, to produce an aanalogvoltage, the length of this section schedule time then depends on the size of resistance 42 and electric capacity 44 values.In preferred embodiment of the present invention, this section schedule time suggestion the chances are 10ms is to 100ms, and for example, when the resistance value of resistance 42 is 500k Ω, when the capacitance of electric capacity 44 was 0.1 μ F, therefore, this section schedule time then was about 50ms.

Average logic level state (aanalogvoltage that is produced just) at this section M/IO signal wire 24 in the schedule time, promptly input to the analog-digital converter 28 in embedded worker's controller 26, via the average logic level values that can obtain a M/IO signal wire 24 after the conversion of analog-digital converter 28, and this mean value can be represented central processing unit 10 average work load during this period of time, and is stored in the work load register 29.Embedded controller 26 comprises one and interrupts line 32 being electrically connected to bus logic circuit 30, and then and central processing unit 10 link up, via interrupting line 32, work supervisory circuit 50 can be interrupted central processing unit 10 normal routine processes flow processs.

Storer 36 establishes a communications link via bus logic circuit 30 and central processing unit 10, wherein comprise basic output loading routine (BIOS) 38 and work adjustment program 40, work adjustment program 40 can in be contained in basic output loading routine 40 and for exporting the part of loading routine 40 substantially.When work supervisory circuit 50 is interrupted the normal routine processes flow process of central processing unit 10 via interrupting line 32 and bus logic circuit 30, also just be equivalent to send an interrupt instruction to central processing unit 10 and serve, and this BIOS service can beginning execution work be adjusted program 40 to call out a BIOS.

Work adjustment program 40 is at first inspected institute's memory contents in the work load register 29, the average logic level values of M/IO signal wire 24 just, because this mean value is represented the average work load of 10 a certain periods of central processing unit, by this, work adjustment program 40 can suitably be adjusted the interior frequency of work of central processing unit 10.For example, if the mean value of being stored in the work load register 29 shows workload or work load increase is arranged, work adjustment program 40 can suitably be adjusted voltage and confirm institute's stored voltage affirmation value in the register 12, so that power supply unit 18 can and then improve via the voltage level of central processing unit principal voltage line 22 provides to central processing unit 10, and the frequency multiplication numerical value that will be stored in the clock multiplier register 14 increases, with frequency in the work that improves central processing unit 10.On the contrary, if showing workload or work load, reduces the mean value of being stored in the work load register 29, the 40 frequency multiplication numerical value that can turn down in the clock multiplier register 14 of work adjustment program, with frequency in the work that reduces central processing unit 10, and turn down the voltage affirmation value in the voltage affirmation register 12, so that power supply unit 18 provides are to the and then reduction of voltage level of central processing unit 10.Thus, the power supply that consumed of central processing unit 10 will roughly present the regular movements of equal proportion along with the work load of central processing unit 10.

When should then there be a variety of modes to finish as for work supervisory circuit 50 via interrupting line 32 to send interrupt instruction to central processing unit 10.Mode the simplest then is to utilize a timer so that just central processing unit 10 is being sent interrupt instruction later in fixing period, and and then inspects institute's memory contents in the work load register 29.Mode used in the present invention then is that work supervisory circuit 50 will be sent interrupt instruction to central processing unit 10 when some predetermined workload of work load of central processing unit 10.

With reference to Fig. 2, Fig. 2 is the hypothesis figure of the central processing unit 10 time dependent work loads of computer system of the present invention.Suppose that embedded controller 26 suitably adjusts its span at 0 to 100 with the M/IO signal wire 24 average logic level values of analog-digital converter 28 gained, 0 represents the work load of central processing unit 10 very light, and the work load of 100 representative central processing units 10 is extremely heavy.Fig. 2 transverse axis is represented the time, and the longitudinal axis is represented the work load of central processing unit 10.The work load of central processing unit 10 and the division of dividing into five

section

60,62,64,66,68, two adjacent region sections are determined by a predetermined threshold value, are represented by dotted lines among the figure.Section 60 represents the work load of central processing unit 10 the lightest, and section 68 represents the work load of central processing unit 10 the heaviest, and on behalf of the work load of

central processing unit

10,62,64,66 of sections increase gradually successively.

In each

section

60,62,64,66,68, work adjustment program 40 can select optimal frequency multiplication numerical value and voltage affirmation to be worth in clock multiplier register 14 and voltage affirmation register 12, so that correspond to the work load of each section, therefore, when section 60, the voltage level that frequency and central processing unit principal voltage line 22 are provided in the work is minimum, and when section 68, the voltage level that frequency and central processing unit principal voltage line 22 are provided in the work is the highest,

section

62,64,66 o'clock, then between the centre and increase successively.

As shown in Figure 2, at incipient moment t ₀, the work load of central processing unit 10 is in section 60, so central processing unit 10 is operated with frequency and operating voltage in the minimum work.At t ₁Constantly, the work load of central processing unit 10 is crossed a critical line and is entered section 62, so embedded controller 26 will be sent interrupt instruction to central processing unit 10 via interrupting line 32, and program 40 is adjusted in the beginning execution work.Work adjustment program 40 at first reads content in the work load register 29, so that understand central processing unit 10 present work loads at section 62, and the corresponding storing value of heightening in clock multiplier register 14 and the voltage affirmation register 12, by heightening of frequency multiplication numerical value and voltage affirmation value, the voltage level that frequency and central processing unit principal voltage line 22 are provided in the work also can and then improve.

Same program repeats to occur in t constantly ₂And t ₃, the work of central processing unit 10 voltage level frequently interior and that accepted improves gradually, at t ₄Constantly, work adjustment program 40 makes central processing unit 10 work in the most at a high speed pattern, in its work frequently and the voltage level of being accepted all be the highest.At moment t ₅, t ₆, t ₇, the work load of central processing unit 10 counter-rotating and reducing gradually is so work adjustment program 40 makes central processing unit 10 work in pattern than low speed gradually, at moment t ₈, central processing unit 10 is operated with frequency and operating voltage in the minimum work once again.

For the work load of relevant central processing unit 10 among above-mentioned Fig. 2, visual actual state is done suitably to distinguish, and five sections needn't necessarily giving an example as the embodiment of the invention.If in two kinds of different work of the hardware constraints of central processing unit 10 tolerable frequently, if then as the work load of the central processing unit 10 of Fig. 2 just be divided into two sections.In addition, though the central processing unit 10 that comprises clock multiplier register 14 and voltage affirmation register 12 has been used in the preferred embodiment of computer system of the present invention, but not to use this kind central processing unit to exceed, yet central processing unit also can set up signal contact with power supply unit 18 computer system of the present invention via the output in the computer system/input port address bus or memory bus.In the same manner, but the clock generator 16 that produces the clock of fixed frequency in the present invention also can replace it with the clock generator that can produce change or selecting type, and central processing unit can change the output clock frequency of this clock generator via output/inbound port address bus or memory bus.

In addition, though the preferred embodiment of computer system of the present invention has been used simple resistor capacitor circuit in work supervisory circuit 50, so that try to achieve the average logic level state of in one period schedule time M/IO signal wire 24, replace yet also can use than complicated or more accurate circuit, for example, can be with the digital circuit that includes counter and timer, to calculate the number of times that M/IO signal wire 24 in a period of time touches access to memory, then this number of times is stored to the work load register 29 in the work supervisory circuit 50.

Though the preferred embodiment of computer system of the present invention utilizes M/IO signal wire 24 with as the average work load of judging 10 a certain periods of central processing unit, yet still have additive method can reach this purpose and not as limit.For some processor that does not have the M/IO signal wire, also can reach with other signal wires or the element that is equal to, in fact, even for having the processor of M/IO signal wire, also can use or learn the work load that processor is average in conjunction with other signal wires, that is to say that as long as the time dependent work load of energy monitoring processor, it all is acceptable which kind of mode reaching this purpose with.

Compare with known technology, computer system of the present invention is utilized work supervisory circuit 50 and the work adjustment program 40 average work loads with monitoring 10 a certain periods of central processing unit, then with in the work of central processing unit 10 frequently and operating voltage be adjusted to its work load and conform to, so the electrical source consumption of central processing unit 10 can dynamically downgrade minimum and still can keep its due operate as normal level in the computer system.

The above only is preferred embodiment of the present invention, and all equivalent variations and modifications of being done according to claim scope of the present invention all should belong to the covering scope of claim of the present invention.

Claims

1. computer system, it includes:

One central processing unit, with frequency deal with data or executive routine in the predetermined work, this central processing unit also can receive the operating voltage of a preset range and change frequency in its work;

One power supply unit is electrically connected on this central processing unit, and provides this central processing unit required operating voltage in the mode that can dynamically adjust;

One storer is electrically connected on this central processing unit with storage data or program, and this storer also comprises a work adjustment program and can be executed in this central processing unit;

One work supervisory circuit is electrically connected on this central processing unit, and to monitor the work load of this central processing unit, this work supervisory circuit also comprises a work load register, to deposit the corresponding parameter of the present work load of this central processing unit of expression;

Wherein this work is adjusted program and can dynamically be adjusted the operating voltage that provides to this central processing unit via this power supply unit, or according to the parameter in this work load register with in the work that changes this central processing unit frequently.

2. computer system as claimed in claim 1, wherein this central processing unit comprises one storer/I/O port status signal lines (M/IO signal wire), the frequency that this M/IO signal wire is triggered can be represented the work load of this central processing unit, this work supervisory circuit also is electrically connected on this M/IO signal wire, to learn the work load that this central processing unit is present via this M/IO signal wire.

3. computer system as claimed in claim 2, wherein this work supervisory circuit can be monitored the frequency that this M/IO signal wire is triggered in one period schedule time, and the result that will monitor is stored in this work register.

4. computer system as claimed in claim 3, wherein this work supervisory circuit comprises a resistor capacitor circuit and is electrically connected on this M/IO signal wire, and one analog-digital converter be electrically connected on this resistor capacitor circuit, the frequency translation that this resistor capacitor circuit can be triggered this M/IO signal wire is an aanalogvoltage, then is stored in this work register for this analog-digital converter is converted to a corresponding parameter.

5. computer system as claimed in claim 1, wherein this storer comprises a basic output loading routine, and this work adjustment program is exported the part of loading routine substantially for this.

6. computer system as claimed in claim 1, wherein when the work load of this this central processing unit of work monitor circuit monitors has surpassed a projected workload, this work supervisory circuit can be sent an interrupt instruction to this central processing unit, when this central processing unit is received this interrupt instruction, can temporarily interrupt present handled work, and carry out this work and adjust program.

7. computer system as claimed in claim 1, wherein this computer system comprises a clock generator and a clock frequency multiplication register, this clock generator is in order to provide the clock of this central processing unit one preset frequency, and store a frequency multiplication numerical value in this clock multiplier register, frequently be that the clock that produced by this clock generator and the product of the frequency multiplication numerical value of being stored in this clock multiplier register are determined in the work of this central processing unit.

8. computer system as claimed in claim 7, wherein this work is adjusted program and can be stored in frequency multiplication numerical value in this clock multiplier register via change, with in the work that changes this central processing unit frequently.

9. computer system as claimed in claim 1, wherein this power supply unit provide to the operating voltage of this central processing unit is selected by selecting one in a plurality of predetermined voltages.

10. computer system as claimed in claim 9, wherein these a plurality of predetermined magnitudes of voltage are to drop within the operating voltage of the acceptable preset range of this central processing unit.

11. computer system as claimed in claim 1, wherein this central processing unit includes a voltage and confirms that register is electrically connected on this power supply unit, this voltage is confirmed in the register and is stored a voltage affirmation value, this power supply unit is to confirm the voltage affirmation value that register sent according to this voltage, to provide this central processing unit required operating voltage.

12. as the computer system of claim 11, wherein this work is adjusted program and can be stored in this voltage via change and confirm voltage affirmation value in register, provides operating voltage to this central processing unit with this power supply unit of dynamic adjustment.