CN1322744C - Continuous impulse link generator by low-voltage clock signal - Google Patents
Continuous impulse link generator by low-voltage clock signal Download PDFInfo
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- CN1322744C CN1322744C CNB031412432A CN03141243A CN1322744C CN 1322744 C CN1322744 C CN 1322744C CN B031412432 A CNB031412432 A CN B031412432A CN 03141243 A CN03141243 A CN 03141243A CN 1322744 C CN1322744 C CN 1322744C
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Abstract
The present invention provides a continuous pulse string generator which uses low voltage clock signals. A circuit of each grade comprises a buffer composed of a dynamical shift register, an electrical level shifter and an inverter. With the use of the dynamical shift register, the continuous pulse string generator of the present invention can normally work under a low voltage clock signal and reduce the power consumption caused by the voltage transmission of the clock signal.
Description
Technical field
The successive pulse groups that the present invention uses relevant for a kind of LCD (sequential pulse train) generator is particularly to a kind of continuous impulse string generator that uses the low pressure clock signal.
Background technology
In LCD, because a frame picture is formed jointly by the array that a plurality of pixel constituted, therefore successive pulse groups just become the essential baseband signal that uses when driving LCD, and the generator of successive pulse groups also becomes the necessary circuitry in the LCD.
Fig. 1 represents that tradition is used for the successive pulse groups generator circuit of LCD.Because a continuous impulse generator is made up of multistage, each grade can have the pulse train of different sequential, and be succinct for what illustrate, is example with three grades only among Fig. 1.Include a shift register (shift register) 111,112 or 113 in each level, and a level shifter (level shifter) 121,122 or 123.Shift register 111,112, the 113 equal receive clock signal CK and the inversion signal CK ' thereof of each grade, and after the shift register 111 of the first order receives an inceptive impulse string IN, along with the delay of each grade on sequential and the current potential adjusting of process level shifter 121,122,123, can produce pulse train respectively with continuous different sequential and enough voltage magnitudes.
Have a certain size resistance 131,132 and electric capacity 151,152 in order to the transmission line of transmit clock signal CK and inversion signal CK ' thereof, also have a certain size resistance 141,142,143 and electric capacity 161,162,163 simultaneously at the transmission line of pulse train output.These resistance and capacitance will increase the required power consumption of whole LCD.
Yet in above-mentioned traditional continuous impulse string generator, because required voltage clock signal amplitude is not low, power consumption at transmission line can strengthen with the signal amplitude that is transmitted, and therefore tradition uses the continuous impulse string generator than the scale clock signal voltage that bigger power consumption will be arranged.
Summary of the invention
In order to address the above problem, the invention provides a kind of continuous impulse string generator that can normal running under a low pressure clock signal, reduce the power consumption that is caused because of the voltage clock signal transmission.
A purpose of the present invention is to provide a kind of continuous impulse string generator that uses the low pressure clock signal, comprises first, second dynamic shift register, first, second level shifter and first, second inverter.Wherein, each dynamic shift register has one first, second, the 3rd and four-input terminal, one first, second and third output, this first dynamic shift register this first, second, the 3rd and four-input terminal receive an inceptive impulse string respectively, one inversion signal of this inceptive impulse string, one inversion signal of one clock signal and this clock signal, this first output of this first dynamic shift register is connected to this first input end of this second dynamic shift register, the 3rd and four-input terminal of this second dynamic shift register receives inversion signal and this clock signal of this clock signal respectively, and each dynamic shift register comprises: one the one the first transistor npn npn, its grid is connected to this first input end, and drain electrode is connected to this second input; One the two the second transistor npn npn, its grid is connected to this second input, and source electrode connects and receives one first current potential; One the three the second transistor npn npn, its grid is connected to this first input end, and drain electrode is connected to this first output, and source electrode is connected to the drain electrode of the two the second transistor npn npns; One the four the second transistor npn npn, its grid are connected to the source electrode of the three the second transistor npn npns, and drain electrode is connected to the source electrode of the one the first transistor npn npns, and source electrode connects this first current potential; One the five the second transistor npn npn, its grid are connected to the source electrode of the one the first transistor npn npns, and drain electrode is connected to the 3rd input, and source electrode is connected to this second output; One the six the second transistor npn npn, its grid is connected to this second input, and drain electrode is connected to the source electrode of the five the second transistor npn npns, and source electrode connects this first current potential; One the seven the second transistor npn npn, its grid are connected to the grid of the five the second transistor npn npns, and drain electrode is connected to this four-input terminal, and source electrode is connected to the 3rd output.Each level shifter has one first, second input and an output, first and second input of this first level shifter is connected respectively to second and third output of this first dynamic shift register, the output of this first level shifter is connected to first output of this first dynamic shift register, first and second input of this second level shifter is connected respectively to second and third output of this second dynamic shift register, the output of this second level shifter is connected to first output of this second dynamic shift register, each level shifter comprises: one the eight the first transistor npn npn, its grid connects this first current potential, and source electrode connects one second current potential; One the nine the first transistor npn npn, its grid is connected with drain electrode, and source electrode is connected to the drain electrode of the eight the first transistor npn npns; One the ten the first transistor npn npn, its grid are connected to the grid of the nine the first transistor npn npns, and source electrode connects this second current potential, and drain electrode is connected to this output; One the ten one the second transistor npn npn, its grid are connected to the drain electrode of the eight the first transistor npn npns, and source electrode is connected to the drain electrode of the nine the first transistor npn npns, and drain electrode is connected to this first input end; One the ten two the second transistor npn npn, its grid are connected to the grid of the ten one the second transistor npn npns, and source electrode is connected to the drain electrode of the ten the first transistor npn npns, and source electrode is connected to this second input.Its input of first and second inverter is connected respectively to the output of this first and second level shifter, and its output is exported first and second pulse train respectively, and the output of this first inverter is connected to second input of this second dynamic shift register.
Another object of the present invention is to provide a kind of continuous impulse string generator that uses the low pressure clock signal, comprising: one first, second, third dynamic shift register, one first, second, third level shifter, one second, third, the 4th, the 5th, the 6th and the 7th inverter.Wherein, each dynamic shift register has one first, second and third input, one first, second and third output, this first dynamic shift register this first, second and third input receives an inceptive impulse string respectively, one inversion signal of this inceptive impulse string, one clock signal, this first output of this first dynamic shift register is connected to this second input of the 3rd dynamic shift register, the 3rd input of this second dynamic shift register receives the inversion signal of this clock signal, the 3rd input of the 3rd dynamic shift register receives this clock signal, and each dynamic shift register comprises: one the one the first transistor npn npn, its grid is connected to this first input end, drain electrode is connected to this second input, and source electrode is connected to the 3rd output; One the two the second transistor npn npn, its grid is connected to this first output, and source electrode connects one first current potential, and drain electrode is connected to this first output; One the three the second transistor npn npn, its grid is connected to this first output, and drain electrode is connected to the 3rd input, and source electrode is connected to this second output; One the four the second transistor npn npn, its grid is connected to this second input, and drain electrode is connected to this second output, and source electrode connects this first current potential.Each level shifter has one first, second input and an output, first and second input of this first level shifter is connected respectively to second and third output of this first shift register, first and second input of this second level shifter is connected respectively to second and third output of this second shift register, first and second input of the 3rd level shifter is connected respectively to second and third output of the 3rd shift register, each level shifter comprises: one the five the first transistor npn npn, its grid connects this first current potential, and source electrode connects one second current potential; One the six the first transistor npn npn, its source electrode are connected to the drain electrode of the five the first transistor npn npns, and drain electrode is connected to this output; One the seven the second transistor npn npn, its grid connects this second current potential, and source electrode connects and is listed as this first input end, and drain electrode is connected to this output; One first inverter, input are connected to this second input, and output is connected to the grid of the six the first transistor npn npns.This is second years old, the input of the 3rd and the 4th inverter be connected respectively to this first, the output of second and third level shifter, the output of this second and third inverter is connected respectively to the first input end of this second and third dynamic shift register, the 5th, the input of the 6th and the 7th inverter be connected respectively to this second, the output of the 3rd and the 4th inverter, the output of the 5th inverter is connected to this second input of this second dynamic shift register, and the 5th, the output of the 6th and the 7th inverter exports one first, second and third pulse train.
Below, with regard to description of drawings a kind of embodiment that uses the continuous impulse string generator of low pressure clock signal of the present invention.
Description of drawings
Fig. 1 is traditional continuous impulse string generator;
Fig. 2 is the continuous impulse string generator of the use low pressure clock signal among the present invention one first embodiment;
Fig. 3 is the dynamic shift register circuit in the first embodiment of the invention;
Fig. 4 is the level shifter circuit in the first embodiment of the invention;
Fig. 5 a and Fig. 5 b are the continuous impulse string generators of the use low pressure clock signal among the present invention one second embodiment;
Fig. 6 is the dynamic shift register circuit in the second embodiment of the invention;
Fig. 7 is the level shifter circuit in the second embodiment of the invention;
Fig. 8 is the successive pulse groups sequential chart that is produced among first and second embodiment of the present invention.
Symbol description
111,112,113: shift register;
121,122,123,221,222,223,521,522,523: level shifter;
131,132,141,142,143: resistance;
151,152,161,162,163,38,65: electric capacity;
211,212,213,511,512,513: dynamic shift register;
231,232,233,531,532,533,541,542,543,74: inverter;
32-37,44,45,62-64,73:N transistor npn npn;
31,41-43,61,71,72:P transistor npn npn.
Embodiment
Fig. 2 is the continuous impulse string generator of the use low pressure clock signal among the present invention one first embodiment.Succinct for what illustrate, be example only among Fig. 2 with three grades, the inverter of using comprising dynamic shift register 211,212,213, voltage shift register 221,222,223, as buffer 231,232,233.Each dynamic shift register 211,212,213 has input S1, S2, S3, S4, reaches output S5, S6, S7.Input S3, the S4 of dynamic shift register 211, S1, S2 receive inversion signal IN ', the clock signal C K of an inceptive impulse string IN, inceptive impulse string IN and the inversion signal CK ' of clock signal CK respectively.The output S7 of dynamic shift register 211 is connected to the input S3 of dynamic shift register 222, and the output S7 of dynamic shift register 212 is connected to the input S3 of dynamic shift register 223.Input S1, the S2 of dynamic shift register 222 be inversion signal CK ' and the clock signal CK of receive clock signal CK respectively, and the inversion signal CK ' of input S1, the S2 of dynamic shift register 223 difference receive clock signal CK and clock signal CK.
Each level shifter 221,222,223 has input L1, L2 and output L3.Input L1, the L2 of level shifter 221 is connected respectively to output S5, the S6 of dynamic shift register 211.Input L1, the L2 of level shifter 222 is connected respectively to output S5, the S6 of dynamic shift register 212.Input L1, the L2 of level shifter 223 is connected respectively to output S5, the S6 of dynamic shift register 213.The output L3 of level shifter 221 is connected to the output S7 of dynamic shift register 211, and the output L3 of level shifter 222 is connected to the output S7 of dynamic shift register 212.The output L3 of level shifter 223 is connected to the output S7 of dynamic shift register 213.
The input of inverter 231,232,233 is connected respectively to the output L3 of level shifter 221,222,223, and its output is distinguished output pulse string OUT1, OUT2, OUT3.The output of inverter 231 is connected to the input S4 of dynamic shift register 212, and the output of inverter 232 is connected to the input S4 of dynamic shift register 213.
Fig. 3 represents the dynamic shift register circuit in the above-mentioned continuous impulse string generator.Comprising P transistor npn npn 31, N transistor npn npn 32-37 and an electric capacity 38.The grid of P transistor npn npn 31 is connected to input S3, and drain electrode is connected to input S4.The grid of N transistor npn npn 32 is connected to input S4, and source electrode connects an earthing potential.The grid of N transistor npn npn 33 is connected to input S3, and drain electrode is connected to output S7, and source electrode is connected to the drain electrode of this N transistor npn npn 32.The grid of N transistor npn npn 34 is connected to the source electrode of N transistor npn npn 33, and drain electrode is connected to the source electrode of P transistor npn npn 31, and source electrode connects earthing potential.The grid of N transistor npn npn 35 is connected to the source electrode of P transistor npn npn 31, and drain electrode is connected to input S1, and source electrode is connected to output S5.The grid of N transistor npn npn 36 is connected to input S4, and drain electrode is connected to the source electrode of N transistor npn npn 35, and source electrode connects earthing potential.The grid of N transistor npn npn 37 is connected to the grid of N transistor npn npn 35, and drain electrode is connected to input S2, and source electrode is connected to output S6.
38 of electric capacity are connected between the grid and source electrode of N transistor npn npn 35.Electric capacity 38 can also be the grid-source electrode parasitic capacitance of N transistor npn npn 35.
Fig. 4 represents the level shifter circuit in the above-mentioned continuous impulse string generator.Comprising P transistor npn npn 41,42,43 and N transistor npn npn 44,45.The grid of P transistor npn npn 41 connects earthing potential, and source electrode connects a high supply power voltage VDD.The grid of P transistor npn npn 42 is connected with drain electrode, and source electrode is connected to the drain electrode of P transistor npn npn 41.The grid of P transistor npn npn 43 is connected to the grid of this P transistor npn npn 42, and source electrode connects high supply power voltage VDD, and drain electrode is connected to output L3.The grid of N transistor npn npn 44 is connected to the drain electrode of P transistor npn npn 41, and source electrode is connected to the drain electrode of P transistor npn npn 42, and drain electrode is connected to input L1.The grid of N transistor npn npn 45 is connected to the grid of N transistor npn npn 44, and source electrode is connected to the drain electrode of P transistor npn npn 43, and drain electrode is connected to input L2.
Fig. 5 a and Fig. 5 b are the continuous impulse string generators of the use low pressure clock signal among the present invention one second embodiment.Succinct for what illustrate, be example only among Fig. 5 with three grades, the inverter 531-533, the 541-543 that use comprising dynamic shift register 511,512,513, voltage shift register 521,522,523, as buffer.Each dynamic shift register 511,512,513 has input S1, S3, S4, output S2, S5, S6.Input S3, the S4 of dynamic shift register 511, S1 receive an inversion signal IN ', the clock signal C K of an inceptive impulse string IN, inceptive impulse string IN respectively.The output S2 of dynamic shift register 511 is connected to the input S4 of dynamic shift register 513.The inversion signal CK ' of the input S1 receive clock signal CK of dynamic shift register 512.The input S1 receive clock signal CK of dynamic shift register 513.
Each level shifter 521,522,523 has input L1, L2 and output L3.Input L1, the L2 of level shifter 521 is connected respectively to output S5, the S6 of dynamic shift register 511.Level shifter 522 input L1, L2 are connected respectively to output S5, the S6 of dynamic shift register 512.Input L1, the L2 of level shifter 523 is connected respectively to output S5, the S6 of dynamic shift register 513.
The input of inverter 531,532,533 is connected respectively to the output L3 of level shifter 521,522,523.The output of inverter 531,532 is connected respectively to the input S3 of dynamic shift register 512,513.The input of inverter 541,542,543 is connected respectively to the output of inverter 531,532,533.The output of inverter 541 is connected to the input S4 of dynamic shift register 512.The output output pulse string OUT1 of inverter 541,542,543, OUT2, OUT3.
Fig. 6 represents the dynamic shift register circuit in the above-mentioned continuous impulse string generator.Comprising P transistor npn npn 61, N transistor npn npn 62-64 and an electric capacity 65.The grid of P transistor npn npn 61 is connected to input S3, and drain electrode is connected to input S4, and source electrode is connected to output S6.The grid of N transistor npn npn 62 is connected to output S2, and source electrode connects an earthing potential, and drain electrode is connected to output S6.The grid of N transistor npn npn 63 is connected to output S6, and drain electrode is connected to input S1, and source electrode is connected to output S5.The grid of N transistor npn npn 64 is connected to input S4, and drain electrode is connected to output S5, and source electrode connects earthing potential.
65 of electric capacity are connected between the grid and source electrode of N transistor npn npn 63.Electric capacity 65 can also be the grid-source electrode parasitic capacitance of N transistor npn npn 63.
Fig. 7 represents the level shifter circuit in the above-mentioned continuous impulse string generator.Comprising P transistor npn npn 71,72, N transistor npn npn 73 and inverter 74.The grid of P transistor npn npn 71 connects earthing potential, and source electrode connects a high supply power voltage VDD.The source electrode of P transistor npn npn 72 is connected to the drain electrode of P transistor npn npn 71, and drain electrode is connected to output L3.The grid of N transistor npn npn 73 connects high supply power voltage VDD, and source electrode is connected to input L1, and drain electrode is connected to output L3.The input of inverter 74 is connected to input L2, and output is connected to the grid of P transistor npn npn 72.
Fig. 8 represents pulse train OUT1, OUT2, the OUT3 that the continuous impulse string generator of use low pressure clock signal among above-mentioned first and second embodiment is produced.Pulse among pulse train OUT1, OUT2, the OUT3 all differs clock signal period half.The voltage magnitude of clock signal C K is 3.3V, and VDD is 9V.
Comprehensively above-mentioned, the invention provides a kind of continuous impulse string generator that can normal running under a low pressure clock signal, each level has been used a dynamic shift register and level shifter, can receive the clock signal of low pressure, reduces the power consumption that is caused because of the voltage clock signal transmission.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (16)
1. continuous impulse string generator that uses the low pressure clock signal comprises:
First and second dynamic shift register, each dynamic shift register has first, second, the 3rd and four-input terminal, first, second and third output, this first dynamic shift register this first, second, the 3rd and four-input terminal receive an inceptive impulse string respectively, the inversion signal of this inceptive impulse string, the inversion signal of clock signal and this clock signal, this first output of this first dynamic shift register is connected to this first input end of this second dynamic shift register, and the 3rd and four-input terminal of this second dynamic shift register receive inversion signal and this clock signal of this clock signal respectively;
First and second level shifter, each level shifter has first, second input and an output, first and second input of this first level shifter is connected respectively to second and third output of this first dynamic shift register, the output of this first level shifter is connected to first output of this first dynamic shift register, first and second input of this second level shifter is connected respectively to second and third output of this second dynamic shift register, and the output of this second level shifter is connected to first output of this second dynamic shift register; And
First and second inverter, its input is connected respectively to the output of this first and second level shifter, and its output is exported first and second pulse train respectively, and the output of this first inverter is connected to second input of this second dynamic shift register.
2. the continuous impulse string generator of use low pressure clock signal as claimed in claim 1, wherein each dynamic shift register comprises:
The one the first transistor npn npns, its grid is connected to the first input end of this dynamic shift register, and drain electrode is connected to second input of this dynamic shift register;
The two the second transistor npn npns, its grid is connected to second input of this dynamic shift register, and source electrode connects first current potential;
The three the second transistor npn npns, its grid is connected to the first input end of this dynamic shift register, and drain electrode is connected to first output of this dynamic shift register, and source electrode is connected to the drain electrode of the two the second transistor npn npns;
The four the second transistor npn npns, its grid are connected to the source electrode of the three the second transistor npn npns, and drain electrode is connected to the source electrode of the one the first transistor npn npns, and source electrode connects this first current potential;
The five the second transistor npn npns, its grid are connected to the source electrode of the one the first transistor npn npns, and drain electrode is connected to the 3rd input of this dynamic shift register, and source electrode is connected to second output of this dynamic shift register;
The six the second transistor npn npns, its grid is connected to this second input of this dynamic shift register, and drain electrode is connected to the source electrode of the five the second transistor npn npns, and source electrode connects this first current potential; And
The seven the second transistor npn npns, its grid are connected to the grid of the five the second transistor npn npns, and drain electrode is connected to the four-input terminal of this dynamic shift register, and source electrode is connected to the 3rd output of this dynamic shift register.
3. the continuous impulse string generator of use low pressure clock signal as claimed in claim 1, wherein each level shifter comprises:
The eight the first transistor npn npns, its grid connects first current potential, and source electrode connects second current potential;
The nine the first transistor npn npns, its grid is connected with drain electrode, and source electrode is connected to the drain electrode of the eight the first transistor npn npns;
The ten the first transistor npn npns, its grid are connected to the grid of the nine the first transistor npn npns, and source electrode connects this second current potential, and drain electrode is connected to the output of this level shifter;
The ten one the second transistor npn npns, its grid are connected to the drain electrode of the eight the first transistor npn npns, and source electrode is connected to the drain electrode of the nine the first transistor npn npns, and drain electrode is connected to the first input end of this level shifter; And
The ten two the second transistor npn npns, its grid are connected to the grid of the ten one the second transistor npn npns, and source electrode is connected to the drain electrode of the ten the first transistor npn npns, and drain electrode is connected to second input of this level shifter.
4. the continuous impulse string generator of use low pressure clock signal as claimed in claim 2, wherein each dynamic shift register more comprises an electric capacity, is connected between the grid and source electrode of the five the second transistor npn npns.
5. as the continuous impulse string generator of claim 2 or 3 described use low pressure clock signals, wherein this first type is the P type, and this second type is the N type.
6. as the continuous impulse string generator of claim 2 or 3 described use low pressure clock signals, wherein this first current potential is an earthing potential.
7. the continuous impulse string generator of use low pressure clock signal as claimed in claim 3, wherein this second current potential is a high supply current potential VDD.
8. the continuous impulse string generator of use low pressure clock signal as claimed in claim 3, wherein the amplitude of this clock signal is less than this second current potential.
9. continuous impulse string generator that uses the low pressure clock signal comprises:
First, second and third dynamic shift register, each dynamic shift register has first, second and third input, first, second and third output, this first dynamic shift register this first, second and third input receives an inceptive impulse string respectively, the inversion signal of this inceptive impulse string, one clock signal, this first output of this first dynamic shift register is connected to this second input of the 3rd dynamic shift register, the 3rd input of this second dynamic shift register receives the inversion signal of this clock signal, and the 3rd input of the 3rd dynamic shift register receives this clock signal;
First, second and third level shifter, each level shifter has first, second input and output, first and second input of this first level shifter is connected respectively to second and third output of this first dynamic shift register, first and second input of this second level shifter is connected respectively to second and third output of this second dynamic shift register, and first and second input of the 3rd level shifter is connected respectively to second and third output of the 3rd dynamic shift register; And
Second, the 3rd, the 4th, the 5th, the the 6th and the 7th inverter, this is second years old, the input of the 3rd and the 4th inverter be connected respectively to this first, the output of second and third level shifter, the output of this second and third inverter is connected respectively to the first input end of this second and third dynamic shift register, the 5th, the input of the 6th and the 7th inverter be connected respectively to this second, the output of the 3rd and the 4th inverter, the output of the 5th inverter is connected to this second input of this second dynamic shift register, and the 5th, the output output first of the 6th and the 7th inverter, second and third pulse train.
10. the continuous impulse string generator of use low pressure clock signal as claimed in claim 9, wherein each dynamic shift register comprises:
The one the first transistor npn npns, its grid is connected to the first input end of this dynamic shift register, and drain electrode is connected to second input of this dynamic shift register, and source electrode is connected to the 3rd output of this dynamic shift register;
The two the second transistor npn npns, its grid is connected to first output of this dynamic shift register, and source electrode connects first current potential, and drain electrode is connected to the 3rd output of this dynamic shift register;
The three the second transistor npn npns, its grid is connected to the 3rd output of this dynamic shift register, and drain electrode is connected to the 3rd input of this dynamic shift register, and source electrode is connected to second output of this dynamic shift register; And
The four the second transistor npn npns, its grid is connected to second input of this dynamic shift register, and drain electrode is connected to second output of this dynamic shift register, and source electrode connects this first current potential.
11. the continuous impulse string generator of use low pressure clock signal as claimed in claim 9, wherein each level shifter comprises:
The five the first transistor npn npns, its grid connects first current potential, and source electrode connects second current potential;
The six the first transistor npn npns, its source electrode are connected to the drain electrode of the five the first transistor npn npns, and drain electrode is connected to the output of this level shifter;
The seven the second transistor npn npns, its grid connects this second current potential, and source electrode is connected to the first input end of this level shifter, and drain electrode is connected to the output of this level shifter; And
First inverter, its input are connected to second input of this level shifter, and its output is connected to the grid of the six the first transistor npn npns.
12. the continuous impulse string generator of use low pressure clock signal as claimed in claim 10, wherein each dynamic shift register more comprises an electric capacity, is connected between the grid and source electrode of the three the second transistor npn npns.
13. as the continuous impulse string generator of claim 10 or 11 described use low pressure clock signals, wherein this first type is the P type, this second type is the N type.
14. as the continuous impulse string generator of claim 10 or 11 described use low pressure clock signals, wherein this first current potential is an earthing potential.
15. the continuous impulse string generator of use low pressure clock signal as claimed in claim 11, wherein this second current potential is a high supply current potential VDD.
16. the continuous impulse string generator of use low pressure clock signal as claimed in claim 11, wherein the amplitude of this clock signal is less than this second current potential.
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| CN1167967A (en) * | 1996-06-07 | 1997-12-17 | Lg半导体株式会社 | Driver circuit for thin film transistor-liquid crystal display |
| US6392628B1 (en) * | 1999-01-08 | 2002-05-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device and driving circuit therefor |
| EP1056069A2 (en) * | 1999-05-28 | 2000-11-29 | Sharp Kabushiki Kaisha | Shift register and image display apparatus using the same |
| JP2002055647A (en) * | 2000-08-09 | 2002-02-20 | Seiko Epson Corp | Dataline drive circuit, scanning line drive circuit, optoelectronic panel and electronic equipment |
| CN1388509A (en) * | 2001-05-24 | 2003-01-01 | 精工爱普生株式会社 | Scanning drive circuit, display, electrooptical apparatus and scanning drive method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1553703A (en) | 2004-12-08 |
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