CN1320775C - Circuit for eliminating signal amplitude mismatch on orthogonal signal path - Google Patents
Circuit for eliminating signal amplitude mismatch on orthogonal signal path Download PDFInfo
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- CN1320775C CN1320775C CNB200410037724XA CN200410037724A CN1320775C CN 1320775 C CN1320775 C CN 1320775C CN B200410037724X A CNB200410037724X A CN B200410037724XA CN 200410037724 A CN200410037724 A CN 200410037724A CN 1320775 C CN1320775 C CN 1320775C
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Abstract
The present invention relates to a circuit for eliminating signal amplitude mismatches in orthogonal signal pathways, which belongs to the technical field of the analogue signal processing and communication technology. The circuit comprises: two power detectors which are respectively connected with the signal output ends of the I pathway and the Q pathway of the orthogonal signal pathways and used for respectively detecting the output power of the I pathway and the Q pathway, a subtracter which is simultaneously connected with the output ends of the two power detectors and used for calculating the power difference between the I pathway and the Q pathway, a VGA control signal generator which is connected with the output end of the subtracter and used for generating the VGA gain control signals of the I pathway and the Q pathway to adjust the gain of the VGA and enable the output signal power of the I pathway and the Q pathway to be equal. The present invention can solve the problem of the amplitude mismatch of the orthogonal signals in a receiver, and has the advantages of enhancing technology tolerance and reducing communication code error rate.
Description
Technical field
The invention belongs to analog and communication technical field, particularly eliminate the circuit design of IQ two paths of signals amplitude mismatch.
Background technology
If frequency, demodulation frequency is modulated and the signal of phase modulated, to use the mode of quadrature demodulation usually, to solve contained frequency of signal and phase information.Modulation signal is downconverted to base band by local quadrature oscillator signal, is divided into I, Q two-way (real part and the imaginary part of representation signal respectively) processing, becomes digital signal.Not not matching of local oscillated signal quadrature output, the device mismatch that I, Q two-way produce in manufacture process, both of these case all can cause the amplitude mismatch of I, Q two link signals, and it is analog-to-digital accurate to influence.What Fig. 1 was given is a common zero intermediate frequency quadrature demodulation receiver.The rf modulated signal that receives is amplified by low noise amplifier (LNA), be divided into the IQ two-way and downconverted to baseband signal by frequency mixer (Mixer), pass through filter (LPF), variable gain amplifier (VGA), low pass filter (LPF) more respectively and handle, send into digital to analog converter at last.Local oscillator (LO) output orthogonal signal wherein, frequency equates with the centre frequency of radiofrequency signal.As example, the problem of I, Q two paths of signals amplitude mismatch can be described, among the figure, if the orthogonal signalling amplitude of local oscillator (LO) output does not match, perhaps because the deviation of technology, make quadrature two links (the I road among Fig. 1, Q road) go up device mismatch, these will cause the amplitude mismatch of baseband signal.
In the present CMOS technology, if the symmetry of strict consideration circuit layout still can only be controlled at amplitude mismatch in the 0.5dB scope.The reason that no matter produces how, do not match if be input to the two-way orthogonal signalling amplitude of analog to digital converter, can improve the error rate and the Packet Error Ratio of receiver greatly.
Solving the scheme of amplitude mismatch at present, mainly is to mate as far as possible by domain to reduce.But, can not solve the problem of amplitude mismatch because process deviation always exists at all.
Summary of the invention
The objective of the invention is in order to overcome the weak point of prior art, propose erasure signal amplitude mismatch circuit on a kind of orthogonal signal channel, can solve the amplitude mismatch problem of orthogonal signalling in the receiver preferably.And have the raising process allowance, reduce the advantage of the communication error rate.
Technical scheme of the present invention comprises: be connected to the I road of orthogonal signal channel and two power detectors of Q road signal output part, be used for detecting respectively the power output of I, Q two-way; While and the subtracter that the output of these two power detectors links to each other, be used to calculate power poor on I road and Q road; A VGA control signal generator that links to each other with the output of this subtracter is used to produce the gain control signal of I road and Q road VGA, with this gain of adjusting VGA, I, Q two-way output signal power is equated.
Characteristics of the present invention and technique effect:
The present invention measures and eliminates the amplitude mismatch of IQ two paths of signals with circuit mode, than traditional realize coupling by the domain coupling fully, more can effectively eliminate mismatch, have more reliability.Amplitude mismatch is brought up to 0.1dB by traditional 0.5dB.Can be widely used in the quadrature demodulation link.
Description of drawings
Fig. 1 is common zero intermediate frequency reciver structure chart.
Fig. 2 is the circuit general structure schematic diagram of erasure signal amplitude mismatch of the present invention.
Fig. 3 eliminates orthogonal signalling amplitude mismatch embodiment of circuit structural representation for the present invention.
Fig. 4 is a circuit embodiments structural representation of VGA control signal generator of the present invention (VcGen).
Fig. 5 is for using the zero intermediate frequency reciver structure chart that the present invention realizes automatic gain control.
Embodiment
The circuit of erasure signal amplitude mismatch reaches embodiment in conjunction with the accompanying drawings and is described in detail as follows on the orthogonal signal channel that the present invention proposes:
The present invention at first utilizes power detection module to detect the power output of two-way base band variable gain amplifier (VGA), calculated difference, thereby obtain a tolerance of amplitude mismatch, the gain that then utilizes this tolerance to adjust two-way VGA makes it to reach power output and equates.Further describe below in conjunction with accompanying drawing.
The circuit general structure of erasure signal amplitude mismatch of the present invention as shown in Figure 2.Power detector (power detector is sent in the VGA output of I, Q two-way respectively, PD), the detected performance number of two PD obtains difference through subtracter (Minus) and sends into VGA control signal generator (VcGen), and this VcGen produces and adjust the VGA gain control signal Vc (Vci among the figure and Vcq) of two-way according to this difference.Make circuit balancing, the VGA output of I, Q two-way equates.
Operation principle of the present invention: supposition I, Q two paths of signals amplitude equate (being that power equates), and VcGen is zero input at this moment, and its VD is as the gain control signal of VGA.If supposition I, Q two paths of signals amplitude is unequal, then use the difference (being proportional to the difference of amplitude) of I, Q two paths of signals power to adjust the direct current output of VcGen, reach the requirement of the power output that makes the VGA that I, Q two paths of signals amplitude equate.
Describe the circuit embodiments structure and the principle thereof of various piece below in detail.
Fig. 3 eliminates orthogonal signalling amplitude mismatch embodiment of circuit structural representation.VGA output in I road is divided into two-way, and one the tunnel through squarer (being designated as ^2 among the figure); Another road enters squarer more earlier through 90 ° of phase-shifters.Through adder (being designated as among the figure+), adder output is I road signal power (| I (t) | 2) to the signal of two squarers output as input.Same, Q road signal is output as Q road signal power ((| Q (t) | 2) through identical device.I road signal power (| I (t) | 2) and Q road signal power ((| Q (t) | 2) enter subtracter (Minus) as input, be output as poor (being proportional to the poor of amplitude) of two power, this difference enters VGA control-signals generator (VcGen) as input at last.
The embodiment of each power detector (PD) among Fig. 2 comprises two squarers, 90 ° of phase-shifters and an adder, wherein the input of first squarer directly links to each other with I or Q road signal output part, the input of second squarer links to each other with I or Q road signal output part by 90 ° of phase-shifters again, and the output of these two squarers all links to each other with an adder.The 90 ° of phase-shift circuits and the squarer of present embodiment are routine techniques, all can find in common analog circuit book, and the subtracter of present embodiment (Minus) is exactly a kind of of adder in fact, also can find.
The principle of this part circuit is described below:
Consider I, Q two paths of signals amplitude mismatch, the VGA output signal of I, Q two-way can be expressed as respectively:
I(t)＝Re{A
m·e
j(ωt+θ)} (1)
Q (t)=Re{ (A
m+ Δ A
m) e
The j pi/2E
J (ω t+ θ)(2) Δ A
mThe degree of expression amplitude mismatch.
Among Fig. 3, I, Q two paths of signals will be through 90 ° of phase shifts, again with original signal square summation, and the power detection part (PD) among Here it is Fig. 2.Can obtain:
The I road:
Re{A
m·e
j(ωt+θ)}
2+Re{A
m·e
jπ/2e
J(ωt+θ)}
2
＝A
m 2 (3)
The Q road:
Re{(A
m+ΔA
m)·e
jπ/2·e
j(ωt+θ)}
2+Re{(A
m+Δ
m)·e
jπ·e
j(ωt+θ)}
2
＝(A
m+ΔA
m)
2 (4)
Two results are subtracted each other (4)-(3) by subtraction circuit:
(A
m+ΔA
m)
2-A
m 2＝2A
mΔA
m+ΔA
m 2
≈2A
m·ΔA
m (5)
General, A
m＞＞Δ A
m
Like this, the input of VcGen is one and has been exaggerated 2A
mRange error Δ A doubly
mVcGen exports gain control signal Vci and the Vcq that controls I road and Q road VGA respectively thus.When reaching balance, should satisfy Δ A
m=0.
Fig. 4 is an embodiment electrical block diagram of VGA control signal generator of the present invention (VcGen).VcGen comprises that (present embodiment can adopt an adder and a subtracter to two adders, show its input polarity among the figure), four voltage-controlled current sources (present embodiment can adopt two PMOS pipes and two NMOS pipes to realize) and low pass filter (present embodiment can adopt electric capacity to realize).Its annexation is:
The first input end of two adders among Fig. 2 among the output of subtracter and Fig. 4 link to each other (the first input polarity of two adders is opposite), the output Vci of VcGen links to each other with second input of two adders with Vcq, and the output of two adders links to each other with the control end (i.e. the grid of metal-oxide-semiconductor among the figure) of two groups of voltage-controlled current sources respectively.Every group of voltage-controlled current source is made up of two voltage-controlled current sources in parallel, (present embodiment is that a PMOS pipe and a NMOS pipe are formed one group of voltage-controlled current source, wherein the drain terminal of two pipes links to each other and as output, the grid of two pipes links to each other with the output of adder simultaneously, the source termination power of PMOS pipe, the source end ground connection of NMOS pipe).The output of every group of voltage-controlled current source links to each other with the input of low pass filter (realizing with electric capacity among the figure), and the output of two low pass filters is as output Vci and the Vcq of VcGen.These two output voltage terminals are external to the gain control end of VGA on I, the Q two-way.
Above-mentioned adder, voltage-controlled current source, low pass filter are the analog circuit form of conventional criteria, all can find from book.
This part circuit theory is described below: follow the tracks of Δ A
mVariation, reach equilibrium condition Δ A
m=0, the VcGen module must realize such function.As shown in Figure 4.Suppose that the VGA output signal is a monotonic increasing function to the function of gain control signal Vc.If Δ A
m＞0, Vci rises so, and I road VGA output signal is strengthened; Vcq descends, and Q road VGA output signal weakens, until Δ A
m=0.Vice versa.
The example of an application of the present invention is described as follows:
Fig. 5 is for using the zero intermediate frequency reciver structure chart that the present invention realizes automatic gain control.The rf modulated signal that receives amplifies through low noise amplifier (LNA), be divided into the IQ two-way and downconverted to baseband signal by frequency mixer (Mixer), multiplied signals is the orthogonal signalling of local oscillator (LO) output, and its frequency equates with the centre frequency of radiofrequency signal.Pass through filter (LPF) afterwards respectively, amplified by variable gain amplifier (VGA).The output of I, Q two-way VGA can be adjusted to equal fully.They at first pass through power detector (PD) and calculate power, subtract each other to obtain the power difference again, and the VcGen module makes it equal according to looking for a difference to adjust the output of VGA.Last IQ two paths of signals is sent into digital to analog converter through low pass filter (LPF).
From the above mentioned, such circuit topological structure can be eliminated the orthogonal signalling amplitude mismatch, and is extremely helpful for the performance raising of receiver.
Claims (3)
1, erasure signal amplitude mismatch circuit on a kind of orthogonal signal channel is characterized in that, comprising: be connected to the I road of orthogonal signal channel and two power detectors of Q road signal output part, be used for detecting respectively the power output of I, Q two-way; While and the subtracter that the output of these two power detectors links to each other, be used to calculate power poor on I road and Q road; A VGA control signal generator that links to each other with the output of this subtracter is used to produce the gain control signal of I road and Q road VGA, with this gain of adjusting VGA, I, Q two-way output signal power is equated; Described VGA control signal generator comprises two adders, four voltage-controlled current sources and low pass filter; Its annexation is: the first input end of two adders links to each other with the output of subtracter, the first input polarity of these two adders is opposite, two outputs of VGA control signal generator link to each other with second input of two adders respectively, and the output of two adders links to each other with the control end of two groups of voltage-controlled current sources respectively; Every group of voltage-controlled current source is made up of two voltage-controlled current sources in parallel, and the output of every group of voltage-controlled current source links to each other with the input of low pass filter, and the output of two low pass filters is external to the gain control end of VGA on I, the Q two-way.
2, erasure signal amplitude mismatch circuit on the orthogonal signal channel as claimed in claim 1, it is characterized in that, described power detector comprises two squarers, 90 ° of phase-shifters and an adder, wherein the input of first squarer directly links to each other with I or Q road signal output part, the input of second squarer links to each other with I or Q road signal output part by 90 ° of phase-shifters again, and the output of these two squarers all links to each other with an adder.
3, erasure signal amplitude mismatch circuit on the orthogonal signal channel as claimed in claim 1, it is characterized in that, described one group of voltage-controlled current source is made up of a PMOS pipe and a NMOS pipe, wherein the drain terminal of this two metal-oxide-semiconductor links to each other and as output, the grid of two metal-oxide-semiconductors links to each other with the output of adder simultaneously, the source termination power of PMOS pipe, the source end ground connection of NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410037724XA CN1320775C (en) | 2004-05-10 | 2004-05-10 | Circuit for eliminating signal amplitude mismatch on orthogonal signal path |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410037724XA CN1320775C (en) | 2004-05-10 | 2004-05-10 | Circuit for eliminating signal amplitude mismatch on orthogonal signal path |
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| CN1571286A CN1571286A (en) | 2005-01-26 |
| CN1320775C true CN1320775C (en) | 2007-06-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100788638B1 (en) * | 2006-10-20 | 2007-12-26 | (주)에프씨아이 | Low if receiver reducing the image signal and the image signal rejection method used by the receiver |
| CN101420236B (en) * | 2007-10-24 | 2013-08-07 | 松下电器产业株式会社 | Local oscillation leakage detection and elimination apparatus and method |
| CN102710218B (en) * | 2012-06-05 | 2015-04-22 | 无锡市晶源微电子有限公司 | Self-adaptive demodulation module with fully-integrated frequency modulation (FM) |
| CN102868650B (en) * | 2012-09-13 | 2015-02-11 | 江苏物联网研究发展中心 | Orthogonal I/O (Input/Output) signal phase unbalance correcting circuit |
| CN117674752A (en) * | 2023-10-19 | 2024-03-08 | 四川鸿创电子科技有限公司 | Automatic gain control method, device and equipment for frequency agile chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6038268A (en) * | 1996-02-15 | 2000-03-14 | General Research Of Electronics, Inc. | Direct conversion FSK signal radio receiver |
| CN1398136A (en) * | 2001-07-12 | 2003-02-19 | 日本电气株式会社 | Radio transmitter and appliance for mobile station |
| CN1430335A (en) * | 2001-12-25 | 2003-07-16 | 株式会社东芝 | Radio receiver and radio receiving method |
-
2004
- 2004-05-10 CN CNB200410037724XA patent/CN1320775C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6038268A (en) * | 1996-02-15 | 2000-03-14 | General Research Of Electronics, Inc. | Direct conversion FSK signal radio receiver |
| CN1398136A (en) * | 2001-07-12 | 2003-02-19 | 日本电气株式会社 | Radio transmitter and appliance for mobile station |
| CN1430335A (en) * | 2001-12-25 | 2003-07-16 | 株式会社东芝 | Radio receiver and radio receiving method |
Non-Patent Citations (1)
| Title |
|---|
| DC Offset Canceller in a Direct Conversion Receiver forQPSKSignal Reception Hiroshi Yoshida,IEEE,Vol.0.7803.4872.9/98 1998 * |
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| CN1571286A (en) | 2005-01-26 |
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