CN1317825C - Apparatus and method for precisely controlling termination impedance - Google Patents
Apparatus and method for precisely controlling termination impedance Download PDFInfo
- Publication number
- CN1317825C CN1317825C CNB2004100747834A CN200410074783A CN1317825C CN 1317825 C CN1317825 C CN 1317825C CN B2004100747834 A CNB2004100747834 A CN B2004100747834A CN 200410074783 A CN200410074783 A CN 200410074783A CN 1317825 C CN1317825 C CN 1317825C
- Authority
- CN
- China
- Prior art keywords
- impedance
- generator
- voltage
- terminal
- programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 44
- 229910002056 binary alloy Inorganic materials 0.000 claims description 19
- 230000001105 regulatory effect Effects 0.000 claims description 17
- 230000008878 coupling Effects 0.000 claims description 15
- 238000010168 coupling process Methods 0.000 claims description 15
- 238000005859 coupling reaction Methods 0.000 claims description 15
- 230000001276 controlling effect Effects 0.000 claims description 12
- 238000012163 sequencing technique Methods 0.000 claims description 11
- 230000000737 periodic effect Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 2
- 230000008676 import Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 244000287680 Garcinia dulcis Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
- Networks Using Active Elements (AREA)
- Programmable Controllers (AREA)
Abstract
An impedance controller that controls termination impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one termination logic element, and an impedance matching controller. The programmable reference impedance generator develops a reference impedance controlled by a reference impedance control input. Each termination logic element includes a programmable termination impedance generator coupled to a corresponding output and controlled by termination impedance control input. The impedance matching controller continually adjusts the reference impedance control input to match the reference impedance with the reference value within a predetermined tolerance and generates the termination impedance control input based on the reference impedance control input.
Description
Technical field
The present invention relates to a kind of IC output driving circuit, and particularly relate to the method and apparatus that draws the accurate control terminal impedance of impedance (precise on-chip bus pull-up impedance) on the accurate chip internal bus of a kind of N of being provided for passage drain open circuit output driver (N-channel open drain output driver).Wherein the impedance of bus is to the variation of temperature and voltage, and the variation that manufacturing variation is established is insensitive.
Background technology
Integrated (integrated promptly long-pending body in early days, below all be called integrated) in circuit (IC) design, the CMOS output driver is designed to push-pull type (push-pull element) element and causes the noise (noise) of output bus (bus is a bus-bar, below all be called bus) to be subjected to the influence fluctuation of various factors very big.These factors comprise: the quantity of element on the difference of circuit temperature, supply voltage, manufacturing process, the bus, or the like.In recent years, along with the raising of technical level, component size and voltage quasi position constantly reduce, and the designer pays much attention to the noise problem of external bus, to reach the maximized raising of the service speed of circuit in the system.Typical bus is included in the one or more holding wires that are gathered together straight line on the system board, and each holding wire can be used as the transmission line model that is subjected to noise (for example: reflection, cross-talk etc.) influence.
One of output driver solution that industrial circle occurs recently is by the transformation of push-pull type export structure to differential receiver (differential receiver) structure.In a differential receiver structure, a side of a differential receiver is supplied to a reference voltage, and drain N pass element drives and opposite side is opened a way.Tradition on system host board or suchlike open circuit drain N pass element be to be provided on the chip (chip is a wafer, below all be called chip), and draw terminal generally to be provided at the outside on the bus.The grade of drawing terminal to give system designer addressing bus neatly noise problem is being provided on the motherboard.
In recent years, the output driver of above-mentioned several types gradually becomes main flow in industrial circle.For example, Pentium II (Pentium II) the x86 microprocessor of Ying Daier company (Intel Corporation).Adopt drain open circuit N passage output element to drive among the Pentium II and have the 1.5V bus of 1.0V critical reference value (reference threshold).The motherboard of this processor draws terminal on generally adopting 56 ohm.Although do not stipulate concrete pull-down impedance, drain open circuit output driver is used, requires (timing specification) to meet bus switch and sequential.Yet, processing, voltage and variations in temperature not being compensated, the aisle resistance of drain open circuit N passage output driver can change between about 4～80 ohm.Because the designer of microprocessor can only predict the permission fluctuation range of processing procedure, voltage, temperature, it is forced in the design of the compatible motherboard of Pentium II, increase rate of change (slew rate) control of how second order of 2-3, and then the output signal character reduces the noise on output bus.
Ying Daier has introduced a kind of device in Pentium III , this device can be used for setting the impedance of output driver on the bus for the designer provides a reference impedance (reference impedance).It is that 14 ohm of precision resistances of 16 ohm insert the bus voltage that is called as VTT by a maximum prescribed resistance that processor encapsulates a pin that is called as NCHCTRL.This precision resistance is positioned at the outside of little process chip, therefore with chip in the temperature and the change in voltage of output driver irrelevant.In addition, will draw terminal to be arranged in the chip on the compatible structure rather than on the system board.And being provided with a pin that is called as RTT, this pin is by a precision resistance R ground connection.The impedance of this precision resistance shows the expectation impedance of drawing terminal on all.Therefore, system designer can be determined to draw impedance on the bus of all signals by an outer meeting resistance.The specification of this resistance can be in 40～130 ohm scope, makes system designer to draw terminal on the adjusting N passage drain open bus, and noise or load are compensated.
This shows that the method for above-mentioned existing control terminal impedance and device obviously still have inconvenience and defective, and demand urgently further being improved in method and use.For method that solves the control terminal impedance and the problem of installing existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and the method and the device of general control terminal impedance do not have appropriate method and structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the method for above-mentioned existing control terminal impedance and device exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of method and device of accurate control terminal impedance newly, can improve the method and the device of general existing control terminal impedance, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing impedance controller exists, and provide a kind of new impedance controller, technical problem to be solved is to make it be suitable for the terminal impedance of accurate control transmission line, with the difference of compensation temperature, voltage and manufacturing process, thereby be suitable for practicality more.
A further object of the present invention provides a kind of integrated circuit, can reach the terminal resistance to each final element on the integrated circuit, regulates continuously in obvious mode in operation, thereby is suitable for practicality more.
Another purpose of the present invention provides a kind ofly controls the method for drawing terminal impedance at least one output according to reference resistance, monitors and regulate terminal impedance sustainably, with the basic operation of easier grasp circuit, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of impedance controller according to the present invention's proposition, it is the terminal impedance of controlling at least one output according to a reference value, it comprises: (sequencing is a formula to a programmable, below all be called program) the reference impedance generator, in order to produce a reference impedance that controlled by reference impedance control input; At least one terminal logic element, each this terminal logic element comprises a programmable terminal impedance generator, wherein this programmable terminal impedance generator and a corresponding output couple, and are subjected to the control of termination impedance control input; And an impedance matching controller, interruptedly do not regulate this reference impedance control input, so that the gap of this reference impedance and this reference value is in a predetermined allowable deviation, and produce the input of this termination impedance control according to this reference impedance control input.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid impedance controller, wherein said programmable reference impedance generator and each this at least one programmable terminal impedance generator comprise that (array is an array to a binary system array of mating the P pass element, below all be called array), and this programmable reference impedance generator each in this at least one programmable terminal impedance generator all provides on relevant with a supply voltage one and draws impedance with all.
Aforesaid impedance controller, wherein said impedance matching controller comprises: a voltage-sensor, voltage difference between the reference voltage that produces in order to this reference element of sensing and the voltage of this programmable reference impedance generator, and setting corresponds to tell-tale error signal of this voltage difference; And an impedance Control logic, regulate this reference impedance control input according to this error signal.
Aforesaid impedance controller, wherein said reference value comprises a reference resistor, wherein a voltage source is applied in this reference resistor and this programmable reference impedance generator, wherein this reference resistor is to couple at an intermediate contact and this programmable reference impedance generator, and wherein this voltage-sensor is set this error signal, so that the gap between the voltage of this intermediate contact and 1/2nd these voltage source voltages is within a predictive error voltage range.
Aforesaid impedance controller, wherein said impedance Control logic receives a clock pulse signal, and during the selected cycle of this clock signal this reference impedance control input is increased or reduces.
Aforesaid impedance controller, wherein said impedance matching controller also comprise an offset adjusted logic, combine in order to a deviant is imported with this reference impedance control, and this termination impedance control input is provided.
Aforesaid impedance controller, it more comprises an output offset logic of sequencing, in order to this deviant to be provided.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of integrated circuit (IC) that the present invention proposes, it comprises: most pins, comprise one with reference to pin and at least one output connecting pin, and this is in order to be coupled to an external reference resistor with reference to pin; At least one terminal logic element, each this terminal logic element comprises a programmable terminal impedance generator, is subjected to the control of termination impedance control input, and couples with corresponding this at least one output connecting pin; And an impedance matching logic, comprising: a programmable reference impedance generator is subjected to the control of reference impedance control input; One comparator logic is not interruptedly regulated this reference impedance control input, so that the value of this reference resistor and this programmable reference impedance generator differs in a predetermined permissible range; And an outlet terminal logic, in order to according to this this termination impedance control input of reference impedance control input control.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid integrated circuit, it more comprises: an output offset logic, in order to a regulated value to be provided; And this outlet terminal logic comprises an offset adjusted logic, in order to couple this reference impedance control input and this regulated value, so that this terminal references control input to be provided.
Aforesaid integrated circuit, wherein said programmable reference impedance generator and each this programmable terminal impedance generator comprise a binary system array of a coupling P channel impedance device.
Aforesaid integrated circuit, wherein said comparator logic comprises: a voltage-sensor, be coupled to this with reference to pin and this programmable reference impedance generator, cross over the voltage of this reference resistor and this programmable reference impedance generator in order to detection, and establish a tell-tale error signal; And a reference impedance logic, in order to regulate this reference impedance control input according to this error signal.
Aforesaid integrated circuit, wherein a reference voltage is applied in leap at this reference resistor that is connected in series mutually by a contact and this programmable reference impedance generator, and when the gap between the voltage of this contact and 1/2nd these reference voltages was within a predictive error voltage range, this voltage-sensor was established an error signal of indication usefulness.
Aforesaid integrated circuit, wherein said reference impedance control input comprises that (numeral is a numerical digit to a numeral, below all be called numeral) value, wherein should receive a clock pulse signal and in the selected cycle of this clock signal this reference impedance be controlled input with reference to control logic increases or reduces.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of method of drawing terminal impedance at least one output of controlling according to reference resistance according to the present invention's proposition, it may further comprise the steps: this reference resistance and a reference impedance generator in serial connection apply a reference voltage, and this reference impedance generator has reference impedance input; The input of this reference impedance of periodic adjustment is controlled in the predetermined permissible range with the gap with the voltage of reference impedance generator and reference resistance; And the terminal impedance input of drawing the impedance generator at least one according to this reference impedance input control, draw the impedance generator to couple mutually on each with a corresponding output.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaidly control the method for drawing terminal impedance at least one output according to reference resistance, it more may further comprise the steps: the voltage of the contact between this reference impedance generator of sensing and the reference resistance; And periodic adjustment comprises 1/2nd of the voltage of intermediate contact and this reference voltage is compared.
Aforesaidly control the method for drawing terminal impedance at least one output according to reference resistance, this reference impedance input of wherein said periodic adjustment is included in the selected clock pulse cycle increase and the minimizing to a digital value.
Aforesaidly control the method for drawing terminal impedance at least one output according to reference resistance, it more may further comprise the steps: sequencing one offset adjusted numerical value; And by controlling terminal impedance input in conjunction with this offset adjusted value and this reference impedance input.
Aforesaidly control the method for drawing terminal impedance at least one output according to reference resistance, it more may further comprise the steps: a binary system array that starts selected reference impedance generator coupling P pass element according to this reference impedance input; And according to this terminal impedance input starts a binary system array of drawing impedance generator coupling P pass element on selected each.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention proposes a kind of impedance controller, and it is a terminal impedance of controlling at least one output according to a reference value, and this impedance controller comprises a programmable reference impedance generator, at least one terminal logic element and an impedance matching controller.This programmable reference impedance generator is being set up reference group when anti-, is to be controlled by reference impedance control input.Each terminal logic element comprises that a programmable terminal impedance generator couples mutually with corresponding output, and is subjected to the control of termination impedance control input.Impedance matching controller is constantly regulated reference impedance control input, reference impedance and reference value can be mated in a permissible error scope of being scheduled to, and produce termination impedance control input according to this reference impedance control unit.
In one embodiment of this invention, this programmable reference impedance generator and each programmable terminal resistance generator all comprise the binary system array of a coupling P pass element.In one embodiment of this invention, each impedance generator provides and draws impedance on relevant with a source voltage.Impedance matching controller can comprise a voltage-sensor and impedance Control logic.In this case, voltage-sensor detects the reference voltage of reference element establishment and the voltage difference of programmable reference impedance generator, and establishes a tell-tale rub-out signal.This rub-out signal of impedance Control logical foundation is regulated reference impedance control input.In one embodiment of this invention, this reference value corresponds to a reference resistor, and a voltage source be applied in this reference resistor and by an intermediate contact (junction) mutually series connection programmable reference impedance generator.This voltage source produces a rub-out signal, to point out the magnitude of voltage of transition joint with respect to the magnitude of voltage 1/2nd of voltage source.
In one embodiment of this invention, the impedance Control logic is received a clock pulse signal and is increased (increment) in the cycle or reduce (decrement) reference impedance control input at selected clock signal.Impedance matching controller also can further comprise offset adjusted logic (bias adjustment logic), and it combines side-play amount with reference impedance control input, so that the termination impedance control input to be provided.The output offset logic as programmable fuse (programmable fuse), provides this side-play amount with can being used to sequencing.
An integrated circuit comprises one with reference to pin (reference pin) according to an embodiment of the invention, itself and external reference resistance couple, and at least one output connecting pin (output pin), at least one terminal logic element (termination logic element) and an impedance matching logic.Each terminal logic element comprises a programmable terminal impedance generator, and it is subjected to the control of reference impedance control input and couples with corresponding output connecting pin.This impedance matching logic comprises a programmable reference impedance generator, and it is subjected to a reference impedance control input, comparator logic and outlet terminal logic control.This comparator logic is regulated reference impedance control input constantly, so that the value of reference resistor and programmable reference impedance generator reaches balanced in a predetermined permissible range.This outlet terminal logic basis reference impedance control input is controlled termination impedance control input.
This IC can comprise the output offset logic, and this output offset logic provides a regulated value, and in this case, the outlet terminal logic can comprise skew adjustment logic, and it is in conjunction with reference impedance control input and regulated value, so that this termination impedance control input to be provided.The binary system array that this programmable reference impedance generator and each programmable terminal impedance generator can be used as a coupling P channel impedance element realizes.
The present invention proposes a kind of method of drawing terminal impedance at least one output of controlling according to a reference resistance, may further comprise the steps: on a reference resistance of connecting and a reference impedance generator, apply a reference voltage, this reference impedance generator has reference impedance input, periodically input is regulated to reference impedance, so that the voltage of the voltage of reference impedance generator and reference resistance reaches balanced in a predetermined permissible range, and control the terminal impedance of drawing the impedance generator at least one according to reference impedance input and import, draw impedance generator and a corresponding output to couple on each.
This method may further include following steps: the voltage at the intermediate contact place of sensing reference impedance generator and reference resistance.In this case, this method can may further comprise the steps: 1/2nd of the voltage at intermediate contact place and reference voltage compared.Periodic adjustment to the reference impedance input can may further comprise the steps: digital value is increased or reduces in the cycle at selected clock signal.This method also can further may further comprise the steps: with an offset adjusted value sequencing, and in conjunction with offset adjusted value and reference impedance input.This method also can further may further comprise the steps: input starts the binary system array of the selected coupling P pass element of reference impedance generator according to reference impedance, and starts the binary system array of the selected coupling P pass element that draws the impedance generator on each according to terminal impedance input.
Via as can be known above-mentioned, the invention relates to a kind of impedance controller, it is a terminal impedance of controlling at least one output according to a reference value, comprises a programmable reference impedance generator, at least one terminal logic element and an impedance matching controller.This programmable reference impedance generator is by the reference impedance of reference impedance control input control.Each terminal logic element comprises a programmable terminal impedance generator that is coupled to a corresponding output, and is subjected to the control of termination impedance control input.This impedance matching controller continue to be regulated reference impedance control input, making reference impedance and reference values match in predetermined permissible range, and produces the termination impedance control input according to reference impedance control input.
In sum, the method and the device of the accurate control terminal impedance of the present invention provide a kind of impedance controller, are suitable for the terminal impedance of accurate control transmission line, can compensation temperature, the difference of voltage and manufacturing process.Simultaneously, the present invention also provides a kind of integrated circuit, can reach the terminal resistance to each final element on the integrated circuit, regulates continuously in obvious mode in operation.In addition, the present invention provides a kind of again and controls the method for drawing terminal impedance at least one output according to reference resistance, can monitor and regulate terminal impedance constantly, with the basic operation of easier grasp circuit.It has above-mentioned many advantages and practical value, and in class methods and device, do not see have similar design to publish or use and really genus innovation, no matter it is all having bigger improvement on method or on the function, have large improvement technically, and produced handy and practical effect, and the method for more existing control terminal impedance and device have the multinomial effect of enhancement, thereby are suitable for practicality more, really are a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Fig. 1 is the simple block diagram of integrated circuit (IC) of the system of according to a preferred embodiment of the present invention a kind of terminal impedance of comprising accurate control transmission line.
Fig. 2 is the more detailed block diagram of a kind of impedance matching logic according to a preferred embodiment of the present invention shown in Figure 1.
Fig. 3 is the schematic diagram of a kind of impedance generator of implementing according to one embodiment of the invention, and this impedance generator can be used for impedance generator shown in Figure 2, also can be used for shown in Figure 1 drawing logic element on arbitrary.
Fig. 4 be show according to a preferred embodiment of the present invention a kind of according to reference resistance control at least one output on draw the flow chart of the method for terminal impedance.
101: integrated circuit 103: the impedance matching logic
105: bus 107: on draw logic
109: output offset logical one 10: fuse
201: impedance controller 203: voltage-sensor
205: impedance Control logic 207: the impedance generator
209: offset adjusted logic 300: the impedance generator
303: the three arrays of 301: the second arrays
307: the five arrays of 305: the four arrays
401～413: each steps flow chart
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the method of the accurate control terminal impedance that foundation the present invention is proposed and install its embodiment, method, step, structure, feature and effect thereof, describe in detail as after.
The inventor recognizes, is necessary outside precision resistor is monitored, and to drawing final element to regulate on the bus on the chip, makes itself and the impedance phase coupling that draws by precision resistor.Therefore, this inventor has designed a kind of apparatus and method that are used for the terminal impedance of accurate control transmission line.Be elaborated below in conjunction with accompanying drawing 1～4.
Seeing also shown in Figure 1ly, is the simple block diagram of integrated circuit (IC) 101 according to a preferred embodiment of the present invention, comprises the system of the terminal impedance of an accurate control transmission line.IC 101 comprises most outside available I/O (I/O) pins, and it comprises a reference resistor pin RTT and a plurality of output connecting pin, in Fig. 1, be shown as output 1, output 2 ... output N, wherein N is a positive integer.Unless otherwise noted, certain signal to pin and transmission thereof claims with same title.Integrated circuit (IC) 101 or development are voltage reference signals or receive a reference voltage signal VDD.The VDD signal can be provided by an external pins relevant with ground connection (GND) pin (not shown).Among the embodiment shown in the figure, the external reference resistor R that dots is coupled between pin RTT and the ground.With regard to specification, resistor R and can be that (for example: 1% resistor), but the present invention is not subjected to the restriction of any characteristics numerical value, scope or resistor types to a precision resistor between 40～190 ohm.In addition, according to the present invention, also can provide the voltage except that VDD.For example, provide as above-mentioned VTT voltage.
IC 101 comprises impedance matching logical one 03, and it receives the VDD signal and monitors the external reference resistance R and the impedance of an internal driving generator 207 (as shown in Figure 2).Among the embodiment shown in the figure, the voltage quasi position of impedance matching logical one 03 monitoring RTT pin, and by the multiple terminals on 105 couples of IC 101 of 6 bit internal buss or on draw logic element 107 (counting separately) that one 6 bit digital value PSUM[5:0 are provided from 1～N].Draw logic element 107 to receive the VDD signals on each and couple with a corresponding output connecting pin OUTx (wherein " x " is any positive integer of 1～N, represents a specific output connecting pin).On each, draw in the logic element 107 each (bit) PSUM[5:0] the having shared drain point and be used to draw and stop the coupling P pass element array of a corresponding OUTx pin of value activation/forbidden energy correspondence.Digital value PSUM[5:0] be defined in the quantity of the P pass element that draws in the logic element 107 and be unlocked (or startup) on each, in the error range of regulation, draw or stop corresponding OUTx signal.Among the embodiment shown in the figure, digital value PSUM[5:0] allow with 64 equidistant steps will on draw the adjusting of the impedance of logic element.
In operation, impedance matching logical one 03 keep one with each on draw the identical coupling P pass element of two choosing system arrays in the logic element 107 the partial binary array.The binary system group that is used for digital output impedance control is all organized into groups or be divided into to each array, hereinafter also can describe in detail at this.The impedance of the partial binary array in the impedance matching logical one 03 is by continuous monitoring, and digital value PSUM[5:0] regulated up or down, so that the voltage of inner array is within the predetermined permissible range of the voltage on the resistor R.In one embodiment, predetermined permissible value is an error voltage that is approximately 50 millivolts (mv).On draw the optimum impedance of logic element 107 be at a bus clock pulse INT BCLK the selected cycle (for example: determine per 2 INT BCLK cycles) or upgrade, and on draw logic element 107 to be updated apparently.
The purpose that output offset logical one 09 is provided is the digital value PSUM[5:0 that provides on the bus 105] carry out addition or subtract each other skew.Provide one 4 bit value PADD[3:0 by output offset logical one 09 to impedance matching logical one 03], to determine a PSUM[5:0] addition or the numerical value that subtracts each other.Control signal PSUBEN by 09 pair of impedance matching logical one 03 of output offset logical one provides will still will subtract each other numerical value (when PSUBEN is established) with numerical value addition (when PSUBEN is not established) with definite.In one embodiment, numerical value PSUM[5:0] directly addition (for example: when PSUBEN be logical zero or when not being established) or deduct (for example: when PSUBEN be logical one or when being established) numerical value PADD[3:0].In another embodiment, numerical value PSUM[5:0] according to PADD[3:0] value and PSUNEN signal increase pro rata or reduce.For example, if PADD[3:0] be set as 1000b (binary system) and the PSUNEN signal is not established, PSUM[5:0 so] increase by 50%.
In one embodiment, output offset logical one 09 or comprise or by one group of fuse 110 sequencing of putting in IC 101.For example, the sequencing state of this group fuse 110 is determined item by item by a test program etc.This group fuse 110 in except that one, all the other all with numerical value PSUM[5:0] low level corresponding.By this way, the designer can increase or reduce PSUM[5:0 by the selected fuse of fusing] value.Output offset logical one 09 is a controlling organization, and the designer can be compensated the processing deviation of IC 101.
Seeing also shown in Figure 2ly, is the more detailed block diagram of impedance matching logical one 03 according to a preferred embodiment of the present invention.Impedance matching logical one 03 comprises an impedance controller 201, and it receives INTBCLK, VDD and RTT signal.R controller 201 comprises a voltage-sensor 203, and it receives the VDD signal, and the voltage of monitoring RTT pin, shows with signal INP in the part.This INP signal is provided for impedance generator 207, and this impedance generator 207 is according to one 6 bit input controlling value SUM[5:0] impedance is provided between VDD and INP signal.203 couples of VDD of voltage-sensor and INP voltage of signals are carried out effective ratio, and produce signal HI and LO offers impedance Control logic 205, in a predetermined permissible range, reach balanced (promptly make the two gap in a predetermined permissible range) to attempt voltage quasi position with impedance generator 207 and resistor R.Impedance Control logic 205 response HI/LO signal logarithm value SUM[5:0] increase/reduce, and the impedance of impedance generator 207 controlled, up to VDD-INP=INP within predetermined error voltage (or making the INP voltage of signals be positioned at the predetermined error voltage of plus-minus of two of vdd voltage/again and again).In other words, voltage-sensor 203 and impedance Control logic 205 are worked in coordination, so that the impedance (passing through voltage) of impedance of impedance generator 207 (passing through voltage) and resistor R (by wrong voltage amount) in predetermined permissible range reaches balanced.
The VDD supply voltage is thought that by the impedance dividing potential drop of resistor R and impedance generator 207 the INP signal provides an intermediate voltage.If the INP voltage of signals is too high, then represent the impedance too low (or less than R) of impedance generator 207, voltage-sensor 207 is established the HI signal and is made the LO signal for negative so.Impedance Control logic 205 is by to SUM[5:0] reduce and give a response, to increase the impedance of impedance generator 207.When the INP signal is too low, represent that then the impedance phase of impedance generator 207 is too high for resistor R, voltage-sensor 203 is established the LO signal, and makes the HI signal for negative.Impedance Control logic 205 is by to SUM[5:0] increase and give a response, to reduce the impedance of impedance generator 207.In the present embodiment, although also consider to have proportionate relationship, numerical value SUM[5:0] be inversely proportional to the impedance of impedance generator 207.
In one embodiment, voltage-sensor 203 comprises a pair of sensing amplifier (not shown), and it has the reference voltage setting that differs predictive error voltage with 1/2nd of VDD respectively.In this case, a high sensing amplifier has a set point that is approximately the error voltage on the 1/2VDD, being used to the controlling HI signal, and a low sensing amplifier has a set point that is approximately the error voltage under the 1/2VDD, to be used to control the LO signal.Each sensing amplifier compares the voltage and the INP voltage of signals of relative set point.If being elevated to the amount that exceeds VDD, the INP voltage of signals surpasses 1/2nd of error voltage, then establish the HI signal, if dropping to the amount that is lower than VDD, the INP signal is lower than 1/2nd of error voltage, then establish the LO signal, if and the difference of INP and 1/2VDD error voltage 1/2nd within, then do not establish the HI signal, do not establish the LO signal yet, and any action does not take place.Predictive error voltage is approximately 50mV more specifically among the embodiment at one, and high like this sensing amplifier is set on the 1/2VDD approximately 25mV, and low sensing amplifier is set under the 1/2VDD approximately 25mV.In order to obtain higher precision, the allowable limit of a strictness can be set for the gap of error voltage, otherwise, the allowable limit of a broad can be set in order to save electric energy.
In one embodiment, impedance Control logic 205 is digital circuits, by INT BCLK signal controlling, and in the selected INT BCLK signal period, such as in each signal period or in a signal period, logarithm value SUM[5:0] regulate (for example: increase and reduce).
With INT BCLK and SUBEN signal, numerical value PADD[5:0] and numerical value SUM[5:0] offer offset adjusted logic 209, by its output PSUM[5:0] value.At selected clock signal INT BCLK in the cycle, as every a clock signal, offset adjusted logic 209 is according to numerical value PADD[3:0] and control signal PSUBEN to PSUM[5:0] value regulate (for example: increase or minimizing).As previously mentioned, in one embodiment, numerical value PADD[3:0] with numerical value SUM[5:0] or addition or subtract each other, and in another embodiment, numerical value SUM[5:0] according to PADD[3:0] value increase in proportion or reduce.Final result is established by offset adjusted logic 209, i.e. numerical value PSUM[5:0 on the bus 105 of IC101].At this, numerical value PADD[3:0] can be considered numerical value SUM[5:0] bias voltage adjust version.
Seeing also shown in Figure 3ly, is the schematic diagram of a kind of impedance generator 300 of implementing according to one embodiment of the invention, and this impedance generator promptly can be used for impedance generator 207, and/or is used for drawing logic element 107 on arbitrary.Impedance generator 300 comprises the binary system array of a 63P pass element P1-P63.In one embodiment, each P pass element P63:P1 mates, so drain is same to the impedance phase of source electrode.The source electrode and the VDD of the element of each element P63:P1 couple, and drain and on draw signal PUP to couple, on draw signal PUP represent impedance generator 207 the INP signal or arbitrary on draw the corresponding OUTx signal of logic element 107.When adopting impedance generator 207, element P63:P1 is by with corresponding each 6 bit binary system impedance value XSUM[5:0] carry out the binary system marshalling, represent numerical value SUM[5:0], and when drawing logic element 107 in the employing any, then represent numerical value PSUM[5:0].First array is an individual component P1, it has the gate of a received signal PS0, second array 301 comprises 2 element P2 and P3 (P3:P2), its each element has the gate of received signal PS1, the 3rd array 303 comprises 4 element P4～P7 (P7:P4), its each element has the gate of received signal PS2, the 4th array 305 comprises 8 element P8～P15 (P15:P8), its each element has the gate of received signal PS3, one the 5th array 307 comprises 16 element P16～P31 (P31:P16), its each element has the gate of received signal PS4, comprise 32 element P32～P63 (P63:P31) with the 6th array 309, its each element has the gate of received signal PS5.
A common binary digit value of sending by a buffer 301, the buffer 301 reception numerical value XSUM[5:0 of forming of PS5-PS0 signal].Each PS5-PS0 signal all is XSUM[5:0] corresponding buffer stage.For example, the XSUM5 bit that is cushioned can be in order to producing the PS5 signal, and the XSUM4 position that is cushioned can be in order to producing PS4 position or the like, and the like.Like this, as numerical value XSUM[5:0] when being increased, the impedance between VDD and the PUP signal descends, vice versa.For example, the XSUM[5:0 of a 100000b] numerical value starts half (or 32) of the about P pass element of array 309 coupled in parallel, and the XSUM[5:0 of a 100010b] numerical value starts 34 or the like of array 303 and 309 coupled in parallel P pass elements, and the like.The XSUM[5:0 of a 000000b] close all P pass elements and be high impedance status, and numerical value 111111b starts all 63 of P pass elements and is the lowest impedance level.In one embodiment, the array of element P63:P1 is arranged by size and is divided into groups, provide a scope between about 20～150 ohm, to draw impedance with operating temperature and bus voltage condition and range, and make allowances for the difference of manufacturing process of expection expection.
See also shown in Figure 4, be show according to a preferred embodiment of the present invention according to a reference resistance control at least one output on draw the flow chart of the method for terminal impedance.In first frame 401, with an optional offset adjusted value sequencing.In an aforesaid IC embodiment, it is with the selected fuse failure in the IC 101, to provide a kind of controlling mechanism to be used to compensate the process variations of IC 101.In next frame 403, a reference impedance generator with reference impedance input and reference resistance is applied a reference voltage.Among the embodiment shown in the figure, reference voltage can be a voltage source, as the VDD signal etc., is applied in the reference resistance and the reference impedance input of series connection.
In next frame 405, reference impedance input is by periodically (for example: regulate continuously), the impedance that makes the reference impedance generator and the gap of reference resistance are in the permissible range of being scheduled to.In embodiment as shown in the figure, the voltage at the intermediate contact place between reference resistance and the reference impedance generator is sensed, and with reference voltage (for example: 1/2nd comparing VDD).In next frame 407, input starts the binary system array of selected reference impedance generator matched impedance element according to reference impedance.In illustrated embodiment, the reference impedance input is a digital value, and wherein every bit starts the selected array of a coupling P pass element.
In next frame 409, according to reference impedance input control terminal impedance input, this terminal impedance input offers draws the impedance generator on each that couples with corresponding output.If with an offset adjusted value sequencing, this offset adjusted value then combines with the reference impedance input, to regulate the terminal impedance input at next frame 411.In illustrated embodiment, offset adjusted logic 209 is with numerical value PADD[5:0] with numerical value SUM[5:0] combine (add, subtract, or other combinations), to produce numerical value PSUM[5:0], and be sent to and draw logic element 107 on each.In next frame 413, start the binary system array of drawing impedance generator matched impedance element on selected according to terminal impedance input.As previously mentioned, draw logic element 107 to comprise the same structure of the P pass element that mates as reference impedance generator 207 on each, the basis of drawing terminal impedance like this in the output is that reference impedance and any output offset are regulated.
According to the terminal resistance of the described impedance controller of each embodiment of the present invention, regulate continuously in obvious mode in operation each final element on the IC.Terminal impedance is monitored constantly and is regulated, and with the difference of compensation temperature, voltage and manufacturing process, the method that is adopted is to grasp easily for the basic operation of circuit.The fluctuation of VDD signal is to the not influence of terminal impedance of output, because change to take place with the proportional mode of INP signal.The benefit that resistance R provides is the variations in temperature that is independent of IC 101.
Although the explanation of the present invention being carried out according to preferred forms still can be made other to invention and shift gears.For example, can adopt the impedance of the balanced programmable impedance of diverse ways generator 207 and reference resistor, such as current technique or equivalence techniques etc.Also have, although disclose use metal-oxide semiconductor (MOS) (MOS at this, metal-oxide semiconductor) element of type, comprise complementary type MOS element, as, NMOS and PMOS transistor etc., the present invention can also be applied in the technology and the field of difference or similar type in a similar fashion, as bipolar cell etc.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1, a kind of impedance controller according to a reference value, is controlled the terminal impedance of at least one output, it is characterized in that comprising:
One programmable reference impedance generator is in order to produce a reference impedance that controlled by reference impedance control input;
One terminal logic element, this terminal logic element comprise a programmable terminal impedance generator, and wherein this programmable terminal impedance generator and a corresponding output couple, and are subjected to the control of termination impedance control input; And
One impedance matching controller, utilize this reference impedance control input, be coupled to this programmable reference impedance generator, utilize this termination impedance control input, be coupled to this terminal logic element, and interruptedly do not regulate this reference impedance control input,, and produce the input of this termination impedance control according to this reference impedance control input so that the gap of this reference impedance and this reference value is in a predetermined allowable deviation.
2, impedance controller according to claim 1, it is characterized in that wherein said programmable reference impedance generator and this programmable terminal impedance generator comprise, according to the binary system array, a plurality of coupling P pass elements that arrangement forms, and this programmable reference impedance generator and this programmable terminal impedance generator all provide one to draw impedance on relevant with supply voltage.
3, impedance controller according to claim 1 is characterized in that wherein said impedance matching controller comprises:
One voltage-sensor, the voltage difference between a reference voltage that produces in order to sensing one reference element and the voltage of this programmable reference impedance generator, and set an indicative error signal, to react this voltage difference; And
One impedance Control logical circuit is regulated this reference impedance control input according to this indicative error signal.
4, impedance controller according to claim 3, it is characterized in that more comprising that a reference resistor is to provide described reference value, wherein this reference resistor is coupled in this programmable reference impedance generator, and produce a junction, and there is a voltage source to be applied to the input of this programmable reference impedance generator, and wherein this indicative error signal indicate this junction voltage whether with the gap of this voltage source voltage, within a predictive error voltage range.
5, impedance controller according to claim 3 is characterized in that wherein said impedance Control logical circuit receives a clock pulse signal, and during the selected cycle of this clock signal this reference impedance control input is increased or reduces.
6, impedance controller according to claim 1 is characterized in that wherein said impedance matching controller also comprises an offset adjusted logical circuit, combines in order to a deviant is imported with this reference impedance control, and this termination impedance control input is provided.
7, impedance controller according to claim 6 is characterized in that more comprising an output offset logical circuit of sequencing, in order to another deviant to be provided.
8, a kind of integrated circuit (IC) is characterized in that comprising:
A most pin comprise one with reference to a pin and an output connecting pin, and this is in order to be coupled to an external reference resistor with reference to pin;
One terminal logic element comprises a programmable terminal impedance generator, is subjected to the control of termination impedance control input, and couples with corresponding this output connecting pin; And
One impedance matching logical circuit comprises:
One programmable reference impedance generator is subjected to the control of reference impedance control input;
One comparator logic circuit is not interruptedly regulated this reference impedance control input, so that the resistance value of the resistance value of this external reference resistor and this programmable reference impedance generator differs in a predetermined permissible range; And
One outlet terminal logical circuit is in order to import according to this this termination impedance control of reference impedance control input control.
9, integrated circuit according to claim 8 is characterized in that more comprising:
One output offset logical circuit is in order to provide a regulated value; And
This outlet terminal logical circuit comprises an offset adjusted logical circuit, in order to receive this reference impedance control input and this regulated value, so that this terminal references control input to be provided.
10, integrated circuit according to claim 9 is characterized in that wherein said programmable reference impedance generator and this programmable terminal impedance generator comprise, according to the binary system array, arranges a plurality of coupling P channel impedance devices that form.
11, integrated circuit according to claim 8 is characterized in that wherein said comparator logic circuit comprises:
One voltage-sensor is coupled to this with reference to pin and this programmable reference impedance generator, crosses over the voltage of this reference resistor and this programmable reference impedance generator in order to detection, and establishes a tell-tale error signal; And
One reference impedance logical circuit is in order to regulate this reference impedance control input according to this error signal.
12, integrated circuit according to claim 11, it is characterized in that wherein this external reference resistor is coupled in this programmable reference impedance generator and produces a junction, and there is a voltage source to be applied to the input of this programmable reference impedance generator, and wherein this tell-tale error signal indicate this junction voltage whether with the gap of this voltage source voltage, within a predictive error voltage range.。
13, integrated circuit according to claim 11, it is characterized in that wherein said reference impedance control input comprises a digital value, wherein this reference impedance logical circuit receives a clock pulse signal and in the selected cycle of this clock signal this reference impedance control input is increased or reduces.
14, a kind of according to the method for drawing terminal impedance in reference resistance control one output, it is characterized in that it may further comprise the steps:
Apply a reference voltage on this reference resistance that is connected in series and a reference impedance generator, this reference impedance generator has reference impedance input;
This reference impedance input of periodic adjustment is to be scheduled to the voltage difference of this reference impedance generator and this reference resistance in the permissible range apart from being controlled at one; And
According to the terminal impedance input of drawing the impedance generator in this reference impedance input control one, each draws the impedance generator to couple mutually with a corresponding output on being somebody's turn to do.
15, according to claim 14 according to the method for drawing terminal impedance in reference resistance control one output, it is characterized in that more may further comprise the steps:
The voltage of the contact between this reference impedance generator of sensing and this reference resistance; And
The voltage at the intermediate contact place between this reference impedance generator of periodic adjustment and this reference resistance, and compare with 1/2nd of this reference voltage.
16, according to claim 14 according to the method for drawing terminal impedance in reference resistance control one output, it is characterized in that this reference impedance input of wherein said periodic adjustment is included in interior increase and minimizing to a digital value of a selected clock signal cycle.
17, according to claim 14 according to the method for drawing terminal impedance in reference resistance control one output, it is characterized in that more may further comprise the steps:
Sequencing one offset adjusted numerical value; And
By controlling terminal impedance input in conjunction with this offset adjusted value and this reference impedance input.
18, according to claim 14 according to the method for drawing terminal impedance in reference resistance control one output, it is characterized in that it more may further comprise the steps:
According to this reference impedance input, be enabled in this reference impedance generator, according to the binary system array, arrange the coupling P pass element that forms; And
According to this terminal impedance input, be enabled in and draw on this in impedance generator, according to the binary system array, arrange the coupling P pass element that forms.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/730,169 | 2003-12-06 | ||
| US10/730,169 US6985008B2 (en) | 2002-12-13 | 2003-12-06 | Apparatus and method for precisely controlling termination impedance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1581698A CN1581698A (en) | 2005-02-16 |
| CN1317825C true CN1317825C (en) | 2007-05-23 |
Family
ID=34592503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100747834A Expired - Lifetime CN1317825C (en) | 2003-12-06 | 2004-09-14 | Apparatus and method for precisely controlling termination impedance |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1317825C (en) |
| TW (1) | TWI324853B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100879783B1 (en) * | 2007-06-26 | 2009-01-22 | 주식회사 하이닉스반도체 | On Die Termination Device and Semiconcuctor Memory Device including thereof |
| CN102045054B (en) * | 2009-10-13 | 2013-04-24 | 晨星软件研发(深圳)有限公司 | Method and related device for correcting output/input circuit |
| CN108231123B (en) * | 2018-02-07 | 2019-03-08 | 长鑫存储技术有限公司 | A kind of calibration method of semiconductor storage unit |
| CN112290977B (en) * | 2020-10-22 | 2021-08-31 | 中国大唐集团科学技术研究院有限公司华中电力试验研究院 | Adaptive dynamic adjustment method for communication loop |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384621B1 (en) * | 2001-02-22 | 2002-05-07 | Cypress Semiconductor Corp. | Programmable transmission line impedance matching circuit |
-
2004
- 2004-09-03 TW TW93126621A patent/TWI324853B/en active
- 2004-09-14 CN CNB2004100747834A patent/CN1317825C/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384621B1 (en) * | 2001-02-22 | 2002-05-07 | Cypress Semiconductor Corp. | Programmable transmission line impedance matching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200520383A (en) | 2005-06-16 |
| CN1581698A (en) | 2005-02-16 |
| TWI324853B (en) | 2010-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1194313C (en) | Integrated data transceiver circuit for use with serial bus and interface with the same | |
| CN1130830C (en) | Integrated circuit device | |
| CN100403656C (en) | Combined transmitter | |
| CN1712981A (en) | Interface circuit of a hall ic and system for using them | |
| CN1770323A (en) | Semiconductor memory device with on die termination circuit | |
| CN1631014A (en) | Differential line driver with on-chip termination | |
| CN1710812A (en) | Flip-flop circuit | |
| CN1684196A (en) | Current sense amplifier circuits having a bias voltage node for adjusting input resistance | |
| CN1905065A (en) | Impedance adjusting circuit and method | |
| CN1591683A (en) | Data output driver | |
| CN1525347A (en) | Signal transmitting device suited to fast signal transmission | |
| CN1400609A (en) | Memory module | |
| CN1829091A (en) | Output driver in semiconductor device | |
| CN1713516A (en) | Low voltage differential amplifier circuit for wide voltage operation range and its operation method | |
| CN1317825C (en) | Apparatus and method for precisely controlling termination impedance | |
| CN1130022C (en) | Semiconductor circuit device operating in synchronization with clock signal | |
| CN1855724A (en) | Buffer circuit | |
| US7443203B2 (en) | Impedance adjustment circuit and integrated circuit device | |
| CN1114262C (en) | Emitter follower circuit having no temperature dependency | |
| CN1417969A (en) | Semicoductor device | |
| CN1992072A (en) | On-die termination circuit and method for semiconductor memory apparatus | |
| CN1204893A (en) | Interface circuit and method of setting determination level therefor | |
| CN1553569A (en) | Apparatus and method for adjusting the impedance of an output driver | |
| CN105846809B (en) | A kind of buffer circuit and buffer chip | |
| CN104935326B (en) | Output circuit in interface circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |