CN1310130C - Reconfigurating operational method of multiplier and reconfigurating multiplier - Google Patents
Reconfigurating operational method of multiplier and reconfigurating multiplier Download PDFInfo
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- CN1310130C CN1310130C CNB031195911A CN03119591A CN1310130C CN 1310130 C CN1310130 C CN 1310130C CN B031195911 A CNB031195911 A CN B031195911A CN 03119591 A CN03119591 A CN 03119591A CN 1310130 C CN1310130 C CN 1310130C
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Abstract
The present invention discloses a reconfiguration operation method of a multiplier and a reconfiguration multiplier. The multiplier reads multiplication instruction through an instruction register, and the multiplication instruction comprises a reconfiguration code for indicating the number of the multiplication operation. A partial product temporary memory respectively and logically operates a plurality of kinds of multiplication of the identification of the reconfiguration code according to a booth algorithm to obtain partial product of a plurality of kinds of multiplication operation, and the partial product of the multiplication operation is stored in the partial product temporary memory. The partial product temporary memory is divided into a plurality of block arrays according to the reconfiguration code, and the partial product of the multiplication operation is stored in the corresponding block array. A part accumulation device carries out accumulation operation to the result in the part accumulation device, and then the accumulated result is sent to a corrector to be corrected. The multiplier designed according to the technical scheme of the present invention not only provides functions of a normal multiplier, but also provides concurrency support for multiple multiplication. The multiplier can be used in the multiplier or a multiplying and accumulating device in a general-purpose microprocessor or a digital signal processor.
Description
Technical field
The present invention relates to the multiplier in the digital circuit, more particularly, the present invention relates to a kind of restructing operation method and restructural multiplier of multiplier.
Background technology
Multiplier is the general utility functions parts of modern high performance microprocessor and digital signal processor DSP.But general multiplier component can only be finished a kind of multiplication function, can only finish the multiplying of two 32 positional operands as 32 multipliers, 16 multipliers then can only be finished the multiplying of two 16 positional operands, and 8 multipliers then can only be finished the multiplying of two 8 positional operands.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, make a multiplier can carry out the not multiplication of isotopic number, and can carry out a plurality of multiplyings simultaneously, thereby propose a kind of restructing operation method and restructural multiplier of multiplier.
Technical scheme of the present invention is:
A kind of restructing operation method of multiplier may further comprise the steps:
(1) order register reads multiplying order; Described multiplying order comprises operand, and described operand comprises 2
NThe multiplicand part and 2 of position
NThe multiplier part of position; Described multiplying order comprises that also shows a multiplying number 2
MThe reconstruct sign indicating number, 0≤M≤N wherein; Correspondingly, multiplicand partly is divided into 2
MIndividual 2
N-MThe multiplicand of position, multiplier partly is divided into 2
MIndividual 2
N-MThe multiplier of position;
(2) multiplicand part and the multiplier in the order register difference transmit operation number partly arrives multiplicand register and multiplier register;
(3) by the partial product working storage respectively to 2
MIndividual multiplication carries out logical operation according to the booth algorithm and obtains 2
MThe partial product of individual multiplying, and be stored in the partial product working storage; Wherein, described partial product working storage is 2
N Row 2
N+1The bit array of row, the partial product working storage is divided into 2 according to the reconstruct sign indicating number
MRow 2
MThe block array of row, each block array all is 2
N-M Row 2
N-M+1The bit array of row; The partial product of i multiplying is stored in the capable i row of the i block array of partial product working storage, wherein, and 1≤i≤2
M
(4) the partial product totalizer carries out accumulating operation with the result in the described partial product totalizer, and it is long-pending not distinguish this several sections when carrying out accumulating operation, but is considered as the one computing, afterwards accumulation result is sent to as a result in the corrector;
(5) corrector is revised accumulation result according to the reconstruct sign indicating number as a result, and modification method is: to the 2nd of accumulation result
N-M+1XOR is made with 1 respectively in * j position, revises the [2 among the result of back
N-M+1* (j-1)+1]～(2
N-M+1* j) position is the result of j multiplying, 1≤j≤2 wherein
M
A kind of restructural multiplier, this multiplier comprises:
Order register is used to read and store multiplying order, and described multiplying order comprises operand and a reconstruct sign indicating number that shows the multiplying number;
Multiplicand register and multiplier register, the data output end of its input end and instruction register connects, and is used for receiving and accumulating operand;
The partial product working storage, its data input pin is connected with the output terminal of multiplicand register and multiplier register, is used for storing the partial product of multiplication procedure;
The partial product integrating instrument, its data input pin is connected with the data output end of partial product working storage, the partial product that the partial product working storage that is used for adding up is stored;
It is characterized in that:
Described partial product working storage also comprises first control end 1 that the and instruction register connects, be used for receiving the reconstruct sign indicating number of instruction, and control the deposit position of partial product in the partial product working storage of one or more multiplyings according to the reconstruct sign indicating number, it is long-pending not distinguish this several sections when carrying out accumulating operation, but is considered as the one computing;
Also comprise a corrector as a result, be used to revise accumulation result; The data input pin of described corrector as a result is connected with the data output end of partial product totalizer, is used to receive accumulation result;
Described corrector as a result also comprises second control end 2 that the and instruction register connects, and is used to receive the reconstruct sign indicating number, and according to the need correction position in the reconstruct sign indicating number control accumulation result.
According to the multiplier of technical scheme design of the present invention, the function of general multiplier not only can be provided, the concurrency support of multiple multiplication can also be provided.For example, in microprocessor based on single instruction stream multiple data stream SIMD, event data stream short vector length is 128, can utilize restructural multiplier of the present invention to carry out the multiply accumulating computing of two 128 bit vectors so, can also vector multiplier be reconstituted 4 32 multipliers or 8 16 multipliers or 32 8 multipliers according to functional requirement.This multiplier can be used for the multiplier or the multiply accumulating device of general purpose microprocessor or digital signal processor.
Description of drawings
Fig. 1 is the structural representation of restructural multiplier of the present invention;
The drawing explanation
First control end, 1 second control end 2
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
With 32 * 32 restructural multipliers is that example is set forth the present invention, and Fig. 1 shows the structural representation of this multiplier.This multiplier comprises order register, multiplicand register, multiplier register, partial product working storage, partial product totalizer and corrector as a result.The data output end of the input end and instruction register of multiplicand register and multiplier register is connected; The data input pin of partial product working storage is connected with the output terminal of multiplicand register and multiplier register; The data input pin of partial product integrating instrument is connected with the data output end of partial product working storage; First control end, the 1 and instruction register of partial product working storage connects; The data input pin of corrector is connected with the data output end of partial product totalizer as a result, and its second control end, 2 and instruction registers connect.
Order register is used to store the order register of multiplying order, and is as shown in table 1.Comprise 32 multiplicand part and multiplier part and reconstruct sign indicating number in this order register, the reconstruct sign indicating number comprises the reconfiguration information of multiplying.
Table 1
| ... | The reconstruct sign indicating number | 32 multiplicand parts | 32 multiplier parts |
32 multiplicand register and multiplier register are used for receiving the operand of order register.The partial product working storage is 32 * 64 bit array, is used to store the partial product of multiplying, and the location mode of partial product is determined by the reconstruct sign indicating number that first control end 1 of partial product working storage receives.When this multiplier will be reconstructed into 2 16 * 16 multiplier, multiplicand partly was regarded as two 16 multiplicand, and multiplier partly is regarded as two 16 multiplier, then identifies this reconfiguration information by the reconstruct sign indicating number.The partial product working storage carries out logical operation to two multiplication according to the booth algorithm respectively according to the reconstruct sign indicating number, and the location mode of the partial product of these two multiplication in the partial product working storage is as shown in table 2.
Table 2
| 63 | ... | 32 | 31 | ... | 1 | 0 | |
| The partial product of (16 * 32 array) low 16 multiplication | 0 | ||||||
| 1 | |||||||
| ... | |||||||
| 15 | |||||||
| The partial product of (16 * 32 array) high 16 multiplication | 16 | ||||||
| ... | |||||||
| 31 | |||||||
By the partial product totalizer partial product is added up then, do not distinguish this two partial products when carrying out accumulating operation, but be considered as the one computing.Accumulation result is one 64 capable arrays, and is as shown in table 3.Accumulation result is proofreaied and correct the reconstruct sign indicating number control that the need correction position in the accumulation result is received by second control end 2 of corrector as a result by corrector as a result.In the present embodiment, bearing calibration for to 31 of accumulation result and 63 (in the table 3 add *) make XOR with modifying factor 1 respectively.Among the result after the correction, 0～31 and 32～63 net results that are respectively two multiplication.
Table 3
| 63 * | ... | 32 | 31 * | ... | 1 | 0 |
When this 32 * 32 restructural multiplier was reconstructed into 48 * 8 multiplier, multiplicand partly was regarded as 48 multiplicand, and multiplier partly is regarded as 48 multiplier, then identifies this reconfiguration information by the reconstruct sign indicating number.The partial product working storage carries out logical operation to two multiplication according to the booth algorithm respectively according to the reconstruct sign indicating number, and the location mode of the partial product of these 4 multiplication in the partial product working storage is as shown in table 4.
Table 4
| 63 | ... | 48 | 47 | ... | 32 | 31 | ... | 16 | 15 | ... | 0 | |
| Partial product 1 (8 * 16 bit array) | 0 | |||||||||||
| ... | ||||||||||||
| 7 | ||||||||||||
| Partial product 2 (8 * 16 bit array) | 8 | |||||||||||
| ... | ||||||||||||
| 15 | ||||||||||||
| Partial product 3 (8 * 16 bit array) | 16 | |||||||||||
| ... | ||||||||||||
| 23 | ||||||||||||
| Partial product 4 (8 * 16 bit array) | 24 | |||||||||||
| ... | ||||||||||||
| 31 | ||||||||||||
By the partial product totalizer partial product is added up then, do not distinguish this 4 partial products when carrying out accumulating operation, but be considered as the one computing.Accumulation result is one 64 capable arrays, and is as shown in table 5.By corrector as a result accumulation result is proofreaied and correct, bearing calibration is for making XOR with modifying factor 1 respectively to 15,31,47 of accumulation result and 63 (positions that add * in the table 5).Among the result after the correction, 0～15,16～31,32～47 and 48～63 net result that is respectively 4 multiplication.
Table 5
| 63 * | ... | 48 | 47 * | ... | 32 | 31 * | ... | 16 | 15 * | ... | 0 |
Obviously, this 32 * 32 restructural multiplier still can be as one 32 * 32 multiplier.Can constitute any 2 according to principle of the present invention
N* 2
NThe restructural multiplier, can carry out 2 simultaneously
MIndividual 2
N-M* 2
N-MMultiplying, 1≤M≤N wherein.
Claims (2)
1, a kind of restructing operation method of multiplier may further comprise the steps:
(1) order register reads multiplying order; Described multiplying order comprises operand, and described operand comprises 2
NThe multiplicand part and 2 of position
NThe multiplier part of position; Described multiplying order comprises that also shows a multiplying number 2
MThe reconstruct sign indicating number, 0≤M≤N wherein; Correspondingly, multiplicand partly is divided into 2
MIndividual 2
N-MThe multiplicand of position, multiplier partly is divided into 2
MIndividual 2
N-MThe multiplier of position;
(2) multiplicand part and the multiplier in the order register difference transmit operation number partly arrives multiplicand register and multiplier register;
(3) by the partial product working storage respectively to 2
MIndividual multiplication carries out logical operation according to the booth algorithm and obtains 2
MThe partial product of individual multiplying, and be stored in the partial product working storage; Wherein, described partial product working storage is 2
NRow 2
N+1The bit array of row, the partial product working storage is divided into 2 according to the reconstruct sign indicating number
MRow 2
MThe block array of row, each block array all is 2
N-MRow 2
N-M+1The bit array of row; The partial product of i multiplying is stored in the capable i row of the i block array of partial product working storage, wherein, and 1≤i≤2
M
(4) the partial product totalizer carries out accumulating operation with the result in the described partial product totalizer, and it is long-pending not distinguish this several sections when carrying out accumulating operation, but is considered as the one computing, afterwards accumulation result is sent to as a result in the corrector;
(5) corrector is revised accumulation result according to the reconstruct sign indicating number as a result, and modification method is: to the 2nd of accumulation result
N-M+1XOR is made with 1 respectively in * j position, revises the [2 among the result of back
N-M+1* (j-1)+1]～(2
N-M+1* j) position is the result of j multiplying, 1≤j≤2 wherein
M
2, a kind of restructural multiplier of implementing the described method of claim 1 comprises:
Order register is used to read and store multiplying order, and described multiplying order comprises operand and a reconstruct sign indicating number that shows the multiplying number;
Multiplicand register and multiplier register, the data output end of its input end and instruction register connects, and is used for receiving and accumulating operand;
The partial product working storage, its data input pin is connected with the output terminal of multiplicand register and multiplier register, is used for storing the partial product of multiplication procedure;
The partial product integrating instrument, its data input pin is connected with the data output end of partial product working storage, the partial product that the partial product working storage that is used for adding up is stored;
It is characterized in that:
Described partial product working storage also comprises first control end (1) that the and instruction register connects, be used for receiving the reconstruct sign indicating number of instruction, and control the deposit position of partial product in the partial product working storage of one or more multiplyings according to the reconstruct sign indicating number, it is long-pending not distinguish this several sections when carrying out accumulating operation, but is considered as the one computing;
Also comprise a corrector as a result, be used to revise accumulation result; The data input pin of described corrector as a result is connected with the data output end of partial product totalizer, is used to receive accumulation result;
Described corrector as a result also comprises second control end (2) that the and instruction register connects, and is used to receive the reconstruct sign indicating number, and according to the need correction position in the reconstruct sign indicating number control accumulation result.
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| CNB031195911A CN1310130C (en) | 2003-03-12 | 2003-03-12 | Reconfigurating operational method of multiplier and reconfigurating multiplier |
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| CNB031195911A CN1310130C (en) | 2003-03-12 | 2003-03-12 | Reconfigurating operational method of multiplier and reconfigurating multiplier |
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| CN1310130C true CN1310130C (en) | 2007-04-11 |
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| CN105824601A (en) * | 2016-03-31 | 2016-08-03 | 同济大学 | Partial product multiplexing method supporting multi-mode multiplier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85107063A (en) * | 1985-09-27 | 1987-01-31 | 耿树贵 | The array multiplier of multifunctional integer superposition element |
| CN1155117A (en) * | 1996-01-19 | 1997-07-23 | 张胤微 | High-speed multiplication device |
| CN1200821A (en) * | 1995-08-31 | 1998-12-02 | 英特尔公司 | Apparatus for performing multiply-add operations on packed data |
| US6434586B1 (en) * | 1999-01-29 | 2002-08-13 | Compaq Computer Corporation | Narrow Wallace multiplier |
-
2003
- 2003-03-12 CN CNB031195911A patent/CN1310130C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85107063A (en) * | 1985-09-27 | 1987-01-31 | 耿树贵 | The array multiplier of multifunctional integer superposition element |
| CN1200821A (en) * | 1995-08-31 | 1998-12-02 | 英特尔公司 | Apparatus for performing multiply-add operations on packed data |
| CN1155117A (en) * | 1996-01-19 | 1997-07-23 | 张胤微 | High-speed multiplication device |
| US6434586B1 (en) * | 1999-01-29 | 2002-08-13 | Compaq Computer Corporation | Narrow Wallace multiplier |
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| CN1530822A (en) | 2004-09-22 |
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