CN1303645C - Multi-area vertical allocated thin film transistor array base board mnaufacturing method - Google Patents
Multi-area vertical allocated thin film transistor array base board mnaufacturing method Download PDFInfo
- Publication number
- CN1303645C CN1303645C CNB031278655A CN03127865A CN1303645C CN 1303645 C CN1303645 C CN 1303645C CN B031278655 A CNB031278655 A CN B031278655A CN 03127865 A CN03127865 A CN 03127865A CN 1303645 C CN1303645 C CN 1303645C
- Authority
- CN
- China
- Prior art keywords
- substrate
- dielectric layer
- film transistor
- pixel electrode
- transistor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention relates to a thin film transistor array base board of multi domain vertical alignment and a manufacturing method thereof, which comprises the following steps: firstly, a base board is provided; secondly, a plurality of switch elements are arranged on the base board; thirdly, a dielectric layer for covering the switch elements is formed on the base board; fourthly, a plurality of furrows are formed on the dielectric layer; finally, a plurality of picture element electrodes are formed on the dielectric layer.
Description
Technical field
The invention relates to a kind of manufacture method of thin-film transistor array base-plate, refer to a kind of manufacture method that is applicable to the thin-film transistor array base-plate of multiregional vertical align liquid crystal indicator especially.
Background technology
The developing goal of LCD all develops towards large scale, high briliancy, high contrast, wide viewing angle and high color saturation at present, and multiregional vertical align (Multi-Domain VerticalAlignment is called for short MVA) promptly is a big countermeasure that solves liquid crystal indicator visual angle problem now.In the liquid crystal indicator of MVA type, because the viewing area is divided into a plurality of zones, makes liquid crystal arrange in the mode of mutual compensation, therefore can see identical phase difference value in different visual angles, and the phenomenon that does not have gray-scale inversion produces, and also can improve when shortening the response time simultaneously.
In addition, for improving the optics penetrance and the resolution of MVA type liquid crystal indicator, the present practice is to increase by a dielectric layer on thin-film transistor (TFT) substrate, and then increases its aperture opening ratio and reach.Because this dielectric layer is generally photosensitive dielectric materials, it is in the process of follow-up sclerosis (Curing) processing procedure, be easy to take place crosslinked (Cross-linking) reaction and produce thermal expansion (Thermoexpansion), cause dielectric layer be full of cracks (Crack), yield for MVA type liquid crystal indicator has very large negative effect, so the inventor urgently thinks a kind of method that can solve the dielectric layer be full of cracks.
Summary of the invention
Main purpose of the present invention is in the manufacture method that a kind of multiregional vertical align thin-film transistor array base-plate is provided, and can prevent its dielectric layer be full of cracks, improves the yield and the reliability of the MVA type liquid crystal indicator of high aperture design.
Another object of the present invention is that a kind of multiregional vertical align liquid crystal indicator is being provided, and can prevent its dielectric layer be full of cracks, improves the yield and the reliability of the MVA type liquid crystal indicator of high aperture design.
For reaching above-mentioned purpose, the manufacture method of a kind of multiregional vertical align thin-film transistor array base-plate of the present invention is characterized in that, may further comprise the steps:
(A) provide a substrate;
(B) on this substrate, form most switch elements;
(C) dielectric layer of formation one this switch element of covering on this substrate;
(D) form most grooves in this dielectric layer; And
(E) on this dielectric layer, form most pixel electrodes; And
Wherein, this majority pixel electrode forms most cracks, and should the majority crack be corresponding to this majority groove.
It also comprises a step (E) and removes this interior pixel electrode of this groove.
Wherein step (B) also comprises most protrusions of formation in this substrate.
Wherein step (B) also comprises formation one conductor layer.
Wherein this substrate is a glass substrate.
Wherein the material of this dielectric layer is a dielectric constant between the material of 1.0 and 4.0 organic or inorganic.
Wherein the material of this pixel electrode is indium tin oxide or indium-zinc oxide.
A kind of multiregional vertical align liquid crystal indicator of the present invention is characterized in that, comprising:
One has most switch elements, pixel electrode, crack, groove, and first substrate of dielectric layer, wherein this switch element is positioned on this substrate, this pixel electrode is positioned at a side of this switch element, this dielectric layer is between this switch element and this pixel electrode, this crack is positioned at this pixel electrode, this groove is positioned at dielectric layer, and is positioned at a side in this crack;
One second substrate; And
One is positioned at the liquid crystal layer between this first substrate and this second substrate.
Wherein this first substrate also comprises most protrusions, wherein should be formed at this first substrate by a majority protrusion.
Wherein this second substrate also comprises most protrusions, wherein should be formed at this second substrate by a majority protrusion.
Wherein this crack and this groove are overlapping.
Wherein the material of this pixel electrode is indium tin oxide or plugs with molten metal zinc oxide.
Wherein the material of this dielectric layer is a dielectric constant between 1.0 and 4.0 organic material.
Description of drawings
Lift following preferred embodiment and be described as follows for allowing the auditor can more understand technology contents of the present invention, wherein:
Fig. 1 a-Fig. 1 e is the flow chart of the method for manufacturing thin film transistor array substrate of a preferred embodiment of the present invention.
Fig. 2 is the vertical view of the multiregional vertical align liquid crystal indicator of a preferred embodiment of the present invention.
Fig. 3 is the cutaway view of the multiregional vertical align liquid crystal indicator of a preferred embodiment of the present invention.
Fig. 4 is the analog result that the liquid crystal molecule of the embodiment of the invention 2 distributes.
Fig. 5 is the cutaway view of the multiregional vertical align liquid crystal indicator of another preferred embodiment of the present invention.
Fig. 6 is the analog result that the liquid crystal molecule of the embodiment of the invention 3 distributes.
Embodiment
Embodiment 1
The manufacture method of multiregional vertical align thin-film transistor array base-plate of the present invention, its fabrication steps is shown in Fig. 1 a-Fig. 1 e.At first on substrate 100, form most switch elements 200 as shown in Figure 1a.Then on substrate 100, form the dielectric layer 300 that covers switch element 200, and be that photoresist carries out micro-photographing process with dielectric layer 300, except need form originally for pixel electrode and the contact hole 310 that drain electrode, grid lead etc. is connected, form pixel electrode crack part in follow-up desire simultaneously and also be pre-formed most grooves 320, shown in Fig. 1 b, providing dielectric layer 300 in follow-up hardening process, to produce the thermal expansion requisite space, thereby avoid dielectric layer 300 to produce be full of cracks.Be the protective layer 210 and the gate insulator 220 of mask etch thin film transistor 200 with dielectric layer 300 afterwards, shown in Fig. 1 c with pattern.Shown in Fig. 1 d, form pixel electrode 400 more at last.In addition, can be further the pixel electrode on groove 320 surfaces be removed, to form and the identical pattern in script pixel electrode crack, shown in Fig. 1 e.
Embodiment 2
Multiregional vertical align liquid crystal indicator of the present invention, its pixel arrangement mode please refer to Fig. 2, Figure 3 shows that among Fig. 2 cross-section structure simultaneously along the crosscut of A-A line, wherein infrabasal plate 10 is the thin-film transistor array base-plate of structure shown in Fig. 1 e among the embodiment 1, its dielectric layer 11 has at least one groove 12, and groove 12 tops are the crack 13 of pixel electrode.Upper substrate 20 inboards are formed with most protrusions 21, and 20 of infrabasal plate 10 and upper substrates are gripped with a liquid crystal layer 30.The fissured structure of its pixel electrode is same as the prior art, so can get analog result as shown in Figure 4, groove 12 then provides dielectric layer 11 expanded by heating requisite spaces, avoids dielectric layer 11 be full of cracks.
Embodiment 3
The liquid crystal indicator structure of present embodiment is with embodiment 2, and only its infrabasal plate 40 is the thin-film transistor array base-plate of structure shown in Fig. 1 d among the embodiment 1, as shown in Figure 5, promptly the pixel electrode on covering groove 12 surfaces is not removed.Though this pixel electrode structure is different with existing pixel electrode fissured structure, but because of the groove 42 of dielectric layer 41 has replaced the pattern in pixel electrode crack originally, so its effect that changes the liquid crystal molecule direction is consistent with the pixel electrode crack, its analog result as shown in Figure 6.
The present invention additionally forms most grooves in dielectric layer, and the distribution area of dielectric layer is reduced, and to solve dielectric layer in the subsequent thermal processing procedure, in the processing procedure that for example hardens, causes volumetric expansion because of producing cross-linking reaction, thereby the problem of be full of cracks takes place.Groove is except that can significantly lowering the distribution area of dielectric layer, simultaneously can provide dielectric layer thermal expansion requisite space, so phenomenon that dielectric layer can not chap, can improve the yield and the reliability of high aperture design MVA liquid crystal indicator widely, the position of dielectric layer groove groove formation simultaneously is identical with the pixel electrode crack, so need not use extra photo etched mask, also can not improve manufacturing cost, but can solve the problem of dielectric layer be full of cracks easily.
The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (13)
1. the manufacture method of a multiregional vertical align thin-film transistor array base-plate is characterized in that, may further comprise the steps:
(A) provide a substrate;
(B) on this substrate, form most switch elements;
(C) dielectric layer of formation one this switch element of covering on this substrate;
(D) form most grooves in this dielectric layer; And
(E) on this dielectric layer, form most pixel electrodes; And
Wherein, this majority pixel electrode forms most cracks, and should the majority crack be corresponding to this majority groove.
2. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, it also comprises a step (E ') and removes this pixel electrode in this groove.
3. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, wherein step (B) also comprises most protrusions of formation in this substrate.
4. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, wherein step (B) also comprises formation one conductor layer.
5. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, wherein this substrate is a glass substrate.
6. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, wherein the material of this dielectric layer is a dielectric constant between the material of 1.0 and 4.0 organic or inorganic.
7. the manufacture method of multiregional vertical align thin-film transistor array base-plate as claimed in claim 1 is characterized in that, wherein the material of this pixel electrode is indium tin oxide or indium-zinc oxide.
8. a multiregional vertical align liquid crystal indicator is characterized in that, comprising:
One has most switch elements, pixel electrode, crack, groove, and first substrate of dielectric layer, wherein this switch element is positioned on this substrate, this pixel electrode is positioned at a side of this switch element, this dielectric layer is between this switch element and this pixel electrode, this crack is positioned at this pixel electrode, this groove is positioned at dielectric layer, and is positioned at a side in this crack;
One second substrate; And
One is positioned at the liquid crystal layer between this first substrate and this second substrate.
9. multiregional vertical align liquid crystal indicator as claimed in claim 8 is characterized in that, wherein this first substrate also comprises most protrusions, wherein should be formed at this first substrate by a majority protrusion.
10. multiregional vertical align liquid crystal indicator as claimed in claim 8 is characterized in that, wherein this second substrate also comprises most protrusions, wherein should be formed at this second substrate by a majority protrusion.
11. multiregional vertical align liquid crystal indicator as claimed in claim 8 is characterized in that, wherein this crack and this groove are overlapping.
12. multiregional vertical align liquid crystal indicator as claimed in claim 8 is characterized in that, wherein the material of this pixel electrode is indium tin oxide or plugs with molten metal zinc oxide.
13. multiregional vertical align liquid crystal indicator as claimed in claim 8 is characterized in that, wherein the material of this dielectric layer is a dielectric constant between 1.0 and 4.0 organic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031278655A CN1303645C (en) | 2003-08-13 | 2003-08-13 | Multi-area vertical allocated thin film transistor array base board mnaufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031278655A CN1303645C (en) | 2003-08-13 | 2003-08-13 | Multi-area vertical allocated thin film transistor array base board mnaufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1581423A CN1581423A (en) | 2005-02-16 |
| CN1303645C true CN1303645C (en) | 2007-03-07 |
Family
ID=34578877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031278655A Expired - Fee Related CN1303645C (en) | 2003-08-13 | 2003-08-13 | Multi-area vertical allocated thin film transistor array base board mnaufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1303645C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI629797B (en) | 2017-05-09 | 2018-07-11 | 友達光電股份有限公司 | Thin film transistor and the optoelectronic device |
| CN108459426A (en) * | 2018-03-19 | 2018-08-28 | 武汉华星光电技术有限公司 | LTPS display panels and liquid crystal display |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| US6191442B1 (en) * | 1997-07-22 | 2001-02-20 | Mitsubishi Denki Kabushiki Kaisha | DRAM memory with TFT superposed on a trench capacitor |
| JP2001264808A (en) * | 2000-03-17 | 2001-09-26 | Fujitsu Ltd | Liquid crystal display panel |
-
2003
- 2003-08-13 CN CNB031278655A patent/CN1303645C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| US6191442B1 (en) * | 1997-07-22 | 2001-02-20 | Mitsubishi Denki Kabushiki Kaisha | DRAM memory with TFT superposed on a trench capacitor |
| JP2001264808A (en) * | 2000-03-17 | 2001-09-26 | Fujitsu Ltd | Liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1581423A (en) | 2005-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1790750B (en) | Thin film transistor, method of manufacturing the same, display apparatus having the same and method of manufacturing the display apparatus | |
| CN1153313A (en) | Liquid crystal display device and method of fabricating the same | |
| CN1881015A (en) | Liquid crystal display panel and fabricating method thereof | |
| CN1758119A (en) | Vertical alignment active matrix liquid crystal display device | |
| CN1752825A (en) | Liquid crystal display device using small molecule organic semiconductor material and method of fabricating the same | |
| CN1280308A (en) | Film transistor array and its producing method | |
| CN1713044A (en) | Liquid crystal display device | |
| CN1389756A (en) | Making process of film transistor LCD | |
| CN1303645C (en) | Multi-area vertical allocated thin film transistor array base board mnaufacturing method | |
| CN1928644A (en) | Liquid crystal display panel and array substrate for liquid crystal display | |
| CN1641450A (en) | Liquid crystal display device, and its manufacturing method anbd transistor array substrate and manufacturing method | |
| CN101567391B (en) | Structure of thin film transistor | |
| CN1832149A (en) | Film transistor array substrate and its manufacturing method | |
| CN1632685A (en) | Array substrate of thin film transistor liquid crystal display and manufacturing method thereof | |
| CN1153090C (en) | Active matrix substrate and liquid crystal display comprising the same | |
| CN100335960C (en) | Thin film transistor array substrate and fabricating method thereof | |
| CN1265239C (en) | Wide viewing angle planar LCD | |
| CN101464603A (en) | Liquid crystal display device | |
| CN106918958B (en) | Fringe field switching liquid crystal display | |
| CN101038383A (en) | Liquid crystal display device capable of reducing distribution signal delay and manufacturing method thereof | |
| CN1519618A (en) | Liquid crystal display with reflection being reduced | |
| CN1243276C (en) | LCD device and its manufacturing method | |
| US20240047470A1 (en) | Array substrate and display panel | |
| CN1869781A (en) | Manufacturing method of array substrate of semi-reflection semi-penetration liquid crystal display | |
| CN1862350A (en) | Film transistor array substrate structure and mfg. method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070307 Termination date: 20210813 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |