CN1300733C - Pseudo-clock time sequence modeling approach of non-synchronous hard core - Google Patents
Pseudo-clock time sequence modeling approach of non-synchronous hard core Download PDFInfo
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- CN1300733C CN1300733C CNB2004100450461A CN200410045046A CN1300733C CN 1300733 C CN1300733 C CN 1300733C CN B2004100450461 A CNB2004100450461 A CN B2004100450461A CN 200410045046 A CN200410045046 A CN 200410045046A CN 1300733 C CN1300733 C CN 1300733C
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Abstract
The present invention discloses a pseudo synchronous time sequence modeling method for asynchronous hard cores. The present invention aims at solving the problem of large modeling workload caused by combinatory explosion because of excessive input output ports of hard cores. The present invention has the technical scheme that clock variables are introduced when time sequence view graphs of the asynchronous hard cores are established; a virtual clock is arranged in modeling; input total corresponding delayed information and output total corresponding delayed data are converted to all input signals corresponding to the establishing time of the virtual clock and output signals corresponding to the output time delay of the virtual clock; therefore, m two-dimensional tables of the input signals corresponding to the establishing time of the rising edge of the clock and n two-dimensional tables of the output signals corresponding to the delay time of the rising edge of the clock only need to be established; only m+n two-dimensional tables are needed; compared with workload that the traditional time sequence modeling need to establish 2*m*n tables, the workload of the present invention is greatly reduced.
Description
Technical field: the present invention relates to the time series modeling technique of full customized module in the large scale integrated circuit design, the time series modeling technique of especially asynchronous IP (intellecture property Intellectual Property) stone (Hard Macro).
Background technology: the method for designing that current large scale integrated circuit design usually adopts standard block and full customization to combine.For improving design performance, to carry out full Custom Design to key modules such as register file, the data path etc. that influence sequential usually, form stone, be integrated in the system design again.In order in system design, to use stone, just be necessary for the sequential view that this stone is set up complete and accurate.On the other hand, continuous increase along with design scale, integrated circuit (IC) design has entered SOC (system on a chip) (System-on-a-chip, be called for short SOC) epoch, design depends on ip module (being IP kernel) more and more, and the design of IP kernel will solve the generation problem of sequential view inevitably.
Asynchronous stone is a kind of special stone, does not have clock signal in its input and output signal, and the delay of input and output signal size and driving force and clock signal have nothing to do.The time series modeling of common asynchronous stone is always with each output signal and all input signal total correlation modelings, i.e. the rising of each output signal and fall delay and all input signal all have relation.Suppose that stone has m output, n input, then time series modeling need be set up the two-dimentional form of m * n * 2, and m, n are natural number.When input and output signal seldom the time, this method is also more feasible, and workload is not very big.4 forms of the sequential view of one two Sheffer stroke gate.But, for the full customized module of register file class,, cause shot array easily, thereby the modeling workload is huge because the input/output port amount is too much, the modeling cost height, efficient is low.
Summary of the invention: the technical problem to be solved in the present invention is when setting up asynchronous stone sequential view, when the input/output port of stone too much causes shot array, causes the huge problem of modeling workload.The present invention proposes a kind of modeling method efficiently, reduces the complexity of setting up asynchronous stone view, shortens the design cycle of stone.The present invention can significantly reduce the workload of setting up the sequential view under the situation that precision allows.
The present invention adopts the synchronous time series modeling technique of a kind of puppet to asynchronous stone, introduces the clock variable when setting up the sequential view of asynchronous stone.A dummy clock is set during modeling, need time series modeling traditionally the total correlation deferred message of all input signals and all output signals to be converted into only to need all input signals with respect to Time Created of dummy clock and all output signals output delay information with respect to dummy clock, so only need set up m input signal with respect to Time Created of rising edge clock and n output signal two-dimentional form with respect to the time delay of rising edge clock, only need m+n two-dimentional form, need set up 2 * m * n form with traditional time series modeling and compare, workload significantly reduces.
The specific implementation process that the present invention utilizes dummy clock to set up the pseudo-synchronous sequence view of asynchronous stone is:
The first step, set up the sequential view of input signal, method is: suppose that from the logic circuit delays that outputs between next stack register of asynchronous stone be t1, and the supposition clock period is T, set up the sequential view of an input signal A of stone, find variation to cause the maximum delay time that output signal changes because of input signal A by simulation (adopting simulation softwards such as Spice or Star-Sim).Suppose to find by simulation that to all output signal delay paths, input A is to the delay maximum of output B from input signal A, and value is tAB, input signal A is with respect to being set to Time Created of rising edge clock tAB+t1 when then setting up the sequential view.
Second step, set up the sequential view of output signal, method is: suppose need postpone to be t1 from output signal to the logical circuit next stack register input, when setting up the sequential view of output signal B, only need so B has been arranged to T-t1 just with respect to the output delay of rising edge clock, so just the time of t1 has been left for the logical circuit of back.
The 3rd step, optimize view: in order reasonably to distribute temporal constraint, allow the asynchronous stone of full customization preceding logic circuit delays t0 and the logic circuit delays t1 behind the stone distribute rationally, to suitably revise view according to the situation after the placement-and-routing, if it is littler than normal sequential time delay to be found to be the time t0 that stone front logic reserves after the wiring by analysis, and be that the logic time t1 that reserves in stone back is well-to-do than normal sequential time delay, then suitably reduce the value of t1, promptly be equivalent in time window, will to customize stone entirely and slide backward.In contrast, if find to keep for the time t1 of stone back logic littler than normal sequential time delay, then the value with t1 suitably increases, and is equivalent to will customize stone entirely to front slide in time window.By iterating the sequential of circuit is reasonably distributed, circuit also just can be optimized finely.Equally also can not use t1 for referencial use, and adopt the logic circuit delays t0 between a last stack latch and the stone to utilize this kind method to build pseudo-synchronous sequence view for reference.
Adopt the present invention can obtain following technique effect:
When adopting the present invention to set up asynchronous stone sequential view, reduced the complexity of setting up asynchronous stone view, shortened the design cycle of stone, modeling is quick, can under the situation that precision allows, significantly reduce the workload of setting up the sequential view, thereby shorten the construction cycle of chip, the input/output port that efficiently solves when stone too much causes that shot array causes the huge problem of modeling workload.
Description of drawings:
Fig. 1 is traditional sequential view of two Sheffer stroke gates.
Fig. 2 adopts the example of asynchronous stone of the present invention in circuit.
Fig. 3 is the sequential view that adopts the present invention that a register file is set up.
Fig. 4 is classic method and adopts the present invention to carry out the workload comparison diagram of time series modeling.
Embodiment:
Fig. 1 is the sequential view of one two Sheffer stroke gate of classic method foundation, the method of setting up is respectively to build a form by simulating rising, the two kinds of situations that descend that will import X influence output Z, rising, the two kinds of situations that descend of input Y influence output Z are respectively built a form, as shown in Figure 1, build together and found 4 two-dimentional forms, because of the input/output port order fewer, so workload is not very big.
Fig. 2 adopts the example of asynchronous stone of the present invention in circuit, and the key of setting up pseudo-synchronous sequence view is the delay t0 and the t1 of non-sequential stone front and back combinational logic in the same timeticks of reasonable distribution.As shown in the figure, middle square frame is the asynchronous stone of full Custom Design, from the required time of logical circuit that outputs between next stack register of stone be t1, clock period is T, the sequential view approach of setting up an input signal A of stone is to find the variation because of input signal A to cause the maximum delay time that output signal changes by simulation (adopting simulation softwards such as Spice or StarSim).Suppose to find that to all output signal delay paths, A is to the delay maximum of B from input signal A, and value is tAB by simulation, only need input signal A when then setting up the sequential view with respect to Time Created of rising edge clock being set to tAB+t1 just.The sequential view approach of setting up output signal is, suppose to postpone to be t1 to the logical circuit next stack register input from output signal B, when setting up the sequential view of output signal B, only need so B has been arranged to T-t1 just with respect to the output delay of rising edge clock, so just the time of t1 has been left for the logical circuit of back.Therefore adjust the size of t1 by the sequential after the analysis wiring, slided in non-sequential stone front and back in time window, thereby obtain the rational distribution that postpones.
Fig. 3 is one the 10 part sequential view of reading the 6 asynchronous register files of writing that utilizes the present invention to set up.Suppose each read port enable regard one group of bus as with address signal, the enabling of each write port, address and data are regarded one group of bus as, one group of signal is regarded in the data output of each read port as, then this asynchronous register stone has 16 inputs and 10 outputs, if the traditional sequential view method for building up that adopts need be built 16 * 10 * 2=320 two-dimentional form, workload is huge, if adopt pseudo-synchronous sequence modeling method, as shown in Figure 3, only need 16+10=26 two-dimentional form.Suppose that the clock period is 6ns, the combinational logic time of leaving register stone back for is 1.59ns, go out in input saltus step (transition) to be 0.07ns through sunykatuib analysis, under the output load 0.07pF situation, changing to the effective maximum-delay of output data from input bus R0_Addr is 0.9812ns, so R0_Addr is 0.9812+1.59=2.5712ns with respect to Time Created of rising edge clock.Therefore, among Fig. 3 in first form upper left corner numerical value be 2.5712.Equally, be 1.59ns because leave the combinational logic time of register stone back for, so the output of the data of register stone postpones to be T-t1=6-1.59=4.4100ns with respect to rising edge clock.Therefore, first delayed data of R0_Data form is 4.4100 among Fig. 3.
Fig. 4 adopts classic method and pseudo-method for synchronous to carry out the workload comparison diagram of time series modeling.Among the figure relatively be that the summation of the input and output signal number of stone is under 10 situations, adopt classic method and the present invention to set up the workload of sequential view.Horizontal ordinate is the number of input signal, and ordinate is to adopt two kinds of methods to set up the number of the two-dimentional form of view needs.Because the present invention to set up the number of two-dimentional form equal the input and output number and, so as shown in the figure, the present invention need build 10 forms, is a horizontal linear.And classic method need to set up the number of two-dimentional form be m * n * 2, the number that need set up two-dimentional form is shown in the curve among the figure.By relatively finding that the workload that adopts the present invention to set up the sequential view obviously reduces.
The present invention has been applied among the YHFT-D3 and YHFT-D4 chip that University of Science and Technology for National Defence develops voluntarily, and the register file of these two chips all adopts the present invention to carry out time series modeling, has shortened the time series modeling cycle greatly.
Claims (2)
1. the pseudo-synchronous sequence modeling method of an asynchronous stone, it is characterized in that when setting up the sequential view of asynchronous stone, introducing the clock variable, a dummy clock is set when being modeling, need time series modeling traditionally the total correlation deferred message of all input signals and all output signals to be converted into only to need all input signals with respect to Time Created of dummy clock and all output signals output delay information, set up m input signal with respect to Time Created of rising edge clock and n output signal two-dimentional form with respect to the time delay of rising edge clock with respect to dummy clock; Wherein m, n are natural number; The specific implementation process of utilizing dummy clock to set up the pseudo-synchronous sequence view of asynchronous stone is:
The first step, set up the sequential view of input signal, method is: suppose that from the logic circuit delays that outputs between next stack register of asynchronous stone be t1, and the supposition clock period is T, set up the sequential view of an input signal (A) of stone, utilize simulation softward to simulate and find variation to cause the maximum delay time that output signal changes because of input signal (A), suppose to find by simulation, from input signal (A) to all output signal delay paths, input (A) is to the delay maximum of output (B), and value is for tAB, and input signal when then setting up the sequential view (A) is with respect to being set to Time Created of rising edge clock tAB+t1;
Second step, set up the sequential view of output signal, method is: suppose need postpone to be t1 from output signal to the logical circuit next stack register input, then when setting up the sequential view of output signal (B), (B) is arranged to T-t1 with respect to the output delay of rising edge clock, so just the time of t1 left for the logical circuit of back;
The 3rd step, optimize view: in order reasonably to distribute temporal constraint, allow the asynchronous stone of full customization preceding logic circuit delays t0 and the logic circuit delays t1 behind the stone distribute rationally, to suitably revise view according to the situation after the placement-and-routing, if it is littler than normal sequential time delay to be found to be the time t0 that stone front logical circuit reserves after the wiring by analysis, and be that the logic time t1 that reserves in stone back is well-to-do than normal sequential time delay, then suitably reduce the value of t1, promptly be equivalent in time window, will to customize stone entirely and slide backward; In contrast, if find to keep for the time t1 of stone back logic littler than normal sequential time delay, then the value with t1 increases, and is equivalent to will customize stone entirely to front slide in time window; By iterating the sequential of circuit is reasonably distributed, circuit also just can be optimized finely.
The pseudo-synchronous sequence modeling method of 2 asynchronous stones as claimed in claim 1 is characterized in that and can not use t1 for referencial use, and adopts the logic circuit delays t0 between a last stack latch and the stone to build pseudo-synchronous sequence view for reference.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001084055A (en) * | 1999-09-16 | 2001-03-30 | Toshiba Corp | Hard macro cell circuit and semiconductor integrated circuit |
| US6216256B1 (en) * | 1997-05-22 | 2001-04-10 | Sony Corporation | Semiconductor integrated circuit and method of designing the same |
| US6434727B1 (en) * | 1998-10-09 | 2002-08-13 | Fujitsu Limited | Methods of making hard macro cell using timing interval |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6216256B1 (en) * | 1997-05-22 | 2001-04-10 | Sony Corporation | Semiconductor integrated circuit and method of designing the same |
| US6434727B1 (en) * | 1998-10-09 | 2002-08-13 | Fujitsu Limited | Methods of making hard macro cell using timing interval |
| JP2001084055A (en) * | 1999-09-16 | 2001-03-30 | Toshiba Corp | Hard macro cell circuit and semiconductor integrated circuit |
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