CN1299198C - Microcontroller structure using variable instruction format to increase density of program codes - Google Patents
Microcontroller structure using variable instruction format to increase density of program codes Download PDFInfo
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- CN1299198C CN1299198C CNB011295694A CN01129569A CN1299198C CN 1299198 C CN1299198 C CN 1299198C CN B011295694 A CNB011295694 A CN B011295694A CN 01129569 A CN01129569 A CN 01129569A CN 1299198 C CN1299198 C CN 1299198C
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Abstract
The present invention relates to a microcontroller structure using a variable instruction format to increase the density of program codes. Compressed instructions are stored in a memory, wherein each compressed instruction is composed of a group beginning code and at least one index and decompress the compressed instructions to be executed to the format of a presumptive instruction by a decompressor; the instruction decompression device is provided with a plurality of instruction group decoding tables; the presumptive instruction of the predetermined type is stored in each instruction group decoding table; the instruction decompressor selects one instruction group decoding table according to the group beginning code of the compressed instruction and takes out the presumptive instruction corresponding to the instruction group decoding table.
Description
Technical field
The present invention especially refers to a kind of microcontroller architecture that is improved the procedure code closeness by changeable order format relevant for the microcontroller architecture of embedded system.
Background technology
High degree of integration is one of very important characteristic in the embedded system (Embedded System), increases day by day and be accompanied by the function that embedded device handles, and the capacity of ROM (read-only memory) (ROM) also increases thereupon.But the ROM (read-only memory) of larger capacity becomes the principal element that influences the total system cost gradually, and may be the bottleneck place that instruction is extracted, thereby further usefulness is carried out in influence.
Solve this problem, the technical challenge that faces promptly is: sacrificial system not functional with the condition of carrying out usefulness under, how to reduce the capacity of ROM (read-only memory)? the solution that has proposed at present can be generalized into two classes,: (1) provides the scaled-down version (Compact Subset of theOriginal ISA) of presumptive instruction structure set, and (2) adopt the compression method (Instruction BlookOriented Compression Scheme) of instruction block guiding.
The typical case of aforementioned first kind of scheme is represented as ARM Thumb and SGI MIPS16, and they are respectively the scaled-down version of ARM and MIPS.These class methods are usually used in the instruction length that the presumptive instruction collection is 32 bits, are reached the instruction length of 16 bits by the bit number that reduces each field, are the scaled-down versions of original instruction set therefore.With MIPS is the example explanation, and the instruction of MIPS is the order format of 32 bit regular lengths, is divided into three classifications: I class (Immediate), J class (Jump) and R class (Register-to-Register).With the I class is example, as shown in Figure 1, it by operation code (Opcode), source working storage (Source Register), target working storage (Target Register), and immediate value (Immediate Value) field constituted.At some in advance under the condition of standard, if the length of dwindling each field can obtain corresponding I class 16 bit scaled-down versions (shown in the MIPS16 of figure).
Similar thus method can define MIPS scaled-down version instruction set MIPS16.Therefore, the procedure code that uses MIPS16 to represent can reduce its length.And at hardware aspect, as shown in Figure 2, need the extra MIPS16 of adding decompression logic 22, be the MIPS instruction with will decompress by the instruction of the MIPS16 that is extracted in the instruction memory cache 21 (reduction), and then carried out in the MIPS pipeline 23 of the original standard of feed-in.
Aforementioned schemes has following shortcoming: (1) usually scaled-down version instruction set can not individualism, and must with original instruction set architecture coexistence, thereby, reduced elasticity.(2),, reduce compression effects so can cause the increase of original program instruction number because be that scaled-down version also is the cause of subclass.(3) hardware is real is to finish in regular turn by the auxiliary of decompression logic as the aspect, causes critical path (Critical Path) so may influence original pipeline design, and then reduces and carry out speed.(4) do not carry out in various degree compression optimization (Optimization), and the benefit of customized (ustomization) is provided at different application programs.
Again, the typical case of the aforementioned second class scheme is represented as IBM CodePack and Wolfe CCRP (Compressed Code RISC Processor).This scheme is usually in order to reach the validity that run time decompresses, great majority are to adopt Huffman (Huffman) coding of revising as the algorithm of compressing, instruction is got row (Instruction Cache Line) soon as the compression unit, program after the compression is stored in the primary memory, and the instruction memory cache is the instruction of depositing after the decompression.
With CCRP is example, and Fig. 3 has shown the institutional framework of accumulator system among the CCRP.As mentioned above, command memory 31 (Instruction Memory) has stored the procedure code after the compression, and instruction memory cache 32 (Instruction Cache) is then deposited unpressed instruction; In addition, memory cache backfill engine 33 (Cache Refill Engine) then is responsible for the action that instruction decompresses.When program is carried out, if when the memory cache access taking place hitting (Cache Hit) then CPU (central processing unit) 34 (CPU) be directly to extract this unpressed instruction column to be carried out.But, when (Cache Miss) do not hit in the access of generation memory cache, memory cache backfill engine 33 can extract the instruction after the compression from command memory 31, carry out and decompress, instruction after will decompressing again deposits in the instruction memory cache 33, and CPU34 extracts the instruction continuation execution that has just deposited in again from instruction memory cache 32 then.
In addition, this accumulator system and adopted capable address table 311 (Line Address Table, LAT) with get soon capable address impact damper 35 (Cache Line Address Lookaside Buffer, CLB).This journey address table 311 is produced by the compressed software instrument when compression stage, in order to the mapping address of instruction block of address to the compression of condensed instruction block, shift the inconsistent problem of (ControlTransfer) instruction institute's difference purpose address that causes (Branch Target Address) so that solve control.Getting soon that capable address paints towards device 35 then is the use of secondary row address table 311, the instruction required time of backfill when reducing the memory cache access and hitting.
Aforementioned schemes then has following shortcoming: when instruction block size was successively decreased, the added burden that LAT stores form will increase progressively (1).(2) in the Embedded Application of microcontroller (Microcontroller) or lower-order, do not instruct the existence of memory cache, so the method is not suitable for these systems.(3) do not carry out in various degree compression optimization, and the benefit of customized (Customization) is provided at different application programs.
By being as can be known, aforementioned known technology in order to the size that reduces procedure code still has many mistakes, and can't satisfy actual needs, thereby still has and give improved necessity.
Summary of the invention
The object of the present invention is to provide a kind of microcontroller architecture that improves the procedure code closeness by changeable order format, in mode by instruction compression, sacrificial system not functional with the condition of carrying out usefulness under, reduce the demand of ROM capacity, and then reduce the cost of total system.
For reaching aforementioned purpose, microcontroller architecture of the present invention comprises:
One storer stores the instruction after the compression, and wherein, the instruction of each compression is made of the additional at least one index of group's prefix;
One condensed instruction impact damper will be in order to being deposited buffering from the instruction that storer extracted;
Whether one next address logic instructs from memory fetch, or directly the next instruction of condensed instruction impact damper is sent with decision according to the current state of microcontroller; And
One instruction decompressor will be in order to being de-compressed into the presumptive instruction form by the present condensed instruction that this condensed instruction impact damper is sent;
Wherein, this instruction decompressor has a plurality of order bloc decoding tables, each order bloc decoding table stores the presumptive instruction of predefined type, this instruction decompressor is selected an order bloc decoding table according to group's prefix of this condensed instruction, and searches the corresponding presumptive instruction of taking out this order bloc decoding table with the index of this condensed instruction.
It comprises a decoding and a performance element, is decoded into the hardware controls signal with the instruction that will decompress, and carries out core execution corresponding action to control.
This instruction decoder comprises an order bloc extractor and a multiplexer, this order bloc extractor is in order to being decomposed by the present condensed instruction that this condensed instruction impact damper is sent, group's prefix with the foundation condensed instruction is controlled this multiplexer, select an order bloc decoding table, and search with the index of condensed instruction and to take out corresponding presumptive instruction in this order bloc decoding table, and export this demoder and performance element to execution by this multiplexer.
This storer is a ROM (read-only memory).
The stored condensed instruction of this storer is made of the additional instruction index of one first group's prefix, and this instruction index value is used to search one first order bloc decoding table, and this first order bloc decoding table is deposited corresponding presumptive instruction.
The stored condensed instruction of this storer is made of the operation code index of the additional expression difference condition code of one second group's prefix and the shift index of an expression difference purpose address, this operation code index and this shift index are respectively in order to search first and second decoding sublist of one second order bloc decoding table, this first decoding sublist is deposited the difference condition code of corresponding presumptive instruction, and this second decoding sublist is deposited the difference purpose address of corresponding presumptive instruction.
The stored condensed instruction of this storer is represented the index immediately of immediate value by the operation code index and of the additional expression operation code of one the 3rd group's prefix, this operation code index and this immediately index respectively in order to search one the 3rd order bloc decoding table the 3rd and the 4th the decoding sublist, the 3rd decoding sublist is deposited the operation code of corresponding presumptive instruction, and the 4th decoding sublist is deposited the immediate value of corresponding presumptive instruction.
Also store the procedure code of the additional presumptive instruction of a four group group prefix in this storer.
This group's prefix is a regular length.
The higher instruction of the frequency of occurrences has short group's prefix in this storer.
Description of drawings
Also in conjunction with the accompanying drawings the present invention is elaborated with preferred embodiment below, wherein:
Fig. 1 shows the mapping relation of known MIPS and MIPS16 instruction;
Fig. 2 summary shows the hardware configuration of known MIPS16 system;
Fig. 3 summary shows the memory system architecture of known CCRP;
Fig. 4 shows to use microcontroller architecture of the present invention that the solution of Embedded System Design is provided;
Fig. 5 shows the relation according to customized instruction of the present invention and decoding table compartment;
Fig. 6 shows the calcspar of microcontroller architecture of the present invention;
Fig. 7 shows the calcspar of the instruction decompressor in the microcontroller architecture of the present invention.
Embodiment
A relevant preferred embodiment that improves the microcontroller architecture of procedure code closeness by changeable order format of the present invention, the structure with use shown in Figure 4 of reference earlier provide the solution of Embedded System Design, and it designs based on following characteristic:
(1) in the embedded system, the specific function of application program and not change at any time, that is in product development stage, the specification of program and characteristic are roughly fixing.
(2) generally speaking, no matter be that the compositional language procedure code or the procedure code of compiler generation all tend to only use a few instructions in all available commands.
Therefore, as shown in Figure 4, at program development stage (Coding Phase), aforesaid scheme is as traditional approach, still available combination language or high level language are (for example: C) write application program, and obtain the execution shelves 43 that presumptive instruction collection (not compression) is constituted.Then, in coding (compression) stage (Encoding Phase), can obtain the execution shelves 44 that customized instruction set 46 (compression) is constituted by assisting of compressed software instrument (for example: Profiler, Translator), and can be for the information 45 of decoding, to be further used for the hardware design of microcontroller architecture 41.
Aforementioned customized instruction set 46 can be according to the characteristic of presumptive instruction (for example: frequency of occurrences and instruction form) be classified into different order bloc (Instruction Group), represent in the mode of more simplifying then, and reach the effect of instruction compression.For example: show the normal instruction that occurs with less bit numerical table, and the index value of a certain form is promptly represented in this new customized instruction; And microcontroller architecture 41 can utilize table lookup (Table Lookup) mode correspondence to go out original instruction or direct decoding goes out controlling signal.
Fig. 5 shown aforementioned customized instruction with can be for the example of relation of the decoding table compartment of the information of decoding.In this example, be that hypothesis will be instructed originally and is classified into four kinds of group of instructions:
G1:R-Group (Instruction without Immediate), this order bloc is generally by the simplest instruction and is constituted, and it is not the instruction that control is shifted, and neither contain the instruction of immediate value.
G2:C-Group (Control Transfer), this type refers to contain the instruction that control is shifted, and it also contains the address field of the purpose of disagreeing usually.
G3:I-Group (Instruction with Immediate), this type is instructed to contain the instruction of immediate value, but is not control transfer instruction.
G4:M-Group (Miscellaneous Instruction), this type is meant unclassified instruction.
Instruction for the G1 type, the customized instruction of its correspondence is made of additional instruction index (Instruction Index) field of group's prefix (Group Prefix) GI, wherein, this instruction index value is used to search corresponding GI order bloc decoding table 51, and this GI order bloc decoding table 51 is promptly deposited corresponding presumptive instruction.
Instruction for the G2 type, the customized instruction of its correspondence is made of the operation code index (Opcode Index) of the additional expression difference condition code of the prefix G2 of group and shift index (Displacement Index) field of an expression difference purpose address, and these two index values are to be respectively applied for two different decoding sublists 521 and 522 of searching G2 order bloc decoding table 52, and this decoding sublist 521 is promptly deposited the difference purpose address of corresponding presumptive instruction.Thus,, mapping constitutes complete instruction decoding but going out different information.
Instruction for the G3 type, the customized instruction of its correspondence is by the operation code index (Opcode Index) of the additional expression operation code of the prefix G3 of group and the index immediately (Immediate Index) of an expression immediate value, and these two index values are to be respectively applied for two different decoding sublists 531 and 532 of searching G3 order bloc decoding table 53, and this decoding sublist 531 is promptly deposited the operation code of corresponding presumptive instruction, and this decoding sublist 532 is deposited the immediate value of corresponding presumptive instruction.Thus,, mapping constitutes complete instruction decoding but going out different information.
And the instruction of G4 type is to belong to the instruction that does not have compression, so this type does not need to de-compress into original order format with decoding table, but is decoded with original mode, therefore, the customized instruction of its correspondence is by the additional original instruction (Original Instruction) of the prefix G4 of group.
The aforementioned prefix G1-G4 of group can be regular length (for example 2 bits), also can be the coding of variable-length, for example according to Huffman (Huffman) coding and will be short yard give group's prefix to the instruction that the higher type of frequency occurs.
The aforementioned G1-G4 order bloc of concluding only is an example, when practical application, can consider in fact according to the characteristic and the hardware of application program, cooperating the Profiling information, clearly define again, form and the length of defined instruction group's mode classification and sum, group's prefix, reach the options such as length of customized instruction, do optimization process, reach the effect of customized (Customization) with the difference of foundation application program.And wherein conspicuous restriction is exactly, and the instruction length of most of customized instruction must so just can reach the effect of instruction compression less than the length of presumptive instruction.
Customized instruction after compression is performed by microcontroller architecture of the present invention 41, Fig. 6 has promptly shown the calcspar of microcontroller architecture 41 of the present invention, it includes a storer 61, a condensed instruction impact damper 62, one next address logic 63, an instruction decompressor 64, reaches a decoding and performance element 65, wherein, this storer 61 is in order to store the procedure code after compressing, because the procedure code of embedded system does not need to revise, so this storer 61 preferably is a ROM (read-only memory) (ROM).
Along when extracting instruction, the content of the block that will be extracted from storer 61 is deposited buffering to this condensed instruction impact damper 62 for microcontroller.And since the instruction length of customized instruction less than the length of presumptive instruction, therefore, this condensed instruction impact damper 62 may include the instruction of several compressions.
Whether the function of this next address logic 63 is to determine will go storer 61 to extract instruction according to the current state of microcontroller, or directly the next instruction of condensed instruction impact damper 62 is sent.
This instruction decompressor 64 in order to the present condensed instruction that this condensed instruction impact damper 62 is sent decompressed (reduction) become the presumptive instruction form, and then further feed-in should be decoded and performance element 65, solve the hardware controls signal by controlling signal demoder 651, carry out core 652 execution corresponding action to control, wherein, this controlling signal demoder 651 is existing by general microcontroller with execution core 652, so be not described in detail in this its structure.
And by the use of aforementioned next address logic 63 and decompressed instruction impact damper 62, microcontroller can correctly extract the instruction that will carry out, and its function mode is by shown in the following steps:
(1) this next address logic 63 is according to the internal state of microcontroller at present, and why learns the next instruction address of wanting access.
(2) this condensed instruction impact damper 62 will include information such as number of instructions and tell next address logic 63, so that whether the instruction that decision promptly will be carried out is present in this condensed instruction impact damper 62.
(3) if be not present in condensed instruction impact damper 62, the instruction address that then next address logic 63 can access is sent, to be carried out the action of next record instruction fetch by this storer 61.Skipping to step (5) then carries out.
(4) if be present in condensed instruction impact damper 62, then this condensed instruction impact damper 62 is by choosing correct instruction in the instruction block of extracting, and the action that decompresses of feed-in instruction compression device 64.Skipping to step (1) then carries out.
(5) will deposit the impact damper of these condensed instruction impact damper 62 inside in by the content that storer 61 extracts block, and alignd (Alignment).
(6) determined the length of condensed instruction according to the group of instructions prefix.
(7) like this, this condensed instruction impact damper 62 knows that promptly this instruction block includes the order of what compressions, and the border of each condensed instruction.With above-mentioned relevant information, inform next address logic 63 by controlling signal.
By this instruction decompressor 64 it is de-compressed into presumptive instruction again through the aforementioned condensed instruction that extracts, Fig. 7 shows the calcspar of this instruction decompressor 64, it comprises an order bloc extractor 641, a plurality of order bloc decoding tables 50, an and multiplexer 643, wherein, this order bloc extractor 641 is in order to being decomposed by the present condensed instruction that this condensed instruction impact damper 62 is sent, content with group's prefix of foundation condensed instruction is controlled this multiplexer 643, select an order bloc decoding table 50, and search with the value of the index field of condensed instruction and to take out corresponding presumptive instruction in this order bloc decoding table 50, and export this decoding and performance element 65 execution to by this multiplexer 643.
The information of aforementioned again order bloc decoding table 50 can be obtained by the auxiliary of the instrument Translator of compressed software, and these forms can utilize that Progranunable Array Logic (PLA) is real to be done, in the in addition sequencing (Programming) again of product volume production stage.In addition, because the present invention is classified according to order property, so for these decoding tables, can't cause single form greatly, but be made of some little forms when customized new instruction.Based on this characteristic, the decompression action of finishing by the table lookup mode can't cause the impact of hardware, also unlikely very long access time of generation.
By above explanation as can be known, the present invention can be by the presumptive instruction sign indicating number characteristic of collecting application program at the product development period analysis, and customized again instruction set architecture, to reduce the size of procedure code, and the index value of a certain form is promptly represented in new instruction, and decoding circuit can utilize table lookup mode correspondence to go out original instruction, therefore, compared to known technology, the present invention really has the following advantages:
(1) uses changeable order format, with man-to-man instruction level compress mode, so (for example: the application of microcontroller) be applicable in the embedded system of lower-order.
(2), optimized and compressed original each preface with customized formula instruction set architecture, and then customized benefit is provided at the demand of different built-in application programs.
(3) result of optimization and compression can obtain higher procedure code closeness (Code Density) and less procedure code, and then reduces the demand of ROM capacity.
(4) because improved the procedure code closeness, increased the instruction fetch utilization factor, thus memory bus flow (Memory Bus Traffic) reduced, and then reduced the power consumption of total system.
(5) adopt software-hardware synergism design (Software/HardwareCodesign) in product development stage, thereby improved cost effectiveness (Cost-Effective).
In sum, the present invention is unhelpful with regard to purpose, means and effect, show that all it is different from known technology, it should be noted that, above-mentioned many embodiment only give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (9)
1, a kind of microcontroller architecture that is improved the procedure code closeness by changeable order format is characterized in that, mainly comprises:
One storer stores the instruction after the compression, and wherein, the instruction of each compression is made of the additional at least one index of group's prefix;
One condensed instruction impact damper will be in order to being deposited buffering from the instruction that storer extracted;
Whether one next address logic instructs from memory fetch, or directly the next instruction of condensed instruction impact damper is sent with decision according to the current state of microcontroller; And
One instruction decompressor will be in order to being de-compressed into the presumptive instruction form by the present condensed instruction that this condensed instruction impact damper is sent;
One decoding and performance element is decoded into the hardware controls signal with the instruction that will decompress, and carries out core execution corresponding action to control;
Wherein, this instruction decompressor has a plurality of order bloc decoding tables, each order bloc decoding table stores the presumptive instruction of predefined type, this instruction decompressor is selected an order bloc decoding table according to group's prefix of this condensed instruction, and searches the corresponding presumptive instruction of taking out this order bloc decoding table with the index of this condensed instruction.
2, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the instruction decompressor comprises an order bloc extractor and a multiplexer, this order bloc extractor is in order to being decomposed by the present condensed instruction that this condensed instruction impact damper is sent, group's prefix with the foundation condensed instruction is controlled this multiplexer, select an order bloc decoding table, and search with the index of condensed instruction and to take out corresponding presumptive instruction in this order bloc decoding table, and export this decoding and performance element to execution by this multiplexer.
3, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, this storer is a ROM (read-only memory).
4, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is made of the additional instruction index of one first group's prefix, this instruction index value is used to search one first order bloc decoding table, and this first order bloc decoding table is deposited corresponding presumptive instruction.
5, microcontroller architecture according to claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is made of the operation code index of the additional expression difference condition code of one second group's prefix and the shift index of an expression difference purpose address, this operation code index and this shift index are respectively in order to search first and second decoding sublist of one second order bloc decoding table, this first decoding sublist is deposited the difference condition code of corresponding presumptive instruction, and this second decoding sublist is deposited the difference purpose address of corresponding presumptive instruction.
6, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is represented the index immediately of immediate value by the operation code index and of the additional expression operation code of one the 3rd group's prefix, this operation code index and this immediately index respectively in order to search one the 3rd order bloc decoding table the 3rd and the 4th the decoding sublist, the 3rd decoding sublist is deposited the operation code of corresponding presumptive instruction, and the 4th decoding sublist is deposited the immediate value of corresponding presumptive instruction.
7, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, also stores the procedure code of the additional presumptive instruction of a four group group prefix in this storer.
8, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, this group's prefix is a regular length.
9, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, the higher instruction of the frequency of occurrences has short group's prefix in this storer.
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| CN1174352A (en) * | 1996-08-19 | 1998-02-25 | 现代电子美国公司 | Non-volatile memory with embedded programmable controller |
| CN1244675A (en) * | 1998-03-31 | 2000-02-16 | 英特尔公司 | Compressed data instruction of executing part width |
| JP2001043082A (en) * | 1999-07-30 | 2001-02-16 | Nec Corp | Information processor and method for coding and decoding instruction |
| US6195743B1 (en) * | 1999-01-29 | 2001-02-27 | International Business Machines Corporation | Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1174352A (en) * | 1996-08-19 | 1998-02-25 | 现代电子美国公司 | Non-volatile memory with embedded programmable controller |
| CN1244675A (en) * | 1998-03-31 | 2000-02-16 | 英特尔公司 | Compressed data instruction of executing part width |
| US6195743B1 (en) * | 1999-01-29 | 2001-02-27 | International Business Machines Corporation | Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion |
| JP2001043082A (en) * | 1999-07-30 | 2001-02-16 | Nec Corp | Information processor and method for coding and decoding instruction |
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