CN1297991C

CN1297991C - Programming method and circuit for semiconductor memory unit and array by using superthin medium breakdown phenominon

Info

Publication number: CN1297991C
Application number: CN 03117372
Authority: CN
Inventors: 彭泽忠
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-02-28
Filing date: 2003-02-28
Publication date: 2007-01-31
Anticipated expiration: 2023-02-28
Also published as: CN1434457A

Abstract

The present invention relates to a method and a circuit for programming semiconductor memory units and memory arrays by using the phenomenon of ultrathin dielectric breakdown. The programming circuit comprises a word line decoder, an adjustable voltage generator and a nematic transistor, and is used for programming a memory unit comprising a selective transistor and a data storage unit, wherein the data storage unit is programmed by programming currents whose quantity can be adjusted by the nematic transistor, the selective transistor or the adjustable voltage generator.

Description

The programmed method of a kind of semiconductor memory cell and memory array and circuit thereof

Technical field

The present invention relates to the programming technique of non-volatile programmable semiconductor memory, more specifically, be to utilize medium [for example MOS (metal-oxide semiconductor (MOS)) gate medium] punch-through to come the programming technique of the non-volatile programmable semiconductor memory unit of storing digital information.

Background technology

Non-volatile memory still can keep the data of storing behind the power supply in cancellation.This is absolutely necessary in many different types of computing machines and other electronic equipment or expects very much at least.Common a kind of non-volatile memory is programmable read only memory (" PROM "), and it utilizes word-line/bit-line point of crossing element and the trapped charge devices such as floating grid avalanche injecting mos (" FAMOS ") transistor such as fuse, anti-fuse to come stored logic information.PROM generally can not programme again.

(U.S. Patent number: 6,215,140) the disclosed a kind of prom cell that utilizes the puncture of silicon dioxide layer in the capacitor to store numerical data is exactly an example to be presented to Lai Xinggeer people's such as (Reinsinger) United States Patent (USP) April 10 calendar year 2001.The Lai Xinggeer disclosed basic PROM of people such as (Reinsinger) utilizes a capacitor oxide and a knot shape diode to form as the point of crossing elements combination exactly.On behalf of 0, one electric breakdown capacitor of logical value, a complete capacitor represent logical one.The thickness adjusted of silicon dioxide layer is to obtaining needed performance specification.

Make various technologies that various non-volatility memorizer adopts generally lag behind widely used technology (as advanced person's CMOS (complementary metal oxide semiconductor (CMOS)) logic process) aspect improvement improvement.For example, if make particular source and the drain junction of seeing usually in the needed various special areas of high-pressure generating circuit and structure, triple-well, floating grid, ONO layer and this device, the needed photoetching number of times of device technology that resembles the quickflashing EEPROM (electricallyerasable ROM (EEROM)) Duos 30% than the advanced CMOS logic process of standard.Correspondingly, the manufacture craft of flash device will lag behind one to two generation of advanced CMOS logic process of standard, and the cost of every big circular slice is than the latter expensive about 30%.As another example, the technology of making anti-fuse must be suitable for making various anti-fuse structures and high-tension circuit, but this technology falls behind an about generation than the advanced CMOS technology of standard equally.

Summary of the invention

The present invention has provided one and cmos compatible single level polysilicon nonvolatile storage location and array, and programmed circuit and method associated therewith.

The related application that relates to: this paper proposed invention is that the part of U.S. Patent application (application number 10/024,327) that proposes Dec 17 calendar year 2001 and the U.S. Patent application (application number 09/955,641) that proposes September 18 calendar year 2001 continues.Be according to 35U.S.C. (United States code) the 120th joint regulation, to the further elaboration of claim in above-mentioned each patented claim and incorporated with it.

Content of the present invention is: a kind of equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, above-mentioned selection transistor has grid to link to each other with selecting word line, the source links to each other with first end points of above-mentioned data storage elements, leakage links to each other with the row bit line, it is characterized in that the said equipment comprises:

The row current control transistor is connected to above-mentioned row bit line;

Wordline decoder is connected to the transistorized grid of above-mentioned selection by above-mentioned selection word line, and above-mentioned wordline decoder provides one to output signal to above-mentioned selection transistor and activate above-mentioned selection transistor;

An adjustable voltage generator provides a variable voltage output, high-voltage level converter is connected to second end points of above-mentioned data storage elements by the row word line, and above-mentioned high-voltage level converter is connected to above-mentioned adjustable voltage generator and implements above-mentioned variation voltage exported and is added to the above line word line;

Described high-voltage level converter is by the above-mentioned output activation signal of above-mentioned wordline decoder;

Described row current control transistor is by fixedly column voltage generator control, so above-mentioned row current control transistor allows electric current to flow on above-mentioned row bit line.

In the content of the present invention: described data storage elements is a MOS (metal-oxide semiconductor (MOS)) capacitor.

In the content of the present invention: described data storage elements comprises a conducting structure that constitutes above-mentioned second end points, one below above-mentioned conducting structure as the ultra-thin medium of the physical store of data, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first end points.

Described data storage elements punctures above-mentioned ultra-thin medium by making alive between above-mentioned first end points and second end and programmes.

Another content of the present invention is: a kind of equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that the said equipment comprises:

The row current control transistor is connected to above-mentioned row bit line,

An adjustable grid voltage generator provides variable voltage output,

The grid level translator is connected to the transistorized grid of above-mentioned selection by above-mentioned selection word line,

Above-mentioned grid level translator is connected to above-mentioned adjustable grid voltage generator, and adds above-mentioned variable voltage and output to above-mentioned selection word line,

Wordline decoder provides an output signal to above-mentioned grid level translator above-mentioned variable output voltage to be added on the above-mentioned selection word line,

High-voltage level shifters is connected to second terminal of above-mentioned data storage elements by a capable word line, and above-mentioned high-voltage level shifters adds a fixing high pressure for the above line word line;

Above-mentioned high-voltage level shifters is by the output activation signal of above-mentioned wordline decoder;

A fixed voltage generator, the fixed voltage generator provides a high fixed voltage by high-voltage level shifters to programming row word line;

Described row current control transistor is by fixedly column voltage generator control, so above-mentioned row current control transistor allows predetermined fixed current to flow on above-mentioned row bit line.

In the described equipment, data storage elements is a MOS (metal-oxide semiconductor (MOS)) capacitor.

In the described equipment, data storage elements comprises: a conducting structure constitutes above-mentioned second terminal, a ultra-thin medium that below above-mentioned conducting structure, is used as the physical store of data, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first terminal.

Described data storage elements punctures above-mentioned ultra-thin medium by making alive between above-mentioned first terminal and second terminal and programmes.

Wordline decoder is connected to the transistorized grid of above-mentioned selection by above-mentioned selection word line, and above-mentioned wordline decoder offers output signal of above-mentioned selection transistor and activates above-mentioned selection transistor,

An adjustable column voltage generator provides a variable voltage output,

High-voltage level shifters is connected to second terminal of above-mentioned data storage elements by the capable word line of programming, above-mentioned high-voltage level shifters add one fixedly high pressure to above-mentioned programmed word line;

The row current control transistor is connected to above-mentioned row bit line, and the grid of above-mentioned row current control transistor are connected to above-mentioned adjustable voltage generator and accept above-mentioned variable voltage output;

Described high-voltage level shifters is by the above-mentioned output activation signal of above-mentioned wordline decoder.

Data storage elements in the described equipment is a MOS (metal-oxide semiconductor (MOS)) capacitor.

Data storage elements in the described equipment, comprise a conducting structure that constitutes above-mentioned second terminal, one below above-mentioned conducting structure as the ultra-thin medium of data physical store, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first terminal.

Another content of the present invention is: a kind of method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that said method comprises:

Allow electric current to flow through above-mentioned row bit line;

Open above-mentioned selection transistor, and a variable voltage is provided for second terminal of above-mentioned data storage elements by the capable word line of programming, above-mentioned variable voltage is commonly used to control the program current of above-mentioned data storage elements;

Above-mentioned selection transistor is to open when above-mentioned variable voltage output offers above-mentioned programming row word line.

Allow electric current to flow through above-mentioned row bit line;

A high pressure is provided for second terminal of above-mentioned data storage elements by the capable word line of programming;

A variable voltage is provided for the transistorized grid of above-mentioned selection by above-mentioned selection word line, above-mentioned variable voltage is commonly used to control the program current of above-mentioned data storage elements;

Above-mentioned variable voltage is that to be applied to above-mentioned selection when above-mentioned high pressure offers above-mentioned second terminal transistorized.

Open above-mentioned selection transistor,

A high pressure is provided for second terminal of above-mentioned data storage elements by the capable word line of programming,

The program current of above-mentioned data storage elements is controlled in adjusting by the electric current of above-mentioned row bit line.

In the described method, regulating current flow is that the row current control transistor is finished.

Above-mentioned row current control transistor is regulated by an adjustable column voltage generator.

Description of drawings

Fig. 1 adopts the partial circuit synoptic diagram of a kind of memory array of the present invention;

The section layout figure of a part of memory array that Fig. 2 is shown in Figure 1;

Fig. 3 is corresponding to the sectional drawing of the integrated circuit structure of the partial memory array of Fig. 2;

The sectional drawing of the mutation structure of integrated circuit among Fig. 4 Fig. 3;

Fig. 5 adopts the partial circuit synoptic diagram of another kind of memory array of the present invention;

The section layout figure of Fig. 6 partial memory array shown in Figure 5;

Fig. 7 is corresponding to the sectional drawing of the integrated circuit structure of the partial memory array of Fig. 6;

Fig. 8 magnitude of voltage table;

Fig. 9 magnitude of voltage table;

Figure 10 magnitude of voltage table;

The concrete schematic diagram of wherein a kind of structure of Figure 11 semicondctor storage array;

Figure 12 is at the section layout figure of the memory array shown in Figure 11;

The block scheme of Figure 13 semiconductor memory;

The electrical schematic diagram of Figure 14 memory array shown in Figure 11 has the programmed circuit that uses variable word line voltage;

The electrical schematic diagram of Figure 15 memory array shown in Figure 11 has the programmed circuit that uses variable selection transistor voltage;

Figure 16 has the schematic diagram of the memory array shown in Figure 11 of the programmed circuit that uses variable current control.

Embodiment

The programmed circuit and the method that have provided programming and read a memory cell.A kind of semiconductor memory cell with the data storage elements that constitutes on every side in ultra-thin medium (as gate oxide) is used to canned data, and its method of operating is to add stress appearance puncture (soft breakdown or hard breakdown) to ultra-thin medium to set up leakage current level of memory unit.Memory cell is read by the electric current that detecting unit absorbs.In current advanced CMOS logic process, can use a kind of suitable ultra-thin medium (such as about 50 dusts are thick or the high-quality gate oxide of 50 dusts below thick) usually.The common formation method of this oxide layer has the oxide growth of deposit, silicon active area or their group technology.Some other suitable medium comprises oxide-nitride-oxide complex media, chemical combination oxide etc.

In describing in detail below, introduced the memory cell of three kinds of concrete devices of difference.Programmed method described here and circuit are applicable to three kinds of all unit.In addition, provided a large amount of details so that concrete device of the present invention is had a thorough understanding.Yet the people who is familiar with related process will recognize that the present invention under the situation of neither one or a plurality of details, and method, element, material that promptly adopts other etc. just can be implemented.In addition, covered, to the just no longer detailed description or the graphic extension of structure, material or principle of operation of some called optical imaging for fear of some aspect of the present invention.

" a concrete device " or " certain specifically installs " expression concrete characteristics, structure or the characteristic related with being somebody's turn to do concrete device mentioned in the whole detailed description are included in the concrete device of the present invention at least.Therefore, " in a concrete device " of each place appearance in whole detailed description or words such as " in certain concrete devices " not necessarily refer to same concrete device entirely.And concrete characteristics, structure or characteristic can combine in a concrete device or a plurality of concrete device in any suitable manner.

At first, provided the detailed description of memory cell and array among Fig. 1-13.Then, Figure 14-16 has provided the detailed description of programmed circuit and method.

Synoptic diagram among Fig. 1 has provided the example of 4 * 4 parts of a memory array 100 that is made of a plurality of such memory cells.Fig. 1 has provided 16 memory cells, and there are MOS (metal-oxide semiconductor (MOS)) transistor and a MOS semitransistor in each unit.For example, at the 1st row R ₁With the 1st row C ₁The memory cell of point of crossing a n ditch MOS transistor 115, its grid and line R are arranged ₁Connect together its source electrode and source line S ₁Connect together, an end of its drain electrode and MOS semitransistor 111 connects together.

The MOS transistor 115 here is also referred to as the selection transistor, be used for " selection " specific memory device unit be used for the programming or read.As described below, in programming step, give and select transistor and MOS semitransistor 111 to add the gate oxide that a voltage punctures MOS semitransistor 111.Yet, puncture and select transistorized gate oxide not expect.Therefore, in concrete device that some substitutes, select transistorized gate oxide thicker than MOS semitransistor 111.In addition or change a kind of method, select transistor to replace with a kind of device of wearing of more resisting.

The grid of MOS semitransistor 111 and alignment C ₁Link together.Other memory cell that provides among Fig. 1 by some following semitransistor-transistors to constituting: 112 and 116,113 and 117,114 and 118,125 and 121,126 and 122,127 and 123,128 and 124,131 and 135,132 and 136,133 and 137,134 and 138,145 and 141,146 and 142,147 and 143, and 148 and 144.

The principle of work of MOS semitransistor is as follows: when programming or reading, add a positive voltage (concerning p-type active area) to grid, grid is an end of electric capacity.Grid plays a plate of electric capacity, also makes a n shape of the following formation inversion layer of grid simultaneously.Inversion layer plays another plate of electric capacity, and constitutes second end of electric capacity with source/drain region.

It is favourable using semi-crystal cast data storage elements in the memory array 100 of Fig. 1, because semitransistor can be made and need not add any mask step with the MOS of many routines and CMOS technology.Yet, if desired, also can use the ultra-thin medium data storage elements of other kind.For example, the benefit of capacitor type data storage elements is to programme in any one direction, and its resistance is smaller when adding stress to ultra-thin medium, but needs to increase mask step in some technology one time.Fig. 3 is the sectional view of semitransistor data storage elements, and Fig. 4 is the sectional view of capacitor type data storage elements.

Though only provided 4 * 4 parts of memory array 100, in fact when with such as 0.13 advanced μ m CMOS logic process when making, such memory array includes the memory cell of about 1000 megabit magnitudes.Along with the further improvement of CMOS logic process also can realize bigger storer.In fact storer 100 is organized into some bytes, the page and redundant row or row (not shown), thisly organizes available your needed any way to carry out.In technology circle many suitable memory organization structures being arranged is called optical imaging.

Shown in Fig. 2 is local layout Figure 200 of memory array 100 parts.Fig. 3 is the sectional drawing of an illustrative MOS integrated circuit 300.The figure shows some main configuration aspects, according to the layout of Fig. 2, these structures are corresponding to right to 115 and 111,121 and 125 memory cells that constitute by transistor-semitransistor.The layout of Fig. 2 is suitable for such as advanced CMOS logic process." MOS " this speech is metal-oxide-silicon in the literal meaning.Though letter ' M ' is represented " metal " grid structure, letter " O " expression oxide, this word of MOS is generally understood as and is applicable to any grid material, comprises doped polycrystalline silicon, other good conductor and silicon dioxide various gate medium in addition.This word usefulness that in this explanation, comes to this.For example, medium can be any medium, and such as oxide or nitride, it when adding the voltage of a period of time hard breakdown or soft breakdown will take place.In a concrete device, used the thick heat growth grid silicon dioxide of about 50 dusts.

Memory array 100 preferably adopts grid mode layout, makes alignment (as C ₁And C ₂) with line (as R ₁, R ₂, R ₃And R ₄) and the diffuse source line vertical.For forming oxide isolation structure, comprise oxide groove 302 and 314 (Fig. 3) and carve active area as 313 (Fig. 3), used active area mask to carry out photoetching with figure 213 (Fig. 2).Active area will comprise the diffuse source line of various transistors, semitransistor and memory array.Be positioned at line R ₁With alignment C ₁The MOS semitransistor 111 of point of crossing and MOS transistor 115 and be positioned at line R ₂With alignment C ₁The MOS semitransistor 125 of point of crossing and MOS transistor 121 form in the following manner at p trap active area 313.

Forming superthin grid oxide layer 312 back deposit and doped polycrystalline silicon.Use grid mask litho pattern then.The figure that the grid mask comprises has: the grid 311 of semitransistor 111,125 and 301 figure 211,214,221 and 224 and the grid of (not providing) semitransistor 112,126 and other semitransistor; With line R ₁And R ₂R ₁And R ₂Figure, these figures also work to select the grid of transistor 115,121,116 and 122 (and other selects transistor).Various source regions and drain region form with n type light dope raceway groove (" NLDD ") processing step (inject, isolate and n+ source/leakage injection), produce n+ district 306,308 and 310.N+ district 308 also is the part of diffuse source line.With the contact through hole that mask forms grid 301 and 311 (Fig. 3) and other grid (not providing) that contacts that comprises figure 210,215,220 and 225 (Fig. 2).The metal mask version comprises and indicates C ₁And C ₂Dashed graph (Fig. 2) is used to form as C ₁And C ₂Such alignment, these alignments and polysilicon line are (as R ₁, R ₂, R ₃And R ₄) and the diffuse source line vertical.Other transistor-semitransistor in the storer 100 forms simultaneously to using the same method.

Shown in Figure 4 is the sectional drawing of the primary structure of an illustrative MOS integrated circuit 400.Sectional drawing 400 is similar with the sectional drawing 300 of Fig. 3, and just the semitransistor 125 and 111 among Fig. 3 is by another kind of ultra-thin medium data storage elements, i.e. capacitor 425 and 411 replacements.Be positioned at line R ₁With alignment C ₁The capacitor 411 of point of crossing forms by polysilicon gate 311.It is to realize contacting by the Metal Contact that carves with figure 210, and covers gate oxide 312 with above the dark diffusion n+ district 410.Equally, be positioned at line R ₂With alignment C ₁The mos capacitance device 425 of point of crossing forms by polysilicon gate 301, and it is to realize contacting by the Metal Contact that carves with figure 215, and covers gate oxide 312 with above the dark diffusion n+ district 406.

N+ district

406 and 410 can allow

capacitor

425 and 411 semitransistors 125 and 111 with respect to Fig. 3 have the low-down conductive state of resistance, but this will depend on the foundation of the inversion layer of conduction current.Capacitor 425 and another advantage of 411 are that they can be programmed by the electric current that any direction flows.Capacitor 406 is exactly generally all to need to come the technology utilized on the market is made amendment by increasing photoetching process and/or injection technology with a shortcoming of 410.For example, the appropriate technology that forms

n+ district

406 and 410 is included in the buried regions n+ that uses before the deposit polysilicon gate and injects, and perhaps carries out the side and inject diffusion after deposit polysilicon and etching.Though

n+ district

406 and 410 seems to spread deeplyer than integrated their doped

region

306 and 310, the degree of depth of diffusion can change on request.

Memory array 500 shown in Figure 5 is exactly a mutation of memory array 100.The figure shows any 4 * 4 parts of a bigger memory array that is made of memory cell, each memory cell has a MOS transistor and a MOS semitransistor.For example, be positioned at the 1st row R ₁With the 1st row C ₁The memory cell of point of crossing comprise that grid are connected to line R ₁, leak and to be connected to the 1st row C ₁, the source is connected to the n ditch MOS transistor 515 of a MOS semitransistor 511.The grid end of MOS semitransistor 511 is connected to source line S ₁To constituting, they are other memory cell shown in Fig. 1: 512 and 516,513 and 517,514 and 518,521 and 525,522 and 526,523 and 527,524 and 528,531 and 535,532 and 536,533 and 537,534 and 538,541 and 545,542 and 546,543 and 547,544 and 548 by similar semitransistor-transistor.

As the situation of the memory array of Fig. 1, in memory array shown in Figure 5, available mos capacitance device replaces the MOS semitransistor.

Figure 6 shows that the local layout 600 of the part of memory array 500.Fig. 7 has provided the sectional drawing of illustrative MOS integrated circuit 700 primary structures, and according to the layout of Fig. 5, these primary structures are corresponding to right to 515 and 511,525 and 521 memory cells that constitute by transistor-semitransistor.The layout of Fig. 6 is suitable for such as advanced CMOS logic process.Memory array 500 is preferably used a kind of grid mode layout, makes alignment (as C ₁And C ₂) with line (as R ₁, R ₂, R ₃And R ₄) and the source line (as S ₁) vertical.Carry out photoetching with n+ diffusion and the active area mask that comprise figure 612,614,622 and 624 (Fig. 6), formation oxygen isolation structure and active area are as 710 (Fig. 7).The oxygen isolation structure comprises oxide groove 704 (Fig. 7); Active area will comprise the various transistors and the semitransistor of memory array.Be positioned at line R ₁With alignment C ₁The MOS semitransistor 511 of point of crossing and MOS transistor 515 and be positioned at line R ₂With alignment C ₁The MOS semitransistor 521 of point of crossing and MOS transistor 525 form in the following manner at p trap active area 710.Carry out polysilicon deposit and doping after forming one deck superthin grid oxide layer 702.Its figure is with having figure R ₁, S ₁And R ₂The grid mask make by lithography, these graphic structures are with transistor 515,525,516 and 526 and the grid of semitransistor 511,521,512 and 522 of electing.Each source region and drain region form by using n type light dope raceway groove (" NLDD ") processing step (injection, isolation and n+ source/leakage is injected), produce n+ district 712,714,716 and 718 (Fig. 7).Use one have figure 610,616,620 and 626 (Fig. 6) contact that mask carries out that 712 and 718 (Fig. 7) form are leaked in photoetching and to the contact through hole of other leakage (not providing).The metal mask version comprises and indicates C ₁And C ₂Dashed graph (Fig. 6) is used for forming alignment (as C ₁And C ₂), alignment and polysilicon line are (as R ₁, R ₂, R ₃And R ₄) and polysilicon source line (as S ₁) vertical.Other transistor-semitransistor in the storer 500 forms simultaneously to using the same method.

The principle of work of memory array 100 is described referring now to illustrative voltages shown in Figure 8.It will be appreciated that these voltages are illustrative, in different application, maybe when using different technologies, will use different voltage probably.When programming, each memory cell in the memory array 100 just is exposed under a kind of situation of four kinds of possible voltage combinations, and these voltage tables are shown on the line 801,802,803 and 804 of Fig. 8; Writing voltage table is shown on line 805,806,807 and 808.

Suppose that selecteed row and column (" SR/SC ") is R ₁And C ₁, come the memory cell of transistor 115 and semitransistor 111 compositions is programmed with it.Shown on line 801, at line R ₁On voltage be 2.5V, at source line S ₁On voltage be 0V, be enough to make transistor 115 conductings, make the drain voltage of transistor 115 become 0V.At alignment C ₁On voltage be 7.0V, it causes the potential difference (PD) of a 7V at the two ends of semitransistor 111.Gate oxide 212 in the semitransistor 111 is to be designed to puncture under this potential difference (PD), thereby memory cell is programmed.When semitransistor 111 was breakdown, the conductive path of acquisition had enough resistivity to stop the gate oxide 212 of transistor 115 to degenerate or puncture.As an example, in some device, the channel resistance of transistor 115 is greatly about about 10k Ω, and the resistance that punctures oxide layer is greater than 100k Ω.

Suppose R ₁And C ₁Be selecteed row and column, consider this and select influence for the memory cell that is constituted by transistor 116 and semitransistor 112 on the point of crossing that is positioned at selected row and not selected row (" SR/UC ").Shown on line 802, at line R ₁On voltage be 2.5V, at source line S ₁On voltage be 0V, be enough to make transistor 116 conductings and make the drain voltage of transistor 115 become 0V.Yet, at alignment C ₂On voltage be 0V, this can make the two ends of semitransistor 112 produce the potential difference (PD) of a 0V.Memory cell can not be programmed.

Suppose R ₁And C ₁Be selecteed row and column, consider this and select for the influence that is positioned at the memory cell that constitutes by transistor 121 and semitransistor 125 on non-selected row and selecteed row (" the UR/SC ") point of crossing.As shown in the line 803, line R ₂On voltage be 0V, source line S ₁On voltage be 0V, so transistor 121 not conductings, and the node between transistor 121 and the semitransistor 125 is floated.At alignment C ₁On voltage be 7.0V, this makes semitransistor 125 two ends produce the potential difference (PD) less than 4V.Memory cell is not programmed, and this without any electric current flow less than the potential difference (PD) deficiency of 4V so that the gate oxide in semitransistor 125 or the transistor 121 damage occurs or decline and fall.

Suppose R ₁And C ₁Be selecteed row and column, consider this and select for the influence that is positioned at the memory cell that is constituted by transistor 122 and semitransistor 126 on non-selected row and non-selected row (" the UR/UC ") point of crossing.Shown on line 804, at line R ₂On voltage be 0V, at source line S ₁On voltage be 0V, so transistor 122 not conductings.At alignment C ₂On voltage also be 0V, so do not have potential difference (PD) at semitransistor 126 two ends.Memory cell is not programmed.

The playback mode of memory array 100 is as follows: what add a 2.5V on selected row (" SR ") reads to select voltage, and what add a 1.5V on selected row (" SC ") reads to select voltage.All other non-selected row (" UR ") and non-selected row (" UC ") are set to 0V.Suppose R ₁And C ₁Be selecteed row and column (" SR/SC "), the memory cell that is formed by transistor 115 and semitransistor 111 is programmed.Shown on line 805, by line R ₁That gives that the grid of transistor 115 add a 2.5V reads to select voltage, by source line S ₁Its source of giving adds a 0V voltage, makes electric current from alignment C ₁Be absorbed.Alignment C ₁On voltage be 1.5V, show that memory cell is programmed.If memory cell is not programmed, just do not have flowing of electric current, the instruction memory unit is not programmed.

If the memory cell in the point of crossing has not selected row or not selected row just can not ABSORPTION CURRENT.The situation of selected alignment is not the same with one as selected line shown in the line 806, the voltage of adding 2.5V for transistorized grid in the memory cell, but because the voltage on alignment is 0V, so there is not electric current to flow.The situation of not selected line of shown on line 807 and a selecteed alignment, be added in that the voltage on the transistor gate is 0V in the memory cell.Though the voltage that exists on the alignment is 1.5V, transistor keeps OFF state, so there is not electric current to flow.The not selected line of shown on line 808 one and one is the situation of selected alignment, is added in that the voltage on the transistorized grid is 0V in the memory cell, and the voltage that exists on alignment is 0V, so there is not electric current to flow.

The principle of work of memory array 500 is described referring now to the voltage shown in Fig. 9 and 10.These voltages are illustrative, maybe when using different technologies, will use different voltage probably in different application.It should be appreciated that, though Fig. 8,9 with 10 table in listed magnitude of voltage be different, the principle of these magnitude of voltage back is the same, this has illustrated the range of useful voltage.

Consider illustrative program voltage listed in Fig. 9 table first.Having one deck ultra-thin gate dielectric at semitransistor, is that gate oxide thickness is suitable for greater than these voltages under the situation of the I/O device of 50 dusts but select transistor.In when programming, each memory cell in the memory array 500 just is exposed under a kind of situation in the voltage combination possible in four, and this illustrates on the line 901,902,903 and 904 of Fig. 9.A common ground of all voltage combinations is exactly source line S ₁Magnitude of voltage be 0V.

Suppose that selecteed row and column (" SR/SC ") is R ₁And C ₁, this selection will be used for the memory cell of transistor 515 and semitransistor 511 formations is programmed.Shown on line 901, at line R ₁On voltage be 7.0V, at alignment C ₁On voltage be 7.0V.This just makes grid and leaks the voltage that 7.0V occurs, is enough to make transistor 515 conductings.The source voltage of transistor 515 is raised to 7.0V, makes transistor 515 two ends that some voltage drops be arranged a little, thereby makes the potential difference (PD) of a 6.6V of two ends appearance of semitransistor 511.Gate oxide 712 in the semitransistor 511 is to be designed to puncture under this potential difference (PD), thereby memory cell is programmed.When semitransistor 511 punctured, the conductive path of acquisition had enough resistivity and adopts the gate oxide 712 that stops transistor 515 and occur declining and fall or puncture.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is for the influence that is positioned at the memory cell that is made of transistor 516 and semitransistor 512 on selecteed row and not selected row (" the SR/UC ") point of crossing.Shown on line 902, at line R ₁On voltage be 7.0V, at alignment C ₁On voltage be 0V.This voltage that makes on the grid is 7.0V, is enough to make transistor 516 conductings, and makes voltage and alignment C on transistor 516 sources ₂On voltage roughly the same, i.e. 0V.Because the potential difference (PD) at semitransistor 512 two ends is about 0V, so memory cell is not programmed.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is for the influence that is positioned at the memory cell that is made of transistor 525 and semitransistor 521 on not selected row and selected row (" the UR/SC ") point of crossing.Shown on line 903, line R ₂On voltage be 0V, alignment C ₁On voltage be 7.0V.This makes that the voltage on the grid is 0V, and the voltage in the leakage is 7.0V.Though current potential and source line S on leaking ₁On current potential between have the voltage difference of 7.0V roughly between transistor 525 and semitransistor 125, to divide equally, and make the oxide layer two ends of semitransistor 521 potential difference (PD) occur, but transistor 525 not conductings less than 4V.Memory cell is not programmed, without any electric current flow less than the potential difference (PD) deficiency of 4V so that the gate oxide of semitransistor 521 or transistor 525 damage occurs or decline and fall.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is to being positioned at the influence of the memory cell that is made of transistor 526 and semitransistor 522 on non-selected row and non-selected row (" the UR/UC ") point of crossing.On line 904 shown, at line R ₂On voltage be 0V, at alignment C ₂On voltage be 0V, so transistor 526 not conductings.At source line S ₁On voltage also be 0V, so do not have potential difference (PD) at the two ends of semitransistor 522.Memory cell is not programmed.

Consider illustrative program voltage listed in the table of Figure 10 then.All have under the situation of superthin grid oxide layer for semitransistor and selection transistor, these magnitudes of voltage are suitable.When programming, each memory cell in the memory array 500 just is exposed under four kinds of a kind of situations in the voltage combination.Expressed this situation on the line 1001,1002,1003 and 1004 in Figure 10.A common ground of all voltage combinations is exactly source line S ₁On magnitude of voltage all be-4.5V.

Suppose R ₁And C ₁Be selecteed row and column (" SR/SC "), this selection will be used for the memory cell that is made of transistor 515 and semitransistor 511 is programmed.Shown on line 1001, at line R ₁On voltage be 2.5V, at alignment C ₁On voltage be 2.5V.This just makes grid and leaks the voltage that 2.5V occurred, is enough to make transistor 515 conductings.The source voltage of transistor 515 is raised to 2.5V, makes transistor 515 two ends slight voltage drop occur, thereby makes the two ends of semitransistor 511 potential difference (PD) of 6.6V occur.Gate oxide 712 in the semitransistor 511 is to be designed to puncture under this potential difference (PD), thereby memory cell is programmed.When semitransistor 511 punctured, the conductive path of acquisition had enough resistivity and stops the gate oxide 712 of transistor 515 to occur puncturing or declining and fall.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is to being positioned at the influence of the memory cell that is made of transistor 516 and semitransistor 512 on selecteed row and non-selected row (" the SR/UC ") point of crossing.Shown on line 1002, at line R ₁On voltage be 2.5V, at alignment C ₁On voltage be 0V, this is 2.5V with regard to making the voltage on the grid, is enough to make transistor 516 conductings, and the source voltage of transistor 516 is raised to be about alignment C ₂On magnitude of voltage, i.e. 0V.Because the potential difference (PD) at semitransistor 512 two ends is approximately 4.0V, so memory cell is not programmed.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is to being positioned at the influence of the memory cell that is made of transistor 525 and semitransistor 521 on non-selected row and selecteed row (" the UR/SC ") point of crossing.Shown on line 1003, at line R ₂On voltage be 0V, at alignment C ₁On voltage be 2.5V.This is 0V with regard to making the voltage on the grid, and the voltage on the source is 2.5V.Although transistor 525 not conductings are current potential and source line S on leaking ₁On the have an appointment potential difference (PD) of 6.5V and roughly dividing equally on transistor 525 and semitransistor 125 of current potential, cause the oxide layer two ends of semitransistor 521 potential difference (PD) to occur less than 4V.Memory cell is not programmed, and this is not enough to the gate oxide in semitransistor 521 or the transistor 525 is caused damage or declines and fall less than the potential difference (PD) of 4V under situation about flowing without any electric current.

Suppose R ₁And C ₁Be selecteed row and column, consider that this selection is to being positioned at the influence of the memory cell that is made of transistor 526 and semitransistor 522 on non-selected row and non-selected row (" the UR/UC ") point of crossing.Shown on line 1004, at line R ₂On voltage be 0V, at alignment C ₂On voltage be 0V, so transistor 526 not conductings.Because at source line S ₁On voltage be-4.5V, so the potential difference (PD) that occurs at semitransistor 522 two ends is less than 4V.Memory cell is not programmed.This under situation about flowing without any electric current less than the potential difference (PD) deficiency of 4V so that the gate oxide in semitransistor 522 or the transistor 526 damage occurs or decline and fall.

No matter use and disuse the program voltage of listing in Fig. 9 or Figure 10 table, memory array 500 is all read in the following manner.Give selecteed row (" SR ") add a 2.5V read select voltage and add that a 1.5V's reads to select voltage for selecteed row (" SC ").All other non-selected row (" UR ") and non-selected row (" UC ") place 0V.Suppose R ₁And C ₁For selecteed row and column (" SR/SC ") and the memory cell that is made of transistor 515 and semitransistor 511 are programmed.Shown on line 905 and 1005, by line R ₁Give the grid of transistor 515 add a 2.5V read select voltage and by alignment C ₁Add to leakage and the voltage of a 1.5V will make electric current from alignment C ₁Be absorbed, show that memory cell is programmed.If memory cell is not programmed, just do not have electric current and flow, show that memory cell is not programmed.

Have in the point of crossing under the situation of a non-selected row or non-selected row, do not have electric current and be stored the absorption of device unit.Not the situation of selected row, transistorized grid have added 2.5V voltage in the memory cell as selected row shown in line 906 and 1006 and one, but the voltage that exists on alignment is 0V, flows so do not have electric current.On line 907 and 1007 the situation of a shown not selected line and a selected alignment, be added in that the voltage on the transistor gate is 0V in the memory cell.Though the voltage that occurs on alignment is 1.5V, there is not electric current to flow, because transistor keeps OFF state.The situation of selected alignment, the voltage that is added on the memory cell transistor grid is not 0V for the not selected line of shown on line 908 and 1008 one and one, and the voltage on the alignment is 0V, so there is not electric current to flow.

Previously described and than the memory cell under the previous technology very big price, performance advantage are arranged to the design of memory cell shown in Figure 10 and array at Fig. 1.Yet as we have seen, relatively large program voltage (representative value is 6 or bigger) is applied to the oxide layer of semitransistor in the programming process.Do not have selected row of programming (as, the selection transistor of non-programming unit) for those, if the programming in advance of this unit, relatively large voltage can be added on the transistorized oxide layer of selection of not programming.This may damage (puncture) selected transistorized oxide layer.In order to address this problem, perhaps select transistor can use the gate oxide on thicker (the 70 Izod right side)., thick gate oxide causes memory cell dimensions to become big.

By revising domain and program voltage, perhaps the problem that proposes previously can be resolved.Particularly, in the concrete device that is described below, select transistorized gate oxide can make the ultra-thin medium the same with the semitransistor memory element.This is because the transistorized gate oxide of selection of not selected memory cell can not stand big voltage.Translate into Figure 11,12, can see wherein a kind of concrete schematic representation of apparatus of the present invention and top layer domain.In this concrete device, select transistor 1701 by a signal V _WR1

(subscript is represented " the 1st sense word line ") control.Other row of memory cell is by signal V _WnTransistor is selected in control, and n is from 1 to N (sum of memory array row) here.Signal V _WRnOn the capable selection wire of mentioning, transmit, in other words on word select line.

Select the leakage of transistor 1701 and voltage V is provided _C1A column selection line 1705 (also claiming the row bit line) link to each other.Memory cell other row with by signal V _CmThe transistorized source of selection of control links to each other, and the m here is from 1 to M (sum that is listed as in the memory array).

Select the source of transistor 1701 to link to each other with an end of capacitor 1703.In a kind of concrete device, capacitor 1703 is mos capacitance devices that formed by ion implanted region, gate oxide and polysilicon layer.In a kind of concrete device, select the source of transistor 1701 to link to each other with the ion implanted region of mos capacitance device 1703.The gate oxide of capacitor is as memory element (in order to programme, gate oxide optionally can be punctured as previously mentioned).(it provides voltage V to the polysilicon layer of mos capacitance device 1703 with programming row 1701 _MPI) link to each other.The row of other the memory cell with mos capacitance device 1703 polysilicon layers is with signal V _WPnBe connected, n is from 1 to N (sum of the row in the memory array) here.Signal V _WRnOn the capable line program of mentioning, transmit, or transmit on the row word line.

Can see the top layer domain of memory array among Figure 12.This top level diagram has shown six memory cells.Figure 11 has identical unit number and same project organization with Figure 12.Thereby the selection transistor 1701 among Figure 12 is shown as the source region and leaks the polysilicon layer (V that forms between the injection region _WRI).Figure 12 also demonstrates handle and selects the contact hole 1801 of the leakage company of transistor 1701 to a row bit line.

As illustration, following table is listed the operation conditions of memory cell under illustrative voltages in Figure 11 and 12.

	V _C	V _WP	V _WR	V _XO	V _GO	Programming
	V _C	V _WP	V _WR	V _XO	V _GO	Programming	Programming	SC/SR	0	5.5	2	5.5	2	Be
SC/UR	0	0	0	0	0	Not	Programming	SC/SR	0	5.5	2	5.5	2	Be

UC/SR	2	5.5	2	3.5	0	Not
UC/SR	2	5.5	2	3.5	0	Not		UC/UR	2	0	0	0	2	Not
						Read current		UC/UR	2	0	0	0	2	Not
						Read current	Read	SC/SR	1.2	0	1.2			Be
SC/UR	1.2	0	0			Not	Read	SC/SR	1.2	0	1.2			Be
SC/UR	1.2	0	0			Not		UC/SR	0	0	0			Not
UC/UR	0	0	0			Not		UC/SR	0	0	0			Not

It is pointed out that above-mentioned voltage value is illustrative, different application modes or different processing technologys, the voltage of application is different probably.In the programming process, numerous memory cells may be exposed in the combination of four kinds of voltages one group in the memory array, corresponds respectively to: the unit on (1) selected row (SC) and selected row (SR) point of crossing; (2) not at selected row (referring to not selected row or " UC "), but in the unit of selected row; (3) not at selected line (referring to non-selected row or " UR "), but in the unit of selected row; (4) neither at selected line again not in the unit of selected row.

For the unit on selected row and the selected row (" SR/SC "), at line V _WROn voltage be 2 volts, at column selection line V _COn voltage be 0 volt, at line program V _WPOn voltage be 5.5 volts.This just causes 5.5 volts electric potential difference (V on the oxide layer of capacitor 1703 _XO).The oxide layer of capacitor is designed in this electric potential difference and punctures, and comes program memory cells with this.In addition, the voltage (V on the selection transistor oxide layer _GO) maximal value be designed to 2 volts.This has prevented to select transistorized oxide layer breakdown.

Next, we consider the influence on the memory cell of selected row and not selected row (" SR/UC ") point of crossing.Shown in preceding table, line V _WROn voltage be 2 volts, column selection line V _COn voltage be 2 volts, line program V _WPOn voltage be 5.5 volts.This makes the voltage V on the capacitor oxide layer _XOIt is 3.5 volts.This can not puncture oxide layer, thereby this unit can not be programmed.This just allows to select transistor to use the superthin grid oxide layer.

Then, we consider the influence on the memory cell of not selected row and selected row (" UR/SC ") point of crossing.Shown in preceding table, line V _WROn voltage be 0 volt, column selection line V _COn voltage be 0 volt, line program V _WPOn voltage be 0 volt.This makes voltage V on the capacitor oxide layer _XOIt is 0 volt.This can not puncture oxide layer, and therefore, this unit can not be programmed.In addition, there is not voltage V _GOPass and select transistorized oxide layer.This just allows to select transistor to use the superthin grid oxide layer again.

Then, we consider the influence on the memory cell of not selected row and not selected row (" UR/UC ") point of crossing.Shown in preceding table, line V _WROn voltage be 0 volt, column selection line V _COn voltage be 2 volts, line program V _WPOn voltage be 0 volt.This makes the voltage V on the capacitor oxide layer _XOIt is 10 volts.This can not puncture oxide layer, and therefore, this unit can not be programmed.In addition, pass the maximum voltage V that selects transistorized oxide layer _GOIt is 2 volts.This just allows to select transistor to use the superthin grid oxide layer again.

Storer can be read in the following method: be provided with on the selected row (" SR ") 1.2 volts read to select voltage, be provided with on the selected row (" SC ") 1.2 volts read column selection voltage.Other all not selected row (" UR ") and not selected row (" UC ") are set to 0 volt.The memory cell of supposing selected row and selected capable point of crossing is programmed.Select transistor 1701 by line V _WROffer 1.2 volts of grid (reading to select voltage), by alignment V _COffer Lou 1.2 volts of voltages.If the unit is programmed, electric current will be from 1.2 volts alignment V _CBe absorbed.If the unit is not programmed, there is not electric current to flow, show that memory cell is not programmed.

Except the memory cell shown in memory array 100 (Fig. 1) and 500 (Fig. 5), in the document of using, oxide layer breakdown various researchs have been carried out.These researchs have pointed out to puncture the suitable voltage of ultra-thin medium, and determine that puncture is controlled.When the superthin grid oxide layer is exposed to following time of stress of voltage induced, will occur in the gate oxide puncturing.Really cutter system is not clear though cause the gate oxide intrinsic breakdown, and breakdown process is a progressive process that arrives hard breakdown (" the HBD ") stage by soft breakdown (" SBD ").A kind ofly puncture the defect center that reason is considered to oxide layer.Can work separately and cause puncture in these defect centers, thereby perhaps trap-charge causes local high electric field and big electric current and a kind of positive feedback condition that causes thermal runaway.Thereby improve manufacturing process and can reduce the appearance that this oxide layer defective reduces this puncture.Capture even the Another reason that punctures is considered to the electronics and the space at various centers in flawless oxide layer, this capturing also can cause thermal runaway.

Memory array 100 shown in Figure 1 is actually an a kind of part of memory integrated circuit, and it comprises the element of many other called optical imaging, such as sensor amplifier, pull-up circuit, word line amplifier, code translator, voltage multiplier or the like.Figure 13 shows an illustrative storer 1600, and it comprises a steering logic 1602, address latch 1604, high-pressure pump 1606, Y code translator 1608, X code translator 1610, input/output (i/o) buffer 1612, a sensor amplifier 1614 and a memory cell array 1616.Memory array may resemble memory array 100 or memory array 500.High-pressure pump 1606 is useful in some topological design, such as the situation of the high programming voltage of the needs shown in the table of Fig. 8 and 9 as 7.0V.High pressure is only supplied with needed line; In Figure 13, only on row or Y line, just need high pressure, as layout pointed in the table of Fig. 8 is desired.Because these elements and these elements all are that technology circle is known with the application of memory array, and running parameter is all very definite, so here will not describe in detail.It is to be noted that storer 1600 is just illustrative, because may need to use many other technology to come memory array is carried out addressing, data are imported into or spread out of memory array, the needed various operating voltage of supply memory array or the like in case of necessity.

Memory cell and array can be applied to various senior technologies (making simultaneously as making n type grid device, p type grid device or two kinds of grid devices), and it is thin that gate medium is accomplished enough, so that adopt one to be lower than voltage that knot presses or the thickest now oxide layer breakdown voltage and to make it stand stress to reach soft breakdown (SBD) or hard breakdown (HBD) when the use of reality.Adopt the MOS technology of different photoetching techniques that many kinds are arranged, but any can use comprises but is not limitation and 0.25 micron, 0.18 micron, 0.15 micron that uses at present usually and 0.13 micron photoetching technique and 0.10 micron of will generally use in the future even better photoetching technique.

The various MOS transistor of using in the various memory cells described here, MOS semitransistor and mos capacitance device all are some normal low voltage logic transistors as a rule, for example, if adopt 0.25 μ m technology, these transistorized superthin grid oxidated layer thickness are on the 50 Izod right sides; If adopt 0.13 μ m technology, these transistorized superthin grid oxidated layer thickness are on the 20 Izod right sides.Voltage on a kind of like this superthin grid oxide layer two ends can temporarily be much higher than V when programming _CC, for V with the integrated circuit of 0.25 μ m technology manufacturing _CCBe generally 2.5V; For the integrated circuit made from 0.13 μ m technology, V _CCBe generally 1.2V.Such super thin oxide layer generally can stand 4 or the voltage of 5V and can not reduce transistor performance.If the selection transistor of its unit is exposed to the voltage (listed voltage is exactly this situation in Fig. 9 table) more than the 4V when memory array adds voltage, the selection transistor of unit preferably adopts thicker gate oxide to make semitransistor or capacitor then adopts the superthin grid oxide layer to make so.Many CMOS logic process can both form the superthin grid oxide layer and be used for the thicker oxide layer of I/O (" I/O ").For example, thicker oxide layer is about 70 dusts for the integrated circuit of 3.3V I/O, is about 50 dusts for the integrated circuit of 2.5V I/O.

Figure 14 has shown first kind of concrete device of the programmed circuit that is applicable to programmable memory array.What Figure 14 showed is the memory cell that Figure 12 uses, and, the circuit of narration and method can easily be fit to foregoing various memory cell.

The programming of the unit by selecting transistor 1701 comprises the puncture of the oxide layer of capacitor 1703.The puncture degree of oxide layer can be controlled by three kinds of parameters: the breakdown current by oxide layer, put on voltage breakdown, oxide layer on the oxide layer and be exposed to time span under electric current and the voltage.Therefore, the programming of time, voltage, these three parameter control capacitors 1703 of electric current.

Have been found that now the variation of time parameter can not regulate the degree of oxide layer breakdown effectively.On the contrary, find that electric current and/or Control of Voltage are the more effective and more direct methods of regulating oxide layer breakdown.

Among Figure 14, memory array 1401 is made up of two row of three row of memory cell 1603.It is many greatly to be applied to physical storage array 1401, but in order clearly to describe the present invention, has only shown a relatively little memory array 1401.Programmed circuit consists of the following components: wordline decoder 1605 (1-2, one of every row), level translator 1607 (1-2, one of every row), adjustable voltage generator 1601, fixedly column voltage generator 1611 (1-3, one of every row), row current control transistor 1609 (1-3, one of every row bit line).

As previously mentioned, the oxide layer of the capacitor 1703 of unit 1603 by puncturing it is programmed.Finish this process by add a voltage to capacitor.Therefore, as previously mentioned with Figure 12,13 relevant, row bit line ground connection (or other low-voltage), and the row word line has a high relatively voltage superimposed via level translator 1607.As follows, in the concrete device of Figure 14, the high-tension exact numerical values recited that adds on the word line of being expert at becomes along with the scope of needs programming.In addition, for an end points giving capacitor 1703 adds the row bit-line voltage and allows electric current to flow through capacitor 1703, wordline decoder 1605 is opened the selection transistor 1701 of unit 1603 selectively.

In a kind of concrete device, the row of memory array 1401 is programmed simultaneously.Therefore, having only a wordline decoder 1605 is " activation " all the time or " opening ".As an example, suppose that the wordline decoder 1605-1 corresponding to first row activates.Wordline decoder 1605-1 will provide a fixed voltage (transistor threshold voltage is big than selecting) to give and the grid of selecting transistor to link to each other, thereby whole selection transistors of first row of memory array 1401 are opened.Perhaps, wordline decoder 1605 only is a simple switch when activating, and gives and selects the grid of transistor 1701 that a voltage is provided.Certainly, also can use other more complicated or sophisticated circuitry or method and finish same task.

Remaining wordline decoder (on all of first row are capable) " unactivated " or " closing ", thus add on the transistorized grid of selection of remaining memory cell that a low-voltage connects separately to them.This causes the selection transistor of every other row to be closed.Therefore, do not have electric current to flow through capacitor and do not have the memory cell of programming with those.

See the memory cell of first row back, select transistor to be unlocked, the row bit line all is placed in low-voltage (typical ground connection or source voltage V _SS).This causes an end points of capacitor 1703 to place electronegative potential.Another end points of capacitor (it has a relative higher voltage superimposed) connects programming row word line via the level translator 1607 of first row.Notice that wordline decoder 1605-1 controls the activation of related level translator 1607-1 in logic.In other words, level translator 1607-1 only just activates when wordline decoder 1605-1 activates.When by from the signal activation of wordline decoder 1605 time, level translator 1607-1 may be taken as simple switch and carry out, and will cause one from adjustable voltage generator 1601, being added in the voltage on the programming row word line.Certainly, also can finish same task with other circuit more complicated or that mix or method.

Although there is a voltage difference at capacitor 1703 two ends,, otherwise can not cause programming unless electric current can flow through capacitor 1703.Figure 14 has shown the path that electric current flows through from the capable word line of programming: pass capacitor 1703, pass and select transistor 1701, until the row bit line.

In the bottom of every row bit line is the row current control transistor 1609 (column voltage generator 1611 controls that it is fixed) of an association.Have only when fixing column voltage generator 1611 and open as a specific row bit line, row current control transistor 1609 just is unlocked, thereby allows electric current to flow through.In addition, row current control transistor 1609 can be controlled the maximum current that flows through the row bit line, is used for program memory cells.

As an example, can suppose the memory cell that needs programming first row, and the memory cell of the secondary series of not programming.In this case, the column voltage generator 1611-1 that is fixed of row oxide-semiconductor control transistors 1609 opens.This allows electric current to flow through capacitor 1703, select transistor 1701, until bit line 1603-1, the result becomes a memory cell that is programmed.Yet the column voltage generator 1611-2 that row oxide-semiconductor control transistors 1609-2 is fixed closes.This does not allow electric current to flow through capacitor 1703, select transistor 1701, until bit line 1603-1, the result becomes a memory cell that is not programmed.Therefore, the programming of memory cell be by by control fixedly this concrete device of column voltage generator 1611 control.

Also have other important aspects in the programmed circuit of Figure 14, can realize the programming that memory cell 1603 is different exactly by the size that control adds voltage on the word line of being expert at.Thereby level translator 1607 (under wordline decoder 1605 control) adds the voltage by 1601 decisions of adjustable voltage generator to the row word line.In an example, the adjustable voltage generator can produce the voltage between one 6 volts to 12 volts, and voltage will pass on the capable word line through level translator 1607.The exemplary voltages output of adjustable voltage generator is by a control signal decision.

By controlling the oxide layer breakdown degree that voltage on the capable word line comes control capacitor 1703.Minimal puncture can be caused near 6 volts low-voltages, and bigger puncture can be caused near 12 volts high voltage.This will influence the electric current sum that flows through capacitor conversely when read operation.In this manner, memory cell 1603 can be stored multi-stage data.Therefore, the ability that changes control voltage on the word line of being expert at provides convenience for the multi-stage data programming.In addition, in some devices, the voltage that changes on the row word line can be used in the programming application of simulating signal.

In addition, the ability that changes control voltage on programming row word line also provides the ability of control programming electric current, thus the power consumption of control programming process.If power consumption is a problem, may use lower program voltage so.In other was used, power problems was not main, but read rate is prior.In this situation, may trend towards using big program current, this can cause the memory cell that has been programmed read rate faster usually.At last, changing the ability of controlling voltage on programming row word line also provides the ability of control programming electric current to avoid that capacitor is damaged.

Figure 15 has shown the concrete device of second kind of programmed circuit, and it comes the control programming electric current by the selection transistor of control store unit 1603.In this device, fixedly high-voltage generator 2001 provides a high fixed voltage by level translator 1607 to programming row word line.In addition, fixedly column voltage generator 1611 with shown in Figure 14 identical.

But, increased some elements that are used for regulating selection transistor 1701 gate voltages.Specifically, increased an adjustable grid voltage generator 2003, it responds according to the control row and exports different voltage.The output of adjustable grid voltage generator 2003 is provided for grid level translator 2005.During operation, wordline decoder 1605 can be used for activating grid level translator 2005, thereby the voltage that adjustable grid voltage generator 2003 provides is delivered on the grid of selecting transistor 1701.As shown in figure 15, all be by wordline decoder 1605 control states of activation corresponding to the high-voltage level converter 1607 of programming row word line with corresponding to the grid level translator 2005 of selecting transistor 1701 grids.In this manner, be applied to select the voltage of transistor gate to come the control programming electric current by control.

At last, in the third concrete device shown in Figure 16, the electric current in the programming process is by 1609 controls of row current control transistor.In this device, be fixed voltage generator 2001 of the adjustable voltage generator 1601 among Figure 14 replaces.This has caused, and capacitor 1703 has a fixed program voltage in the programming process.

Yet the fixedly column voltage generator 1611 among Figure 14 is replaced by the adjustable column voltage generator among Figure 16 2001.As shown in figure 16, each row bit line all has an adjustable column voltage generator 2011.Therefore, in the third device of Figure 16,, just in time can control and flow through the electric current total amount that therefore its neutralization passes through capacitor 1703 by the grid voltage (with adjustable column voltage generator) of control row current control transistor 1609.For example, can change the grid voltage of row current control transistor 1609, thereby can make the electric current of flowing through wherein relevant with grid voltage.

The another one advantage of this device is can finish with a programming step with the multiple level programming of the different units in the delegation.The difference of row current control transistor 1609 grid voltages that can be by different row bit lines, thus distinguish with the memory cell in the delegation.For example, adjustable column voltage generator 2011-1 can provide zero output voltage, causes the memory cell of first row not have electric current to flow, not programming.In addition, adjustable column voltage generator 2011-2 can provide an intermediate output voltage, causes the memory cell of secondary series to have an intermediate electric current to flow and elementary programming.At last, adjustable column voltage generator 2011-3 can provide a high output voltage, causes tertial memory cell that a high current flow and secondary programming are arranged.Thereby, can realize the multiple level programming or even the programming of pure simulating signal of memory cell.

Invention description described here and application thereof are just illustrative, are not to limit invention scope.Here some concrete devices that disclose are had many mutation and modification, and the people who has a common skill in technology circle knows the actual substitute and the equivalent product of various elements in these concrete devices.For example, the various voltages that adopt in each example are illustrative, because people select an accurate magnitude of voltage to disagree in a voltage range, and magnitude of voltage is all relevant with device property in either case.In order to narrate normally used lines kind in the storer, used words such as line, alignment and source line, but some storer has other call to these words.In general, line can be regarded a kind of special selection wire as, and alignment and source line can be regarded special access line as.Here these and other some change and modification that the concrete device that discloses is carried out can not depart from scope of the present invention and central idea.

Claims

1. equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, above-mentioned selection transistor has grid to link to each other with selecting word line, the source links to each other with first end points of above-mentioned data storage elements, leakage links to each other with the row bit line, it is characterized in that the said equipment comprises:

2. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 1, it is characterized in that: described data storage elements is a mos capacitance device.

3. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 1, it is characterized in that: described data storage elements comprises a conducting structure that constitutes above-mentioned second end points, one below above-mentioned conducting structure as the ultra-thin medium of the physical store of data, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first end points.

4. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 3, it is characterized in that: described data storage elements punctures above-mentioned ultra-thin medium by making alive between above-mentioned first end points and second end points and programmes.

5. equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that the said equipment comprises:

An adjustable grid voltage generator provides variable voltage output,

6. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 5, it is characterized in that: described data storage elements is a mos capacitance device.

7. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 5, it is characterized in that: described data storage elements comprises: a conducting structure constitutes above-mentioned second terminal, a ultra-thin medium that below above-mentioned conducting structure, is used as the physical store of data, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first terminal.

8. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 7, it is characterized in that: described data storage elements punctures above-mentioned ultra-thin medium by making alive between above-mentioned first terminal and second terminal and programmes.

9. equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that the said equipment comprises:

An adjustable column voltage generator provides a variable voltage output,

10. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 9, it is characterized in that: described data storage elements is a mos capacitance device.

11. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 9, it is characterized in that: described data storage elements, comprise a conducting structure that constitutes above-mentioned second terminal, one below above-mentioned conducting structure as the ultra-thin medium of data physical store, a doped semiconductor zone that under ultra-thin medium and conducting structure, forms above-mentioned first terminal.

12. by the described equipment that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 11, it is characterized in that: described data storage elements punctures above-mentioned ultra-thin medium by making alive between above-mentioned first terminal and second terminal and programmes.

13. method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that said method comprises:

Allow electric current to flow through above-mentioned row bit line;

14. method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that said method comprises:

Allow electric current to flow through above-mentioned row bit line;

15. method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon, memory cell comprises one and selects transistor and a data memory element, the transistorized grid of above-mentioned selection connect selects word line, the source connects first terminal of above-mentioned data storage elements, leak connection row bit line, it is characterized in that said method comprises:

Open above-mentioned selection transistor,

16. by the described method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 15, it is characterized in that: described adjusting current flow is that the row current control transistor is finished.

17. by the described method that is used to utilize the memory cell programming of ultra-thin medium breakdown phenomenon of claim 16, it is characterized in that: above-mentioned row current control transistor is regulated by an adjustable column voltage generator.