CN1297283A - Current-type step gain controller circuit for digital technology - Google Patents
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Abstract
A current-mode step gain controller circuit for digital technology features that with the current-mode gain regulation, more modules composed of PMOS or NMOS transistor are used for multi-stage control of gain, the resistor match is replaced by transistor match for higher gain control accuracy, and the universal operating amplifiers are used, so adapting integrated circuit.
Description
The present invention relates to a kind of type step gain controller circuit, particularly relate to a kind of current-type step gain controller circuit of digital technology.
In the prior art, control general using operational amplifier and two variable resistors of voltage gain are realized that the type step gain controller circuit schematic diagram of its simplification as shown in Figure 1.In Fig. 1, Vin is the voltage signal of input, and Vout is the voltage signal of output, and resistance R 1 and R2 are for adjusting the variable of gain
Resistance.The performance of setting operational amplifier is desirable, can obtain:
According to following formula,, can obtain the voltage gain of stepping control when the resistance that changes R1 and R2.In the ordinary course of things, change the resistance of feedback resistance R1, become more readily available gain by Digital Signals.For example as R1 during by short circuit, voltage gain is 0DB; When R1=R2, voltage gain is 6DB etc.
Fig. 2 is an example with the step gain circuit of 5bits Digital Signals, shows the circuit theory diagrams of detailed step gain control.Wherein, Vin is the voltage signal of input, and Vout is the voltage signal of output, b0b1b2b3b4 is the 5 digital bit input signals that carry out step gain control, 5-32 decoder (decoder) is deciphered the digital signal of input, and its output has only one to be 1 at any time, and all the other are 0.32 way switch sw00, sw01, sw02 are controlled in 32 tunnel outputs of 5-32 decoder respectively ... sw31, when the digital controlled signal of correspondence was input as 1, this switch was in conducting state.For example when digital controlled signal be input as b0b1b2b3b4=00000 the time, switch sw00 is switched on, rest switch is closed; Sw01 is switched on when b0b1b2b3b4=00001, and rest switch is closed.When the b0b1b2b3b4=11111 of digital controlled signal, switch sw31 is switched on, and rest switch is closed.
The work of configuration switch is desirable, when being input as b0b1b2b3b4=00000, and switch sw00 conducting, at this moment, the negative input end of operational amplifier (opamp) and output short circuit do not have resistance to enter feedback loop, so obtaining the gain in loop is 1, i.e. the ODB voltage gain.When switch sw01 conducting, resistance R _ f 0 is access in feedback loop; When switch sw02 conducting, resistance R _ f 0, Rf1 is access in feedback loop.The rest may be inferred, when switch sw31 conducting, and resistance R _ f 0, Rf1 ... Rf31 is access in feedback loop.
As from the foregoing, the number that is access in the resistance of feedback loop can be expressed as:
n=16
*b0+8
*b1+4
*b2+2
*b3+b4
In following formula, n is and the corresponding 10 system numerical value of 2 system digital controlled signals.Set the b0b1b2b3b4=10001 that is input as of digital controlled signal, then the numerical value of Dui Ying n is 17, and the resistance that promptly is access in feedback loop is 17, that is resistance R _ f 0, Rf1, Rf2 ... Rf16.
By above analysis as can be known, calculate the voltage gain in whole loop, must utilize earlier the digital controlled signal of input to calculate corresponding 10 system numerical value n, will insert the resistance addition of n resistance in the loop then, obtain inserting total resistance of the feedback resistance in loop.Utilize above-mentioned gain calculating formula, can calculate and the corresponding voltage gain of digital controlled signal.
When switch controlling signal swn conducting, the rest switch signal at stop, this moment, the voltage signal gain was:
In following formula, molecule is the total resistance that inserts the resistance of feedback loop.This gain calculating formula is identical with above-mentioned elementary cell.
Press the gain control circuit that resistance mode constitutes for above, because the imperfect work of MOS switch etc.,, make that the resistance of resistance R 2 is bigger, thereby control precision will be subjected to bigger influence as certain conducting resistance etc.Simultaneously, because the existence of more much resistance, gain control circuit can not utilize the digital integrated circuit manufacturing process of standard to carry out integrated.
In addition, in above circuit, gain can increase progressively according to the DB value, but for the resistance in the feedback loop, since with increase progressively DB value corresponding increase progressively resistance right and wrong regular variations, so 32 resistance in the feedback loop, each has the different resistances that increases progressively.And in the coupling of resistance, when the ratio of two resistance is an integer, especially be 1,2,4,8 ... the time matching performance best.So for the resistors match of the non-integer proportionate relationship in feedback loop, it is difficult to realize in LAYOUT (placement-and-routing).Table 1 has been listed the relation between DB gain and the actual gain multiple.
Table 1
| The DB gain | Actual multiple | The DB gain | Actual multiple | The DB gain | Actual multiple | The DB gain | Actual multiple |
| ????1 | ?1.12 | ????9 | ?2.82 | ????17 | ?7.08 | ????25 | ?17.78 |
| ????2 | ?1.26 | ????10 | ?3.16 | ????18 | ?7.94 | ????26 | ?19.95 |
| ????3 | ?1.41 | ????11 | ?3.55 | ????19 | ?8.91 | ????27 | ?22.39 |
| ????4 | ?1.58 | ????12 | ?3.98 | ????20 | ?10 | ????28 | ?25.12 |
| ????5 | ?1.78 | ????13 | ?4.47 | ????21 | ?11.22 | ????29 | ?28.18 |
| ????6 | ??2 | ????14 | ?5.01 | ????22 | ?12.59 | ????30 | ?31.62 |
| ????7 | ?2.24 | ????15 | ?5.62 | ????23 | ?14.13 | ????31 | ?35.48 |
When gain was 1DB, the resistance that needs to increase access was:
Rf0=(1.12-1.0)
*R2=0.12
*R2
When gain was 2DB, the resistance that needs to increase access was:
Rf1=(1.26-1.12)
*R2=0.24
*R2
When gain was 31DB, the access resistance that needs to increase was:
Rf31=(35.48-31.62)
*R2=3.86
*R2
As seen from the above analysis, for the DB gain of stepping, its corresponding resistance variation does not possess regularity, so the coupling of resistance is very difficult.In addition, in the circuit of reality, because the conducting resistance Rsw (on) of switch is not very little, therefore it is one of the factor that must consider in the step gain circuit of accurately control.When gain was nDB, actual voltage signal gain should be:
In following formula, when total resistance of the resistance that inserts feedback loop is sued for peace, considered the influence of the conducting resistance of switch.Owing in the loop of any gain, have only a switch to be access in feedback loop, so in following formula, only increased the resistance of the conducting resistance of a switch.
After the stepping accuracy in the gain control circuit is determined, need the conducting resistance and the R2 of switch be adjusted, to satisfy the requirement of control precision.For example the conducting resistance of switch is 1K ohm, and the stepping control precision of design is 5%, considers the absolute error of resistance R 2 when 0DB gains, and the value of resistance R 2 should be greater than 30K ohm.Therefore in the ordinary course of things, the resistance of R2 is bigger, thereby the resistance in the circuit will utilize high resistance polysilicon technology to realize, and is difficult to utilize the digital integrated circuit manufacturing process of standard to carry out integrated.
In order to solve the resistors match problem that circuit shown in Figure 2 exists, circuit shown in Figure 3 improves the circuit of Fig. 2.
In Fig. 3 circuit, Vin is the voltage signal of input, and Vout is the voltage signal of output, b[0--4] for carrying out the digital signal input of step gain control.The difference of circuit shown in Figure 3 and foregoing circuit is, has increased the feedback resistance Rb2 of 3 ground connection, Rb3, Rb4.In this circuit, the feedback resistance of 4 ground connection is divided into 4 sections with step gain: 0-7DB section, 8-15DB section, 16-23DB section and 24-31DB section.Because the step gain of each section is 8DB, so 4 sections can be realized the step gain of 32DB.Aspect the circuit realization.32 resistance are divided into 4 groups of resistance groups that match each other, and each resistance group's resistance number is 8.
In the circuit of Fig. 3, though the resistance group is mated, 8 resistance of resistance group inside remain does not possess the normalization matching, so in resistance group's implementation, still have bigger difficulty.
In the circuit of Fig. 2 and Fig. 3, another problem of existence is the design of operational amplifier.For the gain controlling of high-frequency signal, when 31DB gained, the gain bandwidth product GBW that requires operational amplifier was about 400MHz or higher as the analog signal of 1MHz.With the technology of digital integrated circuit compatibility in, the operational amplifier of high target is realized than difficult.The compensation of operational amplifier when 0DB gains is the darkest.When loop gain is big, the compensation depth of operational amplifier need be reduced to improve the GBW of operational amplifier.So when different gains,, may need different compensation techniques to operational amplifier according to the manufacturing process of integrated circuit.
In addition, in the circuit of Fig. 2 and Fig. 3, owing to introduced decoding circuit, thereby increased the area of system, reduced the noiseproof feature of system.
In sum, above-mentioned two kinds of existing schemes all have following defective:
(1) coupling of resistance is comparatively difficult;
(2) need high resistance polysilicon technology;
(3) conducting resistance of switch exerts an influence to the precision of stepping control;
(4), need different compensation techniques to the having relatively high expectations of operational amplifier;
(5) need the support of decoding circuit, as the 5-32 decoder circuit of introducing previously.
Wherein, because the problem of above (1), (2) makes that existing voltage control circuit and digital ASIC technology can not be compatible fully.
The objective of the invention is to overcome the shortcoming of prior art, a kind of current-type step gain controller circuit of digital technology is provided, adjust by utilizing the current-mode gain, the coupling of resistance is converted to transistorized coupling, thereby the problem of resistors match is resolved, and improves the gain controlling precision.And utilize unified operational amplifier, do not need extra compensation technique, simultaneously the digits deleted decoding circuit.Make the present invention can be suitable for the integrated circuit manufacturing.
In order to solve the problem of above-mentioned existence, the current-type step gain controller circuit of digital technology of the present invention, constitute by gain being divided into multistage a plurality of modules of controlling, by a plurality of digital control input signal INlogic are fetched the step gain control that realizes electric current with common-mode feedback input current Incmfb mutually with the corresponding ports of each module, the analog input signal port of analog input signal electric current I nsignal and the 1st module joins, the current output terminal Iout of each module joins with the analog input signal port of next stage module successively, and the current output terminal Iout of afterbody module is the current output terminal of whole current-type step gain controller circuit.
In described a plurality of modules, each module comprises A, B, C, D, E district, and PMOS transistor parallel connection that the A district is leaked altogether by m cascade and grid are connected with drain electrode and constitute; The B district is formed in parallel by the PMOS transistor that n cascade leaks altogether; C district and D district are formed in parallel by the nmos pass transistor that m cascade leaks altogether, and each grid is connected with each drain electrode in the C district; The E district is formed in parallel by the nmos pass transistor that n cascade leaks altogether; Wherein, each source terminal in A district links to each other with each source terminal in B district and meets source voltage VDD, and each gate terminal in A district links to each other with each gate terminal in B district, and constitutes the input port of common-mode feedback input current; Each gate terminal in C, D, E district links to each other and constitutes the input port of analog input signal Iinsignal, each source terminal in C, D, E district links to each other and ground connection, but each gate terminal in A, B district selectively links to each other with each source electrode in C, D, E district or with each drain electrode end in D district by path selector switch (SW1); But each drain electrode end in E district links to each other with each source terminal in A, B district or with each drain electrode end in D district by path selector switch (SW2); Switch (SW1) and (SW2) by digital control input signal INlogic control; Contact between each drain electrode end in current output terminal and above-mentioned switch (SW1) and above-mentioned D district is connected.
Described a plurality of module also can have another kind of structure, and promptly each module comprises A, B, C, D, E district, and nmos pass transistor parallel connection that the A district is leaked altogether by m cascade and grid are connected with drain electrode and constitute; The B district is formed in parallel by the nmos pass transistor that n cascade leaks altogether; C district and D district are formed in parallel by the PMOS transistor that m cascade leaks altogether, and each grid is connected with each drain electrode in the C district; The E district is formed in parallel by the PMOS transistor that n cascade leaks altogether; Wherein, each gate terminal in A, B district links to each other and constitutes the input port of common-mode feedback input current Iincmfb, each source terminal in A, B district also ground connection that links to each other; Each grid in C, D, E district links to each other and constitutes the input port of analog input signal electric current I insignal, but each gate terminal in C, D, E district selectively links to each other with each source terminal in A district by path selector switch (SW1), or links to each other with each source terminal in A, B interval by a current mirror (M1); But each drain electrode end in B district by path selector switch (SW2) selectively with each source terminal in C, D, E district or with above-mentioned current mirror (M1) but link to each other with contact between above-mentioned selector switch (SW1); Each drain electrode end in D district with above-mentioned current mirror (M1) but link to each other with contact between above-mentioned selector switch (SW1); Switch (SW1) and (SW2) by step gain digital input signals INlogic control, output Iout is that earth terminal links to each other by each source electrode in current mirror (M2) and A, B interval.
Described a plurality of module is made by the P trap or the N trap digital technology of integrated circuit.
Described switch (SW1) and (SW2) constitute by 2 nmos pass transistors or 2 PMOS transistors.
Described switch (SW1) and (SW2) control by step gain digital input signals INlogic.
The PMOS transistor in above-mentioned each module or the number m of nmos pass transistor and n can have nothing in common with each other, and by setting PMOS transistor or the number m of nmos pass transistor and the ratio of n in each module, can obtain the different current gain of each module.
Above-mentioned current output terminal Iout is by a drain electrode output that is added with the nmos pass transistor of bias voltage Vbias at grid.
When the module number of the multistage current gain control of above-mentioned formation had K, the current gain of I module was 2
(I-1)DB, wherein I＜K.When described module was odd number when the progression of cascade, the AC signal of output was opposite with digital controlled signal polarity; When the progression of cascade is even number, the AC signal of output and digital controlled signal polarity and digital controlled signal polarity.
Useful effect of the present invention is:
In circuit design of the present invention, introduced the common mode negative feedback current, utilize the relation of DC component in common mode current and the signal code, the DC component of signal is carried out part payment, make AC signal is amplified and kept total DC component constant.The main feature of current-mode is: (1) does not need the operational amplifier in the circuit is carried out extra compensation; (2) control precision can be utilized with gain corresponding maximum common multiple and minimum common divisor and adjust, and precision is relevant with the MOS transistor number that realizes gain within the specific limits, and less with the relation of other factors; (3) control to step gain can utilize the input of digital signal directly to carry out, and does not need the auxiliary of decoder circuit.
In the present invention, at the matching problem of step gain dependent resistor, traditional voltage gain control model is converted to the current gain control model.Because the gain controlling of current-mode depends on transistorized coupling, so thoroughly eliminated the dependence to resistors match, has solved the compatibling problem with digital integrated circuit technology.
In the prior art, owing to be the voltage gain pattern, when different voltage gains, be different to the influence and the requirement of operational amplifier, so need different compensation techniques, get different numerical value etc. with the difference of gain as the building-out capacitor of operational amplifier inside.In the present invention,, need not compensate, the pressure of operational amplifier is alleviated greatly owing to adopt current-mode.
In the present invention, owing to adopt current-mode, the conducting resistance of switch has obtained effective inhibition to the influence of gain controlling precision.In theory, the conducting resistance of switch can be ignored to the influence of gain accuracy, thereby has improved control precision greatly.
In the prior art, the control of switch is realized by decoder, because any one has only a switch conduction constantly, so decoder circuit is complicated, use more switch and resistance, and the precision of each switch control all is 1DB, thereby brings bigger difficulty to design.Gain control circuit of the present invention is divided according to the weight of 2 systems, promptly divides 1DB, 2DB, 4DB, 8DB and 16DB totally 5 gain control module, and digital signal can directly be carried out the control of gain, thereby has omitted decoder.
Fig. 1 is the type step gain controller circuit of the simplification of prior art.
Fig. 2 is the 0-31DB type step gain controller circuit of prior art.
Fig. 3 is another 0-31DB type step gain controller circuit of prior art.
Fig. 4 is digital gain control input of the present invention and the corresponding relation shown in the sine wave.
Fig. 5 is 5 grades of current-type step gain controller circuits of the present invention.
Fig. 6 is the circuit structure diagram with each module among Fig. 5 of P trap technology manufacturing.
Fig. 7 is the circuit structure diagram with each module among Fig. 5 of N-well process manufacturing.
The present invention is further illustrated by the following examples and in conjunction with the accompanying drawings.
Fig. 4 has schematically illustrated the present invention when sine wave is imported, the relation between digital input control signal and the gain.Wherein sine wave has passed through simplification.When digital signal was input as 0, output equated that with input gaining is 0DB; When digital signal was input as 31, sine wave output was 35.62 times of input sine wave, i.e. 31DB.As can be seen from Figure 4, obtaining amplifying signal is AC signal, and the DC component of analog signal remains unchanged, therefore following assisting of no capacitance, has realized only amplifying the purpose of AC signal.Simultaneously, because the big bandwidth of the direct current of current-mode payment circuit makes signal in a bigger frequency domain, DC component is suppressed effectively.So the common-mode voltage rejection ratio (CMRR) of current-mode can keep a stable value in the frequency domain of a broad.
Fig. 5 is the circuit theory diagrams of current-type step gain controller control.In Fig. 5, by 5 modules gain is divided into 5 grades and controls, be respectively 1DB controlled stage, 2DB controlled stage, 4DB controlled stage, 8DB controlled stage and 16DB controlled stage.IN0, IN1, IN2, IN3, IN4 are the digital signal input of control step gain.Incmfbl, Incmfb2, Incmfb3, Incmfb4, Incmfb5 are the input port of common-mode feedback electric current, the input end of analog signal mouth of Insignal for gaining and adjusting, Vdd and Vss are respectively power supply and ground, Vbias is for suppressing the voltage bias of raceway groove mudulation effect, and Iout is final electric current output.When digital control input IN0IN1IN2IN3IN4 was 00000, the gain of the gain control stages of 5 cascades all was 0DB, so the gain of signal is 0DB; When digital control input IN0IN1IN2IN3IN4 is 00001, the conducting of 1DB gain control stages, the gain of all the other controlled stage gains is 0DB, so the gain of signal is 1DB; When digital control input IN0IN1IN2IN3IN4 is 00010, the conducting of 2DB gain control stages, the gain 0DB of all the other gain control stages is so signal gain is 2DB.The rest may be inferred, and when digital control input signal IN0IN1IN2IN3IN4 was 10000, the conducting of 16DB gain control stages, the gain of all the other gain control stages were 0DB, so the overall gain of signal is 16DB; When digital control input signal IN0IN1IN2IN3IN4 was 11111, all gain control stages all were switched on, and the overall gain of signal is 1+2+4+8+16=31DB.
In Fig. 5, the formation of each module is relevant with the manufacturing process of integrated circuit.Because in the technology of Typical Digital integrated circuit, only there are P trap technology or N-well process, generally can not utilize P trap and N-well process simultaneously, so module has two kinds of methods for designing: be directed to the design of nmos pass transistor in the P trap and be directed to the transistorized design of PMOS in the N trap.The principle of two kinds of methods for designing is identical, and just to the amplification aspect of signal, its polarity is opposite.
Utilize the P trap or the N trap of integrated circuit, the step gain Control current is carried out different designs, can improve the signal to noise ratio (snr) of circuit.For the N ditch device in the P trap, as nmos pass transistor etc., because its substrate is subjected to the independent insulation blocking of P trap, so they are subjected to extraneous interference less, signal to noise ratio is higher.And,, be subjected to the interference of other devices in the circuit easily because its substrate is public with other devices for the PMOS device, as high power device etc., so its signal to noise ratio is relatively poor.Equally, if N-well process, the signal to noise ratio of PMOS device better and the signal to noise ratio of nmos device is relatively poor.Therefore should select different implementation methods according to the signal to noise ratio requirement of system and the type of technology.
In Fig. 6, show the type step gain controller circuit module of utilizing P trap technology to realize.This module comprises A, B, C, D, E five parts, and A district and B district constitute the gain stage of common-mode feedback electric current, and C district and D district constitute the copy level of signal code, and C district and E district constitute the gain stage of signal code; The A district is formed in parallel by the PMOS transistor that m cascade leaks altogether, the B district is formed in parallel by the PMOS transistor that n cascade leaks altogether, C district and D district are formed in parallel by the nmos pass transistor that m cascade leaks altogether, and the E district is formed in parallel by the nmos pass transistor that n cascade leaks altogether; Iincmfb is a common-mode feedback current input terminal mouth, the input port of the analog signal that Iinsignal adjusts for gaining, INlogic is the digital control input port of step gain, Vbias is a bias voltage, Iout is the current output terminal mouth, and Icollect is the electric current collection node.
Common-mode feedback input port Iincmfb is a direct current, and signal input port Iinsignal adds alternating current IAC for direct current IDC.In the ordinary course of things, the direct current of common-mode feedback input port equates with the direct-current component of signal input port.Bias voltage Vbias makes the voltage of node Icollect fix, thereby prevents the channel length modulation effect of MOS transistor effectively.
The electric current of setting the common-mode feedback input port is:
Iincmfb=IDC
The electric current of signal input port is:
Iinsignal=IDC+IAC
Frame of broken lines A district and the B district lived in the drawings, always total m+n PMOS transistor is owing to its grid links together, so the electric current that flows through in each PMOS transistor is identical.For m the transistor in A district, because its total current is Iincmfb, so the electric current of the single transistor in the A district is Iincmfb/m.In the B district, n transistor drain links together, and the electric current of single transistor is identical with the device in A district, so n the transistorized stream that gathers of PMOS, the electric current that promptly inserts switch SW 1 is:
IS
W1=n/m
*IDC
In following formula, n is the transistorized number of PMOS in the B district, and m is the transistorized number of PMOS in the A district.At the beginning of can seeing from following formula, insert the common-mode feedback electric current of switch sw1, with the proportional relation of transistor number in A district and B district.
Equally, the electric current that inserts switch sw2 is only relevant with the number of the nmos pass transistor in C district and E district.Through similarly analyzing with the front, the electric current that can draw access switch sw2 is:
I
SW2=n/m
*(I
DC+I
AC)
When the digital gain control signal was 0, switch sw1 made electric current I sw1 directly insert ground GND, and switch sw2 makes electric current I sw2 directly insert power vd D.Therefore, at electric current collection node Icollect, gathering of the single current that total current provides for m nmos pass transistor by the D district, the circuit structure that compares C district and D district, the proportionate relationship that can obtain the input current in the output current in D district and C district is m: m, be that the electric current that gathers that D district transistor provides equates with the injection current in C district, also promptly:
I
OUT=Icollect=Iinsignal=I
DC+I
AC
This moment, output current equated that with the signal code of input promptly current gain is 0DB as can be seen.
When the digital gain control signal was 1, switch sw1 inserted electric current collection node Icollect with electric current I sw1, and switch sw2 inserts electric current collection node Icollect with electric current I sw2.Therefore, at node Icollect, total current is:
Iout=Iinsignal+I
SW2-I
SW1=I
DC+(1+n/m)I
AC
Through above analysis, can draw in gain control circuit, the gain of AC signal be (1+n/m) times, direct current signal remains unchanged.In the gain control circuit of cascade, each level is all amplified AC signal and is kept DC component constant.And among the gain n/m of AC signal, n is B district and E district, and m is the transistorized number in A district, C district and D district.M is individual to obtain effective current gain with n transistorized coupling so the present invention can utilize, thereby has solved the regularity problem in the coupling effectively.
In the electric current input of the electric current input of setting common-mode feedback and signal, DC component is identical in more than analyzing.In the circuit of reality, may there be certain difference in both.Simultaneously, the minor variations of DC component can be from not the matching of PMOS transistor and nmos pass transistor n/m, and the deviation of total DC component can be expressed as:
∑ΔI
DC=ΔI
DC+Δ(n/m)
*I
DC
The minor variations of two DC component only can influence the working point of circuit, can not produce distortion to AC signal, so the present invention requires only to be subjected to the influence of gain controlling precision to the coupling of MOS transistor.
In above circuit, the value of n and m can only be an integer, and through normalized, its value is as shown in the table.
| The DB yield value | The n value | The M value |
| ????1 | ????1 | ????8 |
| ????2 | ????1 | ????4 |
| ????4 | ????6 | ????10 |
| ????8 | ????3 | ????2 |
| ????16 | ????16 | ????3 |
After adjusting through normalization, when digital controlled signal be input as 11111 the time, total gain is 35.63 times, with 35.48 times difference of 31DB gain less than 1%.
In foregoing circuit, provided the step gain control implementation that utilizes P trap technology.The implementation of the step gain control that utilizes N-well process below will be described.In N-well process, utilize the PMOS transistor to carry out the conversion of signal, can realize step gain control equally.Fig. 7 shows the type step gain controller circuit that utilizes N-well process to realize, this circuit comprises A, B, C, D, E five parts, A district and B district constitute the gain stage of common-mode feedback electric current, and C district and D district constitute the copy level of signal code, and C district and E district constitute the gain stage of signal code; The A district is formed in parallel by the nmos pass transistor that m cascade leaks altogether, B is formed in parallel by the nmos pass transistor that n cascade leaks altogether, C district and D district are formed in parallel by the PMOS transistor that m cascade leaks altogether, the E district is formed in parallel by the PMOS transistor that n cascade leaks altogether, Iincmfb is a common-mode feedback current input terminal mouth, Iinsignal is the input port of signal, the digital control input port of INlogic step gain, Vbias is a bias voltage, Iout is the current output terminal mouth, and Icollect is the electric current collection node.
By similarly analyzing with the front, can obtain when INlogic=0, the electric current of output is:
Iout=I
DC-I
AC
Can obtain from following formula, polarity is opposite with the AC signal current of input is equal for the AC signal current of output, i.e. the gain of electric current is 0DB phase phasic difference 180 degree.
When digital gain control signal INlogic=1, the electric current of output is:
Iout=I
DC-(1+n/m)I
AC
Equally, at the beginning of can getting from following formula, the gain of AC signal is (1+n/m) but polarity is opposite.
By above analysis as can be known, the step gain Control current for the PMOS transistor that utilizes in the N trap is realized when the progression of cascade is odd number, obtains the corresponding and opposite polarity AC signal with digital controlled signal of gain; When the progression of cascade is even number, obtain the cascade signal that polarity is identical with digital controlled signal is corresponding that gains.
More than describe the present invention by preferred embodiment, but these embodiment are used for limiting the present invention.All in improvement and the replacement done without prejudice to spirit of the present invention and content, all should be considered as protection scope of the present invention.
Claims (11)
1. the current-type step gain controller circuit of a digital technology, constitute by gain being divided into multistage a plurality of modules of controlling, by a plurality of digital control input signal INlogic and common-mode feedback input current Iincmfb and the corresponding ports of each module being fetched mutually the step gain of Control current, the analog input signal port of analog input signal electric current I nsignal and the 1st module joins, the current output terminal Iout of each module joins with the analog input signal port of next stage module successively, and the current output terminal Iout of afterbody module is the current output terminal of whole current-type step gain controller circuit.
2. according to the current-type step gain controller circuit of the described digital technology of claim 1, it is characterized in that, in described a plurality of modules, each module comprises A, B, C, D, E district, and PMOS transistor parallel connection that the A district is leaked altogether by m cascade and grid are connected with drain electrode and constitute; The B district is formed in parallel by the PMOS transistor that n cascade leaks altogether; C district and D district are formed in parallel by the nmos pass transistor that m cascade leaks altogether, and each grid is connected with each drain electrode in the C district; The E district is formed in parallel by the nmos pass transistor that n cascade leaks altogether; Wherein, each source terminal in A district links to each other with each source terminal in B district and meets source voltage VDD, and each gate terminal in A district links to each other with each gate terminal in B district, and constitutes the input port of common-mode feedback input current; Each gate terminal in C, D, E district links to each other and constitutes the input port of analog input signal Iinsignal, each source terminal in C, D, E district links to each other and ground connection, but each gate terminal in A, B district selectively links to each other with each source electrode in C, D, E district or with each drain electrode end in D district by path selector switch (SW1); But each drain electrode end in E district links to each other with each source terminal in A, B district or with each drain electrode end in D district by path selector switch (SW2); Switch (SW1) and (SW2) by digital control input signal INlogic control; Contact between each drain electrode end in current output terminal and above-mentioned switch (SW1) and above-mentioned D district is connected.
3. according to the current-type step gain controller circuit of the described digital technology of claim 1, it is characterized in that, in described a plurality of modules, each module comprises A, B, C, D, E district, and nmos pass transistor parallel connection that the A district is leaked altogether by m cascade and grid are connected with drain electrode and constitute; The B district is formed in parallel by the nmos pass transistor that n cascade leaks altogether; C district and D district are formed in parallel by the PMOS transistor that m cascade leaks altogether, and each grid is connected with each drain electrode in the C district; The E district is formed in parallel by the PMOS transistor that n cascade leaks altogether; Wherein, each gate terminal in A, B district links to each other and constitutes the input port of common-mode feedback input current Iincmfb, each source terminal in A, B district also ground connection that links to each other; Each grid in C, D, E district links to each other and constitutes the input port of analog input signal electric current I insignal, but each gate terminal in C, D, E district selectively links to each other with each source terminal in A district by path selector switch (SW1), or links to each other with each source terminal in A, B interval by a current mirror (M1); But each drain electrode end in B district by path selector switch (SW2) selectively with each source terminal in C, D, E district or with above-mentioned current mirror (M1) but link to each other with contact between above-mentioned selector switch (SW1); Each drain electrode end in D district with above-mentioned current mirror (M1) but link to each other with contact between above-mentioned selector switch (SW1); Switch (SW1) and (SW2) by step gain digital input signals INlogic control, output Iout is that earth terminal links to each other by each source electrode in current mirror (M2) and A, B interval.
4. the current-type step gain controller circuit of digital technology according to claim 2 is characterized in that, described a plurality of modules are made by the P trap digital technology of integrated circuit.
5. the current-type step gain controller circuit of digital technology according to claim 3 is characterized in that, described a plurality of modules are made by the N trap digital technology of integrated circuit.
6. according to the current-type step gain controller circuit of claim 2 or 3 described digital technologies, it is characterized in that described switch (SW1) and (SW2) constitute by 2 nmos pass transistors or 2 PMOS transistors.
7. according to claim 2 or 3 described digital technology current-type step gain controller circuits, it is characterized in that described switch (SW1) and (SW2) control by step gain digital input signals INlogic.
8. according to the current-type step gain controller circuit of claim 2 or 3 described digital technologies, it is characterized in that, the PMOS transistor in above-mentioned each module or the number m of nmos pass transistor and n can have nothing in common with each other, by setting PMOS transistor or the number m of nmos pass transistor and the ratio of n in each module, can obtain the different current gain of each module.
9. the current-type step gain controller circuit of digital technology according to claim 1 is characterized in that, above-mentioned current output terminal Iout is by a drain electrode output that is added with the nmos pass transistor of bias voltage Vbias at grid.
10. according to the current-type step gain controller circuit of claim 2 or 3 described digital technologies, it is characterized in that when the module number of the multistage current gain control of above-mentioned formation had K, the current gain of I module was 2
(I-1)DB, wherein I＜K.
11. the current-type step gain controller circuit of digital technology according to claim 3 is characterized in that, when described module was odd number when the progression of cascade, the AC signal of output was opposite with digital controlled signal polarity; When the progression of cascade was even number, the AC signal of output was identical with digital controlled signal polarity with digital controlled signal polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991237358A CN1138340C (en) | 1999-11-18 | 1999-11-18 | Current-type step gain controller circuit for digital technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991237358A CN1138340C (en) | 1999-11-18 | 1999-11-18 | Current-type step gain controller circuit for digital technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1297283A true CN1297283A (en) | 2001-05-30 |
| CN1138340C CN1138340C (en) | 2004-02-11 |
Family
ID=5282948
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991237358A Expired - Lifetime CN1138340C (en) | 1999-11-18 | 1999-11-18 | Current-type step gain controller circuit for digital technology |
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| Country | Link |
|---|---|
| CN (1) | CN1138340C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100430732C (en) * | 2002-12-17 | 2008-11-05 | 松下电器产业株式会社 | Amplifier with gain in direct proportion to power voltage |
| WO2012051739A1 (en) * | 2010-10-21 | 2012-04-26 | Integrated Device Technology, Inc. | Switch used in programmable gain amplifilier and programmable gain amplifilier |
| CN104113212A (en) * | 2013-03-15 | 2014-10-22 | 英特尔公司 | Current Balancing, Current Sensor, And Phase Balancing Apparatus And Method For A Voltage Regulator |
-
1999
- 1999-11-18 CN CNB991237358A patent/CN1138340C/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100430732C (en) * | 2002-12-17 | 2008-11-05 | 松下电器产业株式会社 | Amplifier with gain in direct proportion to power voltage |
| WO2012051739A1 (en) * | 2010-10-21 | 2012-04-26 | Integrated Device Technology, Inc. | Switch used in programmable gain amplifilier and programmable gain amplifilier |
| US8279007B2 (en) | 2010-10-21 | 2012-10-02 | Integrated Device Technology, Inc. | Switch for use in a programmable gain amplifier |
| CN104113212A (en) * | 2013-03-15 | 2014-10-22 | 英特尔公司 | Current Balancing, Current Sensor, And Phase Balancing Apparatus And Method For A Voltage Regulator |
| US9733282B2 (en) | 2013-03-15 | 2017-08-15 | Intel Corporation | Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator |
| US10184961B2 (en) | 2013-03-15 | 2019-01-22 | Intel Corporation | Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator |
| US10641799B2 (en) | 2013-03-15 | 2020-05-05 | Intel Corporation | Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator |
| US11193961B2 (en) | 2013-03-15 | 2021-12-07 | Intel Corporation | Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1138340C (en) | 2004-02-11 |
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