CN1295781C - Base plate for encapsulating semiconductor and semiconductor device - Google Patents
Base plate for encapsulating semiconductor and semiconductor device Download PDFInfo
- Publication number
- CN1295781C CN1295781C CNB02149326XA CN02149326A CN1295781C CN 1295781 C CN1295781 C CN 1295781C CN B02149326X A CNB02149326X A CN B02149326XA CN 02149326 A CN02149326 A CN 02149326A CN 1295781 C CN1295781 C CN 1295781C
- Authority
- CN
- China
- Prior art keywords
- wiring layer
- semiconductor device
- wafer
- pad portions
- pad
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a base plate for packaging a semiconductor, which can effectively enhance the antistatic discharging capability of a semiconductor device. The present invention comprises a first wiring layer, a second wiring layer and an inner wiring layer. The semiconductor device comprises a base plate and a wafer, wherein the base plate is provided with a first wiring layer, a second wiring layer and an inner wiring layer, the wafer is arranged on the first wiring layer of the base plate, and a pad part of the wafer is electrically connected with a first pad part. The other semiconductor device comprises a base plate and a wafer, wherein the base plate is provided with a first wiring layer, a second wiring layer and an inner wiring layer. The lower surface of the base plate is provided with a plurality of second pad parts and at least one shielding part. At least one of the second pad parts is not electrically connected with the first pad part. The shielding part is positioned around the second parts which are not electrically connected with the first pad part.
Description
Invention field
The invention relates to a kind of semiconductor-sealing-purpose substrate and semiconductor device, especially in regard to a kind of semiconductor-sealing-purpose substrate and semiconductor device of tool antistatic protection function.
Background technology
The demand of and consumption market integrated along with integrated circuit height, the size of semiconductor device also gradually trends towards compact, and has developed the encapsulation kenel that many types in semiconductor packaging.For example such as, present modal encapsulation kenel has pin grid array encapsulation (PGA), BGA Package (BGA), the encapsulation of wafer scale size etc.
In aforesaid encapsulation kenel, spherical grid array type semiconductor device 1 (as shown in Figure 1) can have more projection 13 because of the area that effectively utilizes base plate for packaging 11, so that via being located at the pad portion that electric trace (trace line) on the base plate for packaging 11 and pad portion (pad) are electrically connected to wafer 12, therefore, in spherical grid array type semiconductor device 1, wafer 12 can see through projection 13 and carry out a large amount of signal transmitting and receivings.
Please refer to base plate for packaging shown in Figure 2, above-mentioned 11 and comprise wiring layer 22 in one first wiring layer (wiring layer), 21, one ground connection, the interior wiring layer 23 of a power supply and one second wiring layer 24.They are to pile up in regular turn to form base plate for packaging 11, and wherein, the upper surface of first wiring layer 21 has a plurality of first pad portions (Pad) 211, and it is to electrically connect in order to the pad portion with wafer 12; In addition, be formed with a plurality of first electric traces 212 in first wiring layer 21, the one end is to be connected with respectively to each first pad portion 211.
In the ground connection in wiring layer 22 and the power supply wiring layer 23 are the specific pad portions (being the voltage source ring) that electrically connect the specific pad portion (being ground loop) that is positioned at first wiring layer 21 and second wiring layer 24 respectively so that provide earthing potential and voltage source current potential to wafer 12 from external circuit.
The lower surface of second wiring layer 24 has a plurality of second pad portions 241, is formed with a projection 13 on it respectively; In addition, form a plurality of second electric traces 242 in second wiring layer 24, the one end is connected to each second pad portion 241 respectively.In addition, the other end of each first electric trace 212 sees through the other end electric connection of a via hole (via hole) (not shown) and each second electric trace 242 respectively.Therefore, each pad portion of wafer 12 sees through the first pad portion 211, first electric trace 212, via hole, second electric trace 242, the second pad portion 241 and projection 13, carries out signal transmitting and receiving with external circuit.
From the above, because 11 of base plate for packaging can offer the quantity that the quantity of the second pad portion 241 that projection 13 connects surpasses the pad portion of wafer 12 usually, so the projection 13 of part does not electrically connect with the pad portion of wafer 12, these projections 13 also are called NC Ball; In more detail, the second pad portion that is connected with NC Ball is not connected with second electric trace usually, so NC Ball just can not electrically connect with the pad portion of wafer 12.Reserve these NC Ball and mainly be for the time, required output/input terminal can be provided in response to the functional promotion of semiconductor device (the spherical grid array type semiconductor device 1 as the aforementioned).Yet, when aforesaid spherical grid array type semiconductor device 1 is operated, these NC Ball can be in (floating) state of floating, at this moment, if carry out Electrostatic Discharge when test at this NC Ball, then static may flow to around this NC Ball projection, then, static may one the tunnel flow in the wafer, and the result can cause that other function pin (functionalpin) by electrostatic breakdown, cause the malfunction of spherical grid array type semiconductor device 1.
Therefore, how to provide a kind of semiconductor-sealing-purpose substrate and semiconductor device that can promote the anti-static-discharge capability of NC Bail, just one of important topic of current semiconductor packaging.
Summary of the invention
At the problems referred to above, the purpose of this invention is to provide a kind of semiconductor-sealing-purpose substrate and semiconductor device that can promote anti-static-discharge capability.
The invention provides a kind of semiconductor-sealing-purpose substrate, it comprises:
One first wiring layer (wiring layer), its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface have a plurality of second pad portions, and these a plurality of second pad portions arrange in array (array) mode; And
Wiring layer in one, its between the upper surface of the lower surface of this first wiring layer and this second wiring layer, one of described at least a plurality of second pad portions be electrically connected in this wiring layer and not with the electric connection of described a plurality of first pad portions.
Described semiconductor-sealing-purpose substrate, it also comprises:
A plurality of insulating barriers, its be lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
The invention provides a kind of semiconductor device, it comprises:
One substrate, it has:
One first wiring layer, its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface have a plurality of second pad portions, and
Wiring layer in one, it is between the upper surface of the lower surface of this first wiring layer and this second wiring layer, one of described at least a plurality of second pad portions be electrically connected in this wiring layer and not with the electric connection of described a plurality of first pad portions: and
One wafer, it is to be arranged on this first wiring layer of this substrate, and the pad portion of this wafer electrically connects with described a plurality of first pad portions.
Described semiconductor device, wherein said a plurality of second pad portions arrange with array way, and these a plurality of second pad portions are provided with plurality of bump.
Described semiconductor device, wherein this wafer is to be arranged on this substrate to cover crystalline substance (flip-chip) mode.
Described semiconductor device, wherein this wafer is to engage (wire bonding) mode with routing to be arranged on this substrate, this semiconductor device also comprises:
A plurality of conductor wires, it is pad portion and the described a plurality of first pad portion that engages this wafer; And
One adhesive body, it is to coat this wafer and described a plurality of conductor wires.
Described semiconductor device, wherein this substrate also comprises:
A plurality of insulating barriers, its lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
Another kind of semiconductor device, it comprises:
One substrate, it has
One first wiring layer, its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface has a plurality of second pad portions and at least one shielding portion, at least one of these a plurality of second pad portions electrically connect with these a plurality of first pad portions, and this shielding portion is to be positioned at not around this second pad portion that electrically connects with these a plurality of first pad portions, and
Wiring layer in one, it is between the upper surface of the lower surface of this first wiring layer and this second wiring layer, and this shielding portion is to be electrically connected to this interior wiring layer; And
One wafer, it is arranged on this first wiring layer of this substrate, and the pad portion of this wafer electrically connects with these a plurality of first pad portions.
Described another kind of semiconductor device, wherein these a plurality of second pad portions arrange with array way, and these a plurality of second pad portions are provided with plurality of bump.
Described another kind of semiconductor device, wherein this wafer is to be arranged on this substrate with the routing juncture, this semiconductor device also comprises:
A plurality of conductor wires, it is the pad portion and these a plurality of first pad portions that engages this wafer: and
One adhesive body, it is to coat this wafer and this a plurality of conductor wires.
Described another kind of semiconductor device, wherein this substrate also comprises:
A plurality of insulating barriers, its be lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
As previously mentioned, because the current potential of wiring layer is to the second pad portion that does not electrically connect with the first pad portion in providing according to semiconductor-sealing-purpose substrate of the present invention and semiconductor device, or in providing the earthing potential of wiring layer or voltage source current potential to shielding portion so that cover not the second pad portion that electrically connects with the first pad portion, therefore the second pad portion that does not electrically connect with the first pad portion is in order to be connected the second pad portion of aforesaid NC Ball, so can improve the anti-static-discharge capability of semiconductor device effectively.
Description of drawings
Fig. 1 is a spherical grid array type semiconductor schematic representation of apparatus in the prior art;
Fig. 2 is the exploded view of the base plate for packaging in the spherical grid array type semiconductor device in the prior art;
Fig. 3 is the schematic diagram of the semiconductor-sealing-purpose substrate of preferred embodiment of the present invention;
Fig. 4 is the schematic diagram of the semiconductor device of preferred embodiment of the present invention, and it has semiconductor-sealing-purpose substrate as shown in Figure 3;
Fig. 5 is the schematic diagram of the semiconductor device of another preferred embodiment of the present invention, and it has semiconductor-sealing-purpose substrate as shown in Figure 3;
Fig. 6 is the schematic diagram of the semiconductor-sealing-purpose substrate of another preferred embodiment of the present invention;
Fig. 7 A-7C is the schematic diagram of the form of demonstration shielding portion of the present invention;
Fig. 8 A is the schematic diagram of the semiconductor device of another preferred embodiment of the present invention, and it has semiconductor-sealing-purpose substrate as shown in Figure 6;
Fig. 8 B is the schematic diagram of the semiconductor device of the another preferred embodiment of the present invention, and it has semiconductor-sealing-purpose substrate as shown in Figure 6.
The figure number explanation
1 semiconductor device
11 base plate for packaging
12 wafers
13 projections
21 first wiring layers
211 first pad portions
212 first electric traces
Wiring layer in 22 ground connection
Wiring layer in 23 power supplys
24 second wiring layers
241 second pad portions
242 second electric traces
3 semiconductor-sealing-purpose substrates
31 first wiring layers
311 first pad portions
312 first electric traces
32 second wiring layers
321 second pad portions
322 second electric traces
Wiring layer in 33
34 via holes
34 ' via hole
4 semiconductor devices
42 wafers
43 projections
44 conductor wires
45 adhesive bodies
5 semiconductor devices
6 semiconductor-sealing-purpose substrates
61 first wiring layers
611 first pad portions
612 first electric traces
62 second wiring layers
621 second pad portions
622 second electric traces
623 shielding portions
Wiring layer in 63
64 via holes
64 ' via hole
7 semiconductor devices
72 wafers
8 semiconductor devices
Embodiment
Below with reference to Figure of description the semiconductor-sealing-purpose substrate and the semiconductor device of preferred embodiment of the present invention are described, wherein components identical will be illustrated with identical reference marks.
Please refer to shown in Figure 3ly, it is the semiconductor-sealing-purpose substrate 3 of preferred embodiment of the present invention, comprises wiring layer 33 in one first wiring layer 31, one second wiring layer 32 and.
The upper surface of first wiring layer 31 has a plurality of first pad portions 311, and it is to electrically connect (not shown) in order to the pad portion with a wafer; In addition, also be formed with a plurality of first electric traces 312 in first wiring layer 31.One end of each first electric trace 312 is to be connected with respectively to each first pad portion 311, and its other end is to be connected to a via hole 34 respectively.
The lower surface of second wiring layer 32 has a plurality of second pad portions 321, and is in order to form projection in the second pad portion 321; In addition, be formed with a plurality of second electric traces 322 in second wiring layer 32, the one end is to be connected to each second pad portion 321 respectively, and its other end is to see through above-mentioned via hole 34 respectively to electrically connect with the other end of each first electric trace 312 respectively.In the present embodiment, at least one second pad portion 321 does not electrically connect with arbitrary first pad portion 311; In addition, these second pad portions 321 arrange in array (array) mode, and semiconductor-sealing-purpose substrate 3 is to be a spherical grid array type (BGA) substrate.
Interior wiring layer 33 is to be positioned between the upper surface of the lower surface of first wiring layer 31 and second wiring layer 32.In the present embodiment, the second pad portion 321 that does not electrically connect with arbitrary first pad portion 311 be see through via hole 34 ' be electrically connected in wiring layer 33.At this moment, interior wiring layer 33 can be to be electrically connected to an earth terminal, so that provide earthing potential to the second pad portion 321; And interior wiring layer 33 can also be to be electrically connected to a voltage source, so that provide the voltage source current potential to the second pad portion 321.Allly be familiar with this operator and should understand, can have in the semiconductor-sealing-purpose substrate 3 more than one in wiring layer, for example, it can have an interior wiring layer that is electrically connected to voltage source simultaneously, and an interior wiring layer that is electrically connected to earth terminal.
Here note; in order to ensure the electrical independence between each wiring layer; so; between each wiring layer, can be provided with a layer insulating usually; and only have via hole 34,34 ' to pass each insulating barrier; so that electrically connect the first above-mentioned electric trace 312 and second electric trace 322, and the second pad portion 321 and interior wiring layer 33 that is not electrically connected to the first pad portion 311.
Please refer to shown in Figure 4ly, be made of above-mentioned semiconductor-sealing-purpose substrate 3 according to the semiconductor device 4 of preferred embodiment of the present invention, it comprises a semiconductor base plate for packaging 3 and a wafer 42.
In the present embodiment, semiconductor-sealing-purpose substrate 3 repeats no more as previously mentioned; In addition, semiconductor-sealing-purpose substrate 3 is arranged with plurality of bump 43, and it is connected with respectively in each second pad portion 321.Wafer 42 is sticking placing on first wiring layer 31 of semiconductor-sealing-purpose substrate 3, and the pad portion of wafer 42 electrically connects with these first pad portions 311.
Note that in the present embodiment, wafer 42 is to be arranged on the semiconductor-sealing-purpose substrate 3 to cover crystalline substance (flip-chip) mode, promptly the pad portion of wafer 42 sees through plurality of bump and 311 electric connections of the first pad portion; In addition; wafer 42 can utilize routing to engage (wire bonding) mode and be arranged on the semiconductor-sealing-purpose substrate 3; as shown in Figure 5; drag in the semiconductor device 5 of example in another preferable reality of the present invention; the pad portion of wafer 42 sees through a plurality of conductor wires 44 and 311 electric connections of the first pad portion; and in order to protect wafer 42 and conductor wire 44, so utilize an adhesive body 45 to come coating wafer 42 and conductor wire 44.
In addition, please refer to shown in Figure 6ly, the semiconductor-sealing-purpose substrate 6 of another preferred embodiment of the present invention comprises wiring layer 63 in one first wiring layer 61, one second wiring layer 62 and.
The upper surface of first wiring layer 61 has a plurality of first pad portion 611 and a plurality of first electric traces 612, the first pad portion 611 electrically connects (not shown) in order to the pad portion with a wafer, and an end of each first electric trace 612 is to be connected with respectively to each first pad portion 611, and its other end is to be connected to a via hole 64 respectively.
The lower surface of second wiring layer 62 has a plurality of second pad portions 621, a plurality of second electric traces 622 and at least one shielding portion 623; In the present embodiment, be in order to forming projection in the second pad portion 621, an end of second electric trace 622 is connected to each second pad portion 621 respectively, and its another to divide end be to see through via hole 64 respectively to kick electric connection with another of each first electric trace 612 respectively.In the present embodiment, at least one second pad portion 621 electrically connects with arbitrary first pad portion 611, and shielding portion 623 be positioned at not the second pad portion 621 that electrically connects with the first pad portion 611 around.In addition, these second pad portions 621 arrange with array way, and semiconductor-sealing-purpose substrate 6 is a spherical grid array type substrate at this moment; In addition, around the second pad portion 621 that shielding portion 623 can utilize arbitrary form to be arranged at not to electrically connect with the first pad portion 611, for example, the form of shielding portion 623 is shown in Fig. 7 A-7C.
Interior wiring layer 63 is positioned at the lower surface of first wiring layer 61 and the upper surface of second wiring layer 62.In the present embodiment, shielding portion 623 sees through via hole 64 ' and is electrically connected to interior wiring layer 63.At this moment, interior wiring layer 63 can be to be electrically connected to an earth terminal, so that provide earthing potential to shielding portion 623; And interior wiring layer 63 can be electrically connected to a voltage source, so that provide the voltage source current potential to shielding portion 623.Allly be familiar with this operator and should understand, can have in the semiconductor-sealing-purpose substrate 6 more than one in wiring layer, for example, it can have an interior wiring layer that is electrically connected to voltage source simultaneously, and an interior wiring layer that is electrically connected to earth terminal.
Note, in order to ensure the electrical independence between each wiring layer, so, between each wiring layer, can be provided with foregoing insulating barrier usually, so no longer set forth.
Please refer to Fig. 8 A and 8B, in the semiconductor device 7,8 of another preferred embodiment of the present invention, wafer 72 is carried by above-mentioned semiconductor-sealing-purpose substrate 6, and in semiconductor device 7, wafer 72 is to cover crystal type setting, in semiconductor device 8, wafer 72 is provided with the routing juncture.
In sum, because the earthing potential of wiring layer or voltage source current potential were to the second pad portion that does not electrically connect with the first pad portion in the semiconductor-sealing-purpose substrate of preferred embodiment of the present invention and semiconductor device provided, or in providing the earthing potential of wiring layer or voltage source current potential to shielding portion so that cover not the second pad portion that electrically connects with the first pad portion, oneself does not flow to the second contiguous pad portion with the second pad portion that the first pad portion electrically connects so can avoid static, and then can improve the anti-static-discharge capability of semiconductor device effectively.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (11)
1, a kind of semiconductor-sealing-purpose substrate is characterized in that comprising:
One first wiring layer, its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface have a plurality of second pad portions, and these a plurality of second pad portions arrange with array way; And
Wiring layer in one, its between the upper surface of the lower surface of this first wiring layer and this second wiring layer, one of described at least a plurality of second pad portions be electrically connected in this wiring layer and not with the electric connection of described a plurality of first pad portions.
2, semiconductor-sealing-purpose substrate as claimed in claim 1 is characterized in that also comprising:
A plurality of insulating barriers, its lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
3, a kind of semiconductor device is characterized in that comprising:
One substrate, it has:
One first wiring layer, its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface have a plurality of second pad portions, and
Wiring layer in one, its between the upper surface of the lower surface of this first wiring layer and this second wiring layer, one of described at least a plurality of second pad portions be electrically connected in this wiring layer and not with the electric connection of described a plurality of first pad portions: and
One wafer, it is arranged on this first wiring layer of this substrate, and the pad portion of this wafer electrically connects with described a plurality of first pad portions.
4, semiconductor device as claimed in claim 3 is characterized in that: wherein said a plurality of second pad portions arrange with array way, and these a plurality of second pad portions are provided with plurality of bump.
5, semiconductor device as claimed in claim 3 is characterized in that: wherein this wafer is to be arranged on this substrate to cover crystal type.
6, semiconductor device as claimed in claim 3 is characterized in that this wafer is to be arranged on this substrate with the routing juncture, and this semiconductor device also comprises:
A plurality of conductor wires, it engages pad portion and described a plurality of first pad portion of this wafer; And
One adhesive body, it is to coat this wafer and described a plurality of conductor wires.
7, semiconductor device as claimed in claim 3 is characterized in that this substrate also comprises:
A plurality of insulating barriers, its lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
8, a kind of semiconductor device is characterized in that comprising:
One substrate, it has
One first wiring layer, its upper surface have a plurality of first pad portions,
One second wiring layer, its lower surface has a plurality of second pad portions and at least one shielding portion, at least one of these a plurality of second pad portions electrically connect with these a plurality of first pad portions, and this shielding portion is to be positioned at not around this second pad portion that electrically connects with these a plurality of first pad portions, and
Wiring layer in one, it is between the upper surface of the lower surface of this first wiring layer and this second wiring layer, and this shielding portion is to be electrically connected to this interior wiring layer; And
One wafer, it is arranged on this first wiring layer of this substrate, and the pad portion of this wafer electrically connects with these a plurality of first pad portions.
9, semiconductor device as claimed in claim 8 is characterized in that: these a plurality of second pad portions arrange with array way, and these a plurality of second pad portions are provided with plurality of bump.
10, semiconductor device as claimed in claim 8 is characterized in that this wafer is to be arranged on this substrate with the routing juncture, and this semiconductor device also comprises:
A plurality of conductor wires, it engages the pad portion and these a plurality of first pad portions of this wafer: and
One adhesive body, it coats this wafer and this a plurality of conductor wires.
11, semiconductor device as claimed in claim 8 is characterized in that this substrate also comprises:
A plurality of insulating barriers, its lay respectively at this first wiring layer and should between the wiring layer, and this second wiring layer with this between the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02149326XA CN1295781C (en) | 2002-11-07 | 2002-11-07 | Base plate for encapsulating semiconductor and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB02149326XA CN1295781C (en) | 2002-11-07 | 2002-11-07 | Base plate for encapsulating semiconductor and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1499614A CN1499614A (en) | 2004-05-26 |
| CN1295781C true CN1295781C (en) | 2007-01-17 |
Family
ID=34233599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB02149326XA Expired - Fee Related CN1295781C (en) | 2002-11-07 | 2002-11-07 | Base plate for encapsulating semiconductor and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1295781C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433322C (en) * | 2006-12-25 | 2008-11-12 | 南通大学 | The encapsulation of integrated circuit chip without lead |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1182345A (en) * | 1996-06-19 | 1998-05-20 | 揖斐电株式会社 | Multilayer printed circuit board |
| US5990547A (en) * | 1998-03-02 | 1999-11-23 | Motorola, Inc. | Semiconductor device having plated contacts and method thereof |
| JP2002299512A (en) * | 2001-03-30 | 2002-10-11 | Nec Corp | Semiconductor device and manufacturing method thereof |
-
2002
- 2002-11-07 CN CNB02149326XA patent/CN1295781C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1182345A (en) * | 1996-06-19 | 1998-05-20 | 揖斐电株式会社 | Multilayer printed circuit board |
| US5990547A (en) * | 1998-03-02 | 1999-11-23 | Motorola, Inc. | Semiconductor device having plated contacts and method thereof |
| JP2002299512A (en) * | 2001-03-30 | 2002-10-11 | Nec Corp | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1499614A (en) | 2004-05-26 |
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Granted publication date: 20070117 Termination date: 20091207 |