CN1295431A - Laminating method and product of 8-layer printed circuit board - Google Patents

Laminating method and product of 8-layer printed circuit board Download PDF

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Publication number
CN1295431A
CN1295431A CN 99123697 CN99123697A CN1295431A CN 1295431 A CN1295431 A CN 1295431A CN 99123697 CN99123697 CN 99123697 CN 99123697 A CN99123697 A CN 99123697A CN 1295431 A CN1295431 A CN 1295431A
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layer
circuit board
insulating barrier
thickness
printed circuit
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CN1151707C (en
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郑裕强
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Mitac International Corp
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Mitac International Corp
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Abstract

In the eight-printed circuit board, the Nos.1,3,6,8 layers are signal line layers, the Nos 2,4,7 layers are ground layers, and the No.5 layer in power supply layer, there is a first pressed 2-6 mil thick insulating layer between the 4th and the 5th layers; one second pressed 7-15 mil thick insulating layer between 3rd and the 4th layers and between 5th and the 6th layers separately; one third pressed 7-13 mil thick insulating layer between the 2nd and the 3rd layers and between the 6th and the 7th layers separately; and one forth pressed 3.5-7.5 mil thick insulating layer between 1 st and the 2nd layers and betweent he 7th and the 8th layers separately. The printed circuit board is made to impedance matched between layers to reduce reflection and electromagnetic interference of high speed signal.

Description

The compression method of 8-layer printed circuit board and finished product thereof
The present invention relates to a kind of compression method and finished product thereof of circuit board, particularly relate to and a kind ofly can reach the impedance matching of circuit board ectonexine, with the compression method and the finished product thereof of the 8-layer printed circuit board that reduces high speed signal reflection and electromagnetic interference.
As shown in Figure 1, this is each layer arrangement mode of prior art 8-layer printed circuit board 1, wherein this circuit board 1 from top to bottom first, three, six and eight laminates are respectively signal lead layer S1, S2, S3 and S4, second, four and seven laminates are respectively ground plane GND, and the layer 5 plate is bus plane PWR, this first laminate S1 and the 8th laminate S4 are that part is laid layer, one thickness is arranged is first insulating barrier 2 of 8mil in pressing in the middle of the 4th laminate GND and layer 5 plate PWR, it is second insulating barrier 3 of 5mil (1mil=0.00254cm) that the middle pressing respectively of the 4th laminate GND and three ply board S2 and layer 5 plate PWR and layer 6 plate S3 has a thickness, it is the 3rd insulating barrier 4 of 8mil that the middle pressing respectively of this three ply board S2 and the second laminate GND and layer 6 plate S3 and layer 7 plate GND has a thickness, and it is the 4th insulating barrier 5 of 9.5mil that the middle pressing respectively of this second laminate GND and the first laminate S1 and layer 7 plate and the 8th laminate has a thickness, and, this first insulating barrier 2 and the 3rd insulating barrier 4 are a mylar (prepreg), this second insulating barrier 3 and the 4th insulating barrier 5 are a base material (core), and can obtain this first laminate S1 to resistance value Rs1=the 8th laminate S4 of the second laminate GND 76.4 ohm of resistance value Rs4 (Ω) to layer 7 plate GND in the pressing mode between aforesaid each laminate, this three ply board S2 is to the resistance value Rs2=layer 6 plate S3 of the second laminate GND and the 4th laminate GND, 51 ohm of the resistance value Rs3 (Ω) to layer 5 plate PWR and layer 7 plate GND.We are as can be seen thus, the resistance value Rs1 of this first laminate S1 (lamina rara externa) and the 8th laminate S4 (lamina rara externa) and Rs4 have differed 25.4 ohm (Ω) with resistance value Rs2 and the Rs3 of this three ply board S2 (inner plating) and layer 6 plate S3 (inner plating) respectively, and the anti-obvious gap of this ectonexine plate resistance can cause impedance not match, so that when a high speed signal transmits in this circuit board, when this high speed signal from skin, when just part laying layer (as the first laminate S1 or the 8th a laminate S4) is worn layer cabling to internal layer (as three ply board S2 or layer 6 plate S3), can cause this high speed signal not cause signal reflex because of anti-the matching of ectonexine plate resistance of passing through, cause the transmission quality of high speed signal bad, here our reflection coefficient that can calculate this high speed signal is: ρ = Zl - Zo Zl + Zo = RS 1 - Rs 2 Rs 1 + Rs 2 = 0 . 199
And because this high speed signal can produce standing wave in reflection process, and the standing wave that continues to produce can strengthen the electromagenetic wave radiation of this high speed signal, and makes its magnetic flux negative function variation, causes Electromagnetic Interference.
In addition, the sort circuit plate is when walking the high speed signal, the resistance value design of its transmission line, the resistance value in the middle of laminate and the laminate just, should be best about 55 Ω ± 10% according to the specification theoretical value that Intel (Intel) sets, just near 49.5 Ω ~ 60.5 Ω, but the lamina rara externa of calculating by the circuit board of prior art, resistance value Rs1 (or Rs4)=76.4 Ω of this first laminate S1 and the 8th laminate S4 just, it is a lot of to have exceeded this scope, even so its inner plating, just resistance value Rs2 (or Rs3)=51 Ω of this three ply board S2 and layer 6 plate S3 is in this scope, can not match yet and cause the reflection of high speed signal because of the impedance of inside and outside laminate, so the firm and hard high speed signal that is unsuitable for away of this circuit.
The object of the present invention is to provide a kind of inside and outside laminate of circuit board that makes to reach impedance matching, thereby reduce the compression method and the finished product thereof of the 8-layer printed circuit board of high speed signal reflection and Electromagnetic Interference.
The object of the present invention is achieved like this:
A kind of compression method of 8-layer printed circuit board, this circuit board from top to bottom are provided with eight layers of metal level in regular turn, and this first and third, six and eight layer is the signal lead layer, and second, four and seven layer is ground plane, and layer 5 is a bus plane, are characterized in that this method comprises the following steps:
A. at first the 4th layer of this circuit board with layer 5 in the middle of pressing one first insulating barrier is arranged, and the thickness of this first insulating barrier is in 4 ± 2mil scope;
B. a. step that continues, the 4th layer of this circuit board with the 3rd layer of centre and layer 5 and layer 6 in the middle of distinguish pressing one second insulating barrier, and the thickness of this second insulating barrier is in 11 ± 4mil scope;
C. the b. step that continues, the 3rd layer of this circuit board with the second layer in the middle of and difference pressing 1 the 3rd insulating barrier in the middle of layer 6 and the layer 7, and the thickness of the 3rd insulating barrier is in 10 ± 3mil scope;
D. the c. step that continues, in the middle of the second layer of this circuit board and the ground floor and layer 7 distinguish pressing 1 the 4th insulating barrier in the middle of with the 8th layer, and the thickness of the 4th insulating barrier is in 5.5 ± 2mil scope.
A kind of 8-layer printed circuit board made from said method, first of this circuit board, three, six and eight layers is the signal lead layer, second, four and seven layers is ground plane, layer 5 is a bus plane, and the 4th layer of this circuit board is provided with one first insulating barrier with the layer 5 therebetween, the 4th layer of this circuit board is folded with one second insulating barrier with the 3rd layer of centre and layer 5 respectively with the layer 6 centre, the 3rd layer and second layer centre and layer 6 and middle one the 3rd insulating barrier that is folded with respectively of layer 7 of this circuit board, the second layer of this circuit board and ground floor centre and layer 7 and the 8th layer of centre are folded with one the 4th insulating barrier respectively, are characterized in:
Described first thickness of insulating layer is in 4 ± 2mil scope; This second thickness of insulating layer is in 11 ± 4mil scope; The 3rd thickness of insulating layer is in 10 ± 3mil scope; The 4th thickness of insulating layer is in 5.5 ± 2mil scope.
The present invention makes it compared with prior art have tangible advantage and good effect owing to adopted above-mentioned technical scheme.The compression method of 8-layer printed circuit board of the present invention and finished product thereof are owing to the thickness with first insulating barrier is arranged in 4 ± 2mil scope, the thickness of second insulating barrier is arranged in 11 ± 4mil scope, the thickness that the thickness of the 3rd insulating barrier is arranged on 10 ± 3mil and falls the 4th insulating barrier is arranged in 5.5 ± 2mil scope, thus, make the inside and outside laminate of this circuit board can reach impedance matching, thereby reduce the signal reflection of high speed signal and the effect of Electromagnetic Interference.
By following to 8-layer printed circuit board of the present invention compression method and an embodiment of finished product in conjunction with the description of its accompanying drawing, cross over and further understand purpose of the present invention, specific structural features and advantage, wherein, accompanying drawing is:
Fig. 1 is pressing and the thickness of insulating layer schematic diagram between each laminate of prior art 8-layer printed circuit board;
Fig. 2 is according to pressing and the thickness of insulating layer schematic diagram between each laminate in the compression method of the 8-layer printed circuit board of the present invention's proposition and the finished product thereof;
Fig. 3 is the compression method of 8-layer printed circuit board of the present invention and the fragmentary cross-sectional view of finished product thereof.
The compression method of 8-layer printed circuit board of the present invention and finished product thereof can be suitable for for the 8-layer printed circuit board of thickness of slab in 1.1mm ~ 2.1mm scope, and following embodiment, are to be that the 8-layer printed circuit board of 1.6mm is an example with a thickness of slab.
As shown in Figure 2, in the present embodiment, its thickness of slab is the 8-layer printed circuit board 6 of 1.6mm, this circuit board 6 is from top to bottom arranged, order is: first, three, six and eight laminates are signal lead layer S1, S2, S3, S4, second, four and seven laminates are to be ground plane GND, and the layer 5 plate is bus plane PWR, and, first laminate S1 of this circuit board 6 and the 8th laminate S4 are that part is laid layer, in addition, be provided with one first insulating barrier 61 at the 4th laminate GND and layer 5 plate PWR therebetween, in the middle of the 4th laminate GND and three ply board S2 and layer 5 plate PWR and layer 6 plate S3, be folded with one second insulating barrier 63 respectively, in the middle of this three ply board S2 and the second laminate GND and layer 6 plate S3 and layer 7 plate GND, be folded with one the 3rd insulating barrier 65 respectively, and in the middle of this second laminate GND and the first laminate S1 and layer 7 plate GND and the 8th laminate S4, be folded with one the 4th insulating barrier 67 respectively, and, this first insulating barrier 61 and the 3rd insulating barrier 65 are a mylar (prepreg), and this second insulating barrier 63 and the 4th insulating barrier 67 are a base material (core).
Resistance value in the middle of general circuit flaggy plate and the laminate, normally the specification theoretical value of setting according to Intel (Intel) designs, and design is to walk the circuit board of high speed signal, resistance value specification in the middle of its laminate and the laminate should design about 55 ± 10% Ω, just can meet the designing requirement of high-speed line, and in order to improve the shortcoming of above-mentioned prior art 8-layer printed circuit board 1, impedance between the inside and outside laminate of circuit board 6 can be mated, can adjust the middle insulating barrier 61 of each laminate, 63,65 and 67 thickness changes the resistance value in the middle of laminate and the laminate, the resistance value of inside and outside laminate is equated, to reach the impedance matching between each laminate, so propose following computing formula:
Formula one (asking the computing formula of outer layer impedance Rs1 and Rs4): Rs 1 or Rs 4 = 87 E R + 1 . 41 ln { 5 . 98 H 0 . 8 W + T }
Wherein, E R=4.5, be dielectric constant;
Please cooperate referring to shown in Figure 3, wherein:
H is dielectric thickness, just the thickness of the 4th insulating barrier 67 in the middle of this first laminate S1 and the second laminate GND and layer 7 plate GND and the 8th laminate S4;
W=6mil, for trace width (in fact the W value from 2 ~ 8mil all can, but be best with 6mil);
T=1.4mil is cabling thickness.
Formula two (computing formula of layer impedance Rs2 and Rs3 in asking): Rs 2 or Rs 3 = 60 E R ln { 4 B 0 . 67 πW ( 0 . 8 + T W ) }
Wherein, E R=4.5, be dielectric constant;
Please cooperate again referring to shown in Figure 3, wherein:
B is total dielectric thickness, and just second insulating barrier 63 in the middle of this second laminate GND (ground plane) and the 4th laminate GND (ground plane) centre or layer 5 plate PWR (bus plane) and the layer 7 plate GND (ground plane) adds the thickness of the 3rd insulating barrier 65;
T=0.7mil is cabling thickness;
W=6mil, for trace width (in fact the W value from 2 ~ 8mil can, but be best with 6mil).
At first, the resistance value of Rs1 (or Rs4) and Rs2 (or Rs3) must drop on 55 ± 10% Ω, in the middle of 49.5 Ω ~ 60.5 Ω, just can meet to walk the designing requirement of high speed signal exactly, so can be earlier from formula one, Rs1 (or Rs4) is respectively with 49.5 Ω and 60.5 Ω substitutions, the value of trying to achieve H is in a scope, as 5.5mil ~ 6.0mil, as shown in Figure 2, we know that the thickness of slab of each laminate from top to bottom is respectively 1.4mil, 0.7mil, 0.7mil, 0.7mil, 0.7mil, 0.7mil, 0.7mil reach 1.4mil, the total thickness of slab that can try to achieve each laminate thus is 7mil; And because total thickness of slab of circuit board is 1.6mm=64mil, so can draw 2H+2B+D=64mil-7mil=57mil, 2B+D=57mil-2H, just 2B+D is in the middle of 46mil ~ 45mil, and in formula two, substitution one B value can calculate Rs2 (or Rs3), and the gap of comparison Rs1 (or Rs4) and both numerical value of Rs2 (or Rs3), and whether both all drop near 55 ± 10% Ω (49.5 Ω ~ 60.5 Ω), and adjust the numerical value of H and B respectively with this result relatively, calculate another Rs1 (or Rs4) and Rs2 (or Rs3) value in substitution formula one and the formula two respectively again, compare mutually again, adjust the thickness size of H and B, both are the most approaching and drop on value in the middle of 55 ± 10% Ω (49.5 Ω ~ 60.5 Ω) just to obtain Rs1 (or Rs4) and Rs2 (or Rs3), after H and B value are determined, just can try to achieve the value of D, so thickness (being D) of this first insulating barrier 61, second insulating barrier 63 (being H2) add the thickness (being B) of the 3rd insulating barrier 65 (being H3) and the 4th insulating barrier 69 thickness (being H) suitable thickness thereby determine, make the thickness of slab=1.6mm of 2H+2B+D+ (each laminate thickness and (7mil))=circuit board.
By by formula one, two computing and solution procedure, can find out optimum value for working as H=5.5mil, when B=22.4mil and D=4mil, Rs1 (or Rs4) 60 Ω, Rs2 (or Rs3) 60 Ω, all drop in the middle of 55 ± 10% Ω (49.5 Ω ~ 60.5 Ω), ectonexine resistance value gap can reach 0 Ω, reach the purpose of impedance matching fully, therefore when high speed signal transmits in this circuit board 6, when high speed signal from lamina rara externa, when just part laying layer (as the first laminate S1 or the 8th a laminate S4) is worn layer to inner plating (as three ply board S2 or layer 6 plate S3), because of the impedance of inside and outside laminate is mated fully,, can calculate its reflection coefficient at this and be so can effectively eliminate the signal reflex amount (being standing wave) of this high speed signal: ρ = Zl - Zo Zl + Zo = Rs 1 - Rs 2 Rs 1 + Rs 2 = 0
Compared to reflection coefficient ρ=0.199 of prior art circuits plate, improved the reflection of high speed signal significantly and fully, subdue Electromagnetic Interference naturally, improved the transmission quality of high speed signal.
In addition, when the layout of circuit board, though the cabling of holding wire is worn to different layers, but owing to controlled the pressing thickness of circuit board, make the ectonexine impedance reach impedance matching, the trace width that need not change holding wire just can reach the effect of impedance Control, has improved the ageing of layout.

Claims (8)

1. the compression method of a 8-layer printed circuit board, this circuit board from top to bottom is provided with eight layers of metal level in regular turn, and this first and third, six and eight layer is the signal lead layer, and second, four and seven layer is ground plane, layer 5 is a bus plane, it is characterized in that this method comprises the following steps:
A. at first the 4th layer of this circuit board with layer 5 in the middle of pressing one first insulating barrier is arranged, and the thickness of this first insulating barrier is in 4 ± 2mil scope;
B. a. step that continues, the 4th layer of this circuit board with the 3rd layer of centre and layer 5 and layer 6 in the middle of distinguish pressing one second insulating barrier, and the thickness of this second insulating barrier is in 11 ± 4mil scope;
C. the b. step that continues, the 3rd layer of this circuit board with the second layer in the middle of and difference pressing 1 the 3rd insulating barrier in the middle of layer 6 and the layer 7, and the thickness of the 3rd insulating barrier is in 10 ± 3mil scope;
D. the c. step that continues, in the middle of the second layer of this circuit board and the ground floor and layer 7 distinguish pressing 1 the 4th insulating barrier in the middle of with the 8th layer, and the thickness of the 4th insulating barrier is in 5.5 ± 2mil scope.
2. the compression method of 8-layer printed circuit board as claimed in claim 1 is characterized in that: described first insulating barrier and the 3rd insulating barrier are for a kind of insulation material, and described second insulating barrier and the 4th insulating barrier are with a kind of insulation material.
3. the compression method of 8-layer printed circuit board as claimed in claim 2, it is characterized in that: described first insulating barrier and the 3rd insulating barrier are mylar, this second insulating barrier and the 4th insulating barrier are base material.
4. the compression method of 8-layer printed circuit board as claimed in claim 3, it is characterized in that: the thickness of slab of described 8-layer printed circuit board is in 1.1mm ~ 2.1mm scope, and with eight layers of electroplax of thickness of slab 1.6mm, first thickness of insulating layer of the 8-layer printed circuit board of this thickness of slab 1.6mm is 4mil, this second thickness of insulating layer is 11mil, and the 3rd thickness of insulating layer is that 10mil and the 4th thickness of insulating layer are 5.5mil.
5. 8-layer printed circuit board made from the compression method of the described 8-layer printed circuit board of claim 1, first of this circuit board, three, six and eight layers is the signal lead layer, second, four and seven layers is ground plane, layer 5 is a bus plane, and the 4th layer of this circuit board is provided with one first insulating barrier with the layer 5 therebetween, the 4th layer of this circuit board is folded with one second insulating barrier with the 3rd layer of centre and layer 5 respectively with the layer 6 centre, the 3rd layer and second layer centre and layer 6 and middle one the 3rd insulating barrier that is folded with respectively of layer 7 of this circuit board, the second layer of this circuit board and ground floor centre and layer 7 and the 8th layer of centre are folded with one the 4th insulating barrier respectively, it is characterized in that:
Described first thickness of insulating layer is in 4 ± 2mil scope; This second thickness of insulating layer is in 11 ± 4mil scope; The 3rd thickness of insulating layer is in 10 ± 3mil scope; The 4th thickness of insulating layer is in 5.5 ± 2mil scope.
6. 8-layer printed circuit board as claimed in claim 5 is characterized in that: described first insulating barrier and the 3rd insulating barrier are that this second insulating barrier and the 4th insulating barrier are with a kind of insulating barrier with a kind of insulating barrier.
7. 8-layer printed circuit board as claimed in claim 6 is characterized in that: described first insulating barrier and the 3rd insulating barrier are mylar, and this second insulating barrier and the 4th insulating barrier are base material.
8. 8-layer printed circuit board as claimed in claim 7, it is characterized in that: the thickness of slab of described 8-layer printed circuit board is in 1.1mm ~ 2.1mm scope, and with the 8-layer printed circuit board of thickness of slab 1.6mm, first thickness of insulating layer of the 8-layer printed circuit board of this thickness of slab 1.6mm is 4mil, second thickness of insulating layer is 11mil, and the 3rd thickness of insulating layer is that 10mil and the 4th thickness of insulating layer are 5.5mil.
CNB991236971A 1999-11-04 1999-11-04 Laminating method and product of 8-layer printed circuit board Expired - Fee Related CN1151707C (en)

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Application Number Priority Date Filing Date Title
CNB991236971A CN1151707C (en) 1999-11-04 1999-11-04 Laminating method and product of 8-layer printed circuit board

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Application Number Priority Date Filing Date Title
CNB991236971A CN1151707C (en) 1999-11-04 1999-11-04 Laminating method and product of 8-layer printed circuit board

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CN1295431A true CN1295431A (en) 2001-05-16
CN1151707C CN1151707C (en) 2004-05-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106455295A (en) * 2016-10-14 2017-02-22 盛科网络(苏州)有限公司 PCB (printed circuit board)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106455295A (en) * 2016-10-14 2017-02-22 盛科网络(苏州)有限公司 PCB (printed circuit board)

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CN1151707C (en) 2004-05-26

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