CN1294349A - Storage module controller - Google Patents
Storage module controller Download PDFInfo
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- CN1294349A CN1294349A CN 99123371 CN99123371A CN1294349A CN 1294349 A CN1294349 A CN 1294349A CN 99123371 CN99123371 CN 99123371 CN 99123371 A CN99123371 A CN 99123371A CN 1294349 A CN1294349 A CN 1294349A
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Abstract
A memory module controller is composed of at least one multiplexer, one automatic detector and one terminal. Each memory slot in system sends a signal to automatic detector to judge the state of each slot and send and state signal as control signal to multiplexer. The slots output signals to inputs of multiplexer, whose output is connected to terminals, so forming a complete channel of data signals and clock pulse signals.
Description
The present invention relates to a kind of memory module device, particularly relate to a kind of control device of high-speed memory module.
Storer is the member that has extremely great status in computer system, and what be most widely used at present is a kind of dynamic RAM memory storage of (dynamic random access memory is called for short DRAM) that is called.In recent years, the DRAM technology presents theatrical development.The density of memory component by each chip (chip) capacity be kilobit (1K bits) to 64 megabits (64M bits), yet the usefulness of DRAM is not but improved as having significantly as its capacity.Especially very person, at present microprocessor (micro processor) usefulness speed fast, make that the usefulness between microprocessor and the storer is difficult to coupling.Therefore, many complexity and expensive storer control access system just are developed, in order to increase the usefulness of storer: as synchronous random access cache storer (synchrotron randomaccess memory caches, SRAM caches) and DRAM and column array few techniques such as (parallel arrays ofDRAMs).
For the Efficacy Problem that solves storer degree of difficulty with reductions technology, Rambus company develop a kind of storer chips to the bussing technique of chip (chip to chip) with and the control interface of correspondence, and define the specification of this kind memory module.This kind bus control technology is referred to as direct Rambus passage (direct Rambus channel), and it can be connected to memory chip as microprocessor, graphic process unit (graphics processor) and ASICs etc.This kind passage only carries all address, data and control signal with the high speed signal of minority.The memory module of using this kind specification and technology to derive out just is called Rambus dynamic RAM module (RambusDRAM module) or is called RIMM.
Shown in Figure 1A to Fig. 1 C, it illustrates the storer control interface of the direct Rambus passage of four-way, two passages and single passage respectively.Memory chip 10 is directly connected to control interface 16 on the Memory Controller 14 via direct Rambus passage 12.By accompanying drawing as can be known, all chipsets 10 in the memory module of this kind technology are connected in series by a passage 12.The message transmission rate of each bar passage is minimum to be the 1.6GB byte, so Figure 1A just is respectively 6.4GB byte, 3.2GB byte and 1.6GB byte to the message transmission rate of Fig. 1 C.Therefore, the RIMM memory module has high-effect and advantage cheaply.
Though the RIMM memory module has above-mentioned advantage, so it needs high system works frequency, and its frequency can make the RIMM memory module work normally up to 400MHz.Therefore, the terminal of memory module must have suitable terminal organ (terminator) can prevent the reflection of high-frequency signal.
With reference to Fig. 2 A, three RIMM memory module 20a, 20b and 20c are serially connected memory chip 22a, 22b and 22c between each module fully by passage 24 after inserting memory bank.Module 20a is connected to control interface 26a on the Memory Controller 26 by passage 24, and last module 20c is connected to terminal organ 28 and gate generator 29 with passage, so just constitutes a complete signal path between Memory Controller 26, memory module and terminal organ 28.Yet, if the slot of memory module does not stick with fully, shown in Fig. 2 B, when only plugging wherein one, just can't constitute a complete signal path between Memory Controller 26, memory module and the terminal organ 28.Technique known is that the slot of not plugging memory module is plugged two virtual RIMM modules (dummy RIMM module) 20b ' and 20c '.Virtual RIMM module 20b ' and the top not chip of storer of 20c ', it only provides signal path, make between Memory Controller 26, memory module 20a and terminal organ 28 and the gate generator 29 to constitute a complete signal path, in order to transmit address, data and the control signal of control store.
From the above, technique known is plugged alternative virtual memory module in order to solve the problem that signal integrity connects with the slot of not inserting memory module.The problem that takies memory bank so, is just arranged.In addition, if will increase the problem that memory module also has the dismounting inconvenience newly.In addition, utilize the virtual memory module can more increase cost.
Therefore purpose of the present invention just provides a kind of storage module controller, and it can use the simplest method to reach signal complete between memory module and terminal organ and the gate generator to be connected.
Another object of the present invention is providing a kind of storage module controller exactly, and which memory module slot it can detect on automatically slotting memory module, and automatically signal path between memory module and the terminal organ is coupled together.
For reaching above-mentioned purpose with other, the invention provides a kind of storage module controller, it is summarized as follows:
Device of the present invention is the behaviour in service that can be used for detecting a memory bank in the computer system, and memory module is connected to end device automatically, to constitute a complete signal transmission channel.This storage module controller comprises a traffic pilot, an automatic testing circuit and an end device at least.Each memory bank of system transmits a signal respectively and gives automatic testing circuit, and circuit is judged the user mode of each slot thus, and exports a status signal and give traffic pilot, as control signal.
Each memory bank also outputs signal to the input end of traffic pilot.The output terminal of traffic pilot then is connected to end device.Send the control signal of traffic pilot to by automatic testing circuit, traffic pilot can select one of them input end to be connected to the output terminal of traffic pilot.Therefore, last output signal that is inserted with the slot of memory module just can be connected on the end device automatically, constitutes a complete data-signal and the transmission channel of clock pulse signal.Plug virtual memory so needn't on the thronely be inserted with the slot of memory module.
Storage module controller of the present invention comprises: a storage control device; One first, 1 second and 1 the 3rd slot, have a signal input part and a signal output part respectively, this signal output part of this first slot is couple to this signal input part of this second slot, this signal output part of this second slot is couple to this signal input part of the 3rd slot, and this first, this second with the 3rd slot form a tandem junction structure, this signal input part of this first slot then is couple to this storage control device; One traffic pilot has one first, 1 second and 1 the 3rd input end and an output terminal, this first, this second with this output terminal of the 3rd slot also be couple to respectively this traffic pilot this first, this second with the 3rd input end; One end device is couple to this output terminal of this traffic pilot; An and automatic testing circuit, be couple to this first, this second with the 3rd slot, in order to detect user mode, to export a status signal to this traffic pilot, in order to select this first, this second with one of them of this signal output part of the 3rd slot so that output signal is sent to this end device.
Storage control device of the present invention is connected to last memory module automatically can reach end device once simple control circuit, constitutes complete signal transmission passage.Therefore, whole cost just thereby reduce makes its application product have more commercioganic Competition Characteristics.
Moreover, because do not need as known skill, use the virtual memory module, so any user dismounting memory module easily needn't be considered the connection of terminal organ.Terminal organ is should be connected to correct position by the automatic decision of system.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Figure 1A is respectively the synoptic diagram of storer control interface of the direct Rambus passage of four-way, two passages and single passage to Fig. 1 C;
Fig. 2 A is the connection diagram of signal path between Memory Controller, memory module and the terminal organ;
Fig. 2 B is that known technology replaces memory module to finish the connection diagram of signal path between Memory Controller, memory module and the terminal organ with the virtual memory module;
Fig. 3 is the preferred embodiment of storage module controller of the present invention:
Fig. 4 is another preferred embodiment of storage module controller of the present invention.
With reference to Fig. 3, it is the structure calcspar according to a kind of storage module controller of the present invention.
Storage control device is a kind of Signal Terminal device control device that is applicable to direct Rambus passage dynamic RAM (direct Rambus channel DRAM) specification or is called the RIMM specification.It can be applied in the general computer system.
As shown in Figure 3, be example with PENTIUM II rating calculation machine, its CPU has can control three groups of abilities as the RIMM memory module.The access control of storer is controlled by Memory Controller 30, Memory Controller 30 can transmit a plurality of signals about storer address, data, control signal and clock pulse signal, can select one of them memory chip in the access RIMM memory module to carry out access control whereby.Three groups of memory module are first, second and the 3rd slot 32a, 32b and the 32c that can insert respectively as shown in the figure.Slot 32a, 32b and 32c have signal input part A1～A3 and signal output part B1～B3 respectively.The signal output part B1 of the first slot 32a is couple to the signal input part A2 of the second slot 32b, and the signal output part B2 of the second slot 32b is couple to the signal input part A3 of the 3rd slot 32c.Above-mentioned first, second and the 3rd RIMM memory bank 32a, 32b and 32c just form a tandem junction structure (castcade), and the signal input part A1 of the first slot 32a then is couple to storage control device 30.
Connection between the above-mentioned signal end is to connect with a bus (bus), be to come as interface bus in the present invention, in order to transmit the majority signal of storer address, data, control signal and clock pulse signal with direct Rambus passage (direct Rambus channel).
Whether automatically the input end of testing circuit 38 can be received the earth terminal of the pin of each slot, be inserted among the slot in order to judge the RIMM memory module.
When a slot is only arranged, as slot 32a, when plugging storer, this moment testing circuit 38 can to measure slot 32b, 32c be that sky connects, so output status signal informs that the output signal of the output terminal of traffic pilot 34 selection slot 30a is connected to output terminal Y, therefore end device 36 just is connected to the memory module that first slot is inserted automatically, and constitutes complete signal path.In like manner can make, when slotting two storeies during to slot 32a and 32b, traffic pilot 34 just because of the effect of testing circuit 38 select input end X2 as with being connected of output terminal Y.When slot 32a, 32b and 32c stuck with the RIMM memory module entirely, input end X3 just was connected to output terminal Y.
From the above mentioned, storage module controller of the present invention can detect the user mode of slot automatically by simple circuit, so can automatically last group memory module be connected on the end device, and not need to be inserted on the untapped slot as the extra virtual memory module of known needs.Therefore can save the advantage that cost and storer change the outfit fast.That is, as long as after directly plugging memory module, system can judge automatically just end device should be connected to the signal output part on which slot.
Above-mentioned example is to be example with three memory banks, but practical application maybe can be used in the accumulator system with a plurality of slots.
At the device described in first embodiment, be easily for the user.Yet traffic pilot must switch many signals, as storer address, data, control signal and clock pulse signal etc., therefore, just that the circuit design of traffic pilot seems is very complicated.Moreover cost also can be higher.The control device structure that present embodiment proposed is the structure that can simplify multi-path converter circuit.Traffic pilot only is used to switch clock pulse signal, so its internal circuit just can greatly be simplified.Yet, need many specially designed virtual memory modules (dummy RIMM module).This virtual memory module comprises a terminal organ circuit and a time clock loop.
With reference to Fig. 4, it is another preferred embodiment of storage module controller of the present invention.
As shown in the figure, be example still with PENTIUM II rating calculation machine, its CPU has can control three groups of abilities as the RIMM memory module.The access control of storer is controlled by Memory Controller 40, Memory Controller 40 can transmit the majority signal about storer address, data, control signal and zz clock pulse signal, can select one of them memory chip in the access RIMM memory module to carry out access control whereby.Three groups of memory module are first, second and the 3rd slot 42a, 42b and the 42c that can insert respectively as shown in the figure.Slot 42a, 42b and 42c have signal input part A1～A3 and signal output part B1～B3 respectively.The signal output part B1 of the first slot 32a is couple to the signal input part A2 of the second slot 32b, and the signal output part B2 of the second slot 42b is couple to the signal input part A3 of the 3rd slot 42c.Above-mentioned first, second and the 3rd RIMM memory bank 42a, 42b and 42c just form a tandem junction structure (castcade), and the signal input part A1 of the first slot 42a then is couple to storage control device 40.
In addition, each slot also has clock pulse input terminal C1～C3 and output terminal of clock pulse D1～D3, and wherein the clock pulse input terminal C1 of slot 42a is couple to the clock pulse input terminal C2 that this Memory Controller 40 and output terminal of clock pulse D1 are couple to slot 42b.Traffic pilot 44 has first and second input end X1, X2 and an output terminal Y, and output terminal Y is couple to the output terminal of clock pulse D2 of the second slot 42b, and first input end X1 is couple to the clock pulse input terminal C3 of the 3rd slot 42c.First end device 46 is couple to the signal output part B3 of the 3rd slot 42c.Second end device 48 is couple to the output terminal of clock pulse D3 of the 3rd slot 42c and the second input end X2 of traffic pilot 44.
Automatically testing circuit 50 has first and second signal input part E, F and is couple to the second slot 42b and the 3rd slot 42c respectively, in order to detect the user mode of the second and the 3rd slot 42b, 42c, so as to exporting a status signal to traffic pilot 44.When status signal judged that a virtual memory module is inserted in the second slot 42b, traffic pilot 44 just selected the second input end X2 to be connected to output terminal Y; And when status signal judged that the virtual memory module is inserted in the 3rd slot 42c, traffic pilot 44 just selected first input end X1 to be connected to output terminal Y.Can finish the complete clock pulse signal path of memory module one thus.
From the above mentioned, storage module controller of the present invention is by simple circuit and cooperate the virtual memory module of a particular design, just can detect the user mode of slot automatically, so can be automatically the virtual memory module of last group be connected on the device of clock terminal.Traffic pilot only needs to do the selection of clock pulse signal, so its internal circuit design is also comparatively simple.Therefore can save cost.That is, as long as after directly plugging memory module, and in the end plug the virtual memory module of particular design, system can judge automatically just the clock terminal device should be connected to the clock arteries and veins clock signal output part on which slot.
Above-mentioned example is to be example with three memory banks, but practical application maybe can be used in the accumulator system with a plurality of slots.
Therefore, feature of the present invention is to utilize simple traffic pilot and automatic testing circuit, is judged end device and should be connected to which bar memory bank, and do not need untapped slot is stuck with the virtual memory module.
Another feature of the present invention is to utilize the virtual memory module of simple traffic pilot and an automatic testing circuit and a particular design, it can detect the user mode of slot automatically, and the clock pulse signal output of virtual memory module is connected on the device of clock terminal.
A feature more of the present invention is the simple and making easily of circuit, so can reduce cost.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention should be with being as the criterion that the claim scope is defined.
Claims (19)
1. storage module controller comprises:
One storage control device;
One first, 1 second and 1 the 3rd slot, have a signal input part and a signal output part respectively, this signal output part of this first slot is couple to this signal input part of this second slot, this signal output part of this second slot is couple to this signal input part of the 3rd slot, and this first, this second with the 3rd slot form a tandem junction structure, this signal input part of this first slot then is couple to this storage control device;
One traffic pilot has one first, 1 second and 1 the 3rd input end and an output terminal, this first, this second with the output terminal of the 3rd slot also be couple to respectively this traffic pilot this first, this second with should and the 3rd input end;
One end device is couple to this output terminal of this traffic pilot; And
One automatic testing circuit, be couple to this first, this second with the 3rd slot, in order to detect user mode, to export a status signal to this traffic pilot, in order to select this first, this second with one of them of this signal output part of the 3rd slot so that output signal is sent to this end device.
2. storage module controller as claimed in claim 1, wherein this end device also comprises a terminal organ and a time clock generator.
3. storage module controller as claimed in claim 2, wherein this gate generator produces the high-frequency signal that a frequency is 400MHz.
4. storage module controller as claimed in claim 1, wherein this first, this second with the 3rd slot between be connected in series, between the input end of this signal output part and this traffic pilot couple and this first slot and this Memory Controller between to couple be to finish with an interface bus.
5. storage module controller as claimed in claim 4, wherein this interface bus is the bus that satisfies direct Rambus passage specification.
6. storage module controller as claimed in claim 1, wherein said memory bank are as the memory module that satisfies direct Rambus storer specification.
7. storage module controller comprises:
One storage control device;
One first, one second and one the 3rd slot, this is first years old, this the second and the 3rd slot has a signal input part and signal output part respectively, and a time clock input end and a time clock output terminal, wherein the signal input part of this first slot is couple to this signal input part that this storage control device and this signal output part are couple to this second slot, this signal output part of this second slot then is couple to this signal input part of the 3rd slot, and this clock pulse input terminal of this first slot is couple to this clock pulse input terminal that this storage control device and this output terminal of clock pulse are couple to this second slot;
One traffic pilot has one first and one second input end and an output terminal, and this output terminal is couple to this output terminal of clock pulse of this second slot, and this first input end is couple to the clock pulse input terminal of the 3rd slot;
One first end device is couple to this signal output part of the 3rd slot;
One second end device is couple to the output terminal of clock pulse of the 3rd slot and second input unit of traffic pilot; And
One automatic testing circuit has one first and one secondary signal input end and is couple to this second slot and the 3rd slot respectively, in order to detect this second with the user mode of the 3rd slot, exporting a status signal to this traffic pilot,
When this status signal judges that a virtual memory module is inserted in this second slot, this traffic pilot just selects this second input end just to be connected to this output terminal, and when this status signal judged that a virtual memory module is inserted in the 3rd slot, this traffic pilot just selected this first input end to be connected to this output terminal.
8. storage module controller as claimed in claim 7, wherein this second end device also comprises a time clock terminal organ and a time clock generator.
9. storage module controller as claimed in claim 8, wherein this gate generator produces the high-frequency signal that a frequency is 400MHz.
10. storage module controller as claimed in claim 7, wherein this first end device is a data bus terminal device.
11. storage module controller as claimed in claim 7, wherein this first, this second with being connected in series of the 3rd slot, and coupling between this first slot and this Memory Controller is to finish with an interface bus.
12. storage module controller as claimed in claim 11, wherein this interface bus is the bus that satisfies direct Rambus passage specification.
13. storage module controller as claimed in claim 7, wherein this virtual memory module comprises a terminal organ circuit and a time clock loop.
14. a storage module controller comprises:
One storage control device;
A plurality of slots, each described slot has a signal input part and a signal output part, this signal output part of this slot of previous stage is couple to this signal input part of this slot of back one-level, described slot forms a tandem junction structure, and this signal input part of first slot in the described slot then is couple to this storage control device;
One traffic pilot has a plurality of input ends and an output terminal, and this output terminal of each described slot also is couple to each described input end of this traffic pilot respectively;
One end device is couple to this output terminal of this traffic pilot; And
One automatic testing circuit, be couple to each described slot, in order to detect the user mode of each described slot, to export a status signal to this traffic pilot, in order to select one of them of described input end institute input signal, make one of them output signal of described slot be sent to this end device.
15. storage module controller as claimed in claim 14, wherein this end device also comprises a terminal organ and a time clock generator.
16. storage module controller as claimed in claim 15, wherein this gate generator produces the high-frequency signal that a frequency is 400MHz.
17. storage module controller as claimed in claim 14, between the described input end of the serial connection of wherein said slot, the signal output part of described slot and this traffic pilot couple and this first slot and this Memory Controller between to couple be to finish with an interface bus.
18. storage module controller as claimed in claim 17, wherein this interface bus is the bus that satisfies direct Rambus passage specification.
19. storage module controller as claimed in claim 14, wherein said memory bank are as the memory module that satisfies direct Rambus storer specification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991233719A CN100385412C (en) | 1999-10-26 | 1999-10-26 | Storage module controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991233719A CN100385412C (en) | 1999-10-26 | 1999-10-26 | Storage module controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1294349A true CN1294349A (en) | 2001-05-09 |
| CN100385412C CN100385412C (en) | 2008-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991233719A Expired - Lifetime CN100385412C (en) | 1999-10-26 | 1999-10-26 | Storage module controller |
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| CN (1) | CN100385412C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112020177A (en) * | 2019-05-28 | 2020-12-01 | 技嘉科技股份有限公司 | Illuminated memory device and memory module |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5963981A (en) * | 1995-10-06 | 1999-10-05 | Silicon Graphics, Inc. | System and method for uncached store buffering in a microprocessor |
| JPH10228421A (en) * | 1997-02-14 | 1998-08-25 | Nec Ic Microcomput Syst Ltd | Memory access control circuit |
-
1999
- 1999-10-26 CN CNB991233719A patent/CN100385412C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112020177A (en) * | 2019-05-28 | 2020-12-01 | 技嘉科技股份有限公司 | Illuminated memory device and memory module |
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| CN100385412C (en) | 2008-04-30 |
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Granted publication date: 20080430 |