CN1292484C

CN1292484C - Nonvolatile static ROM memories

Info

Publication number: CN1292484C
Application number: CN02127328.6A
Authority: CN
Inventors: 廖修汉; 杨鸿铭
Original assignee: Lianbang Science And Technology Co Ltd
Current assignee: Lianbang Science And Technology Co Ltd; Brilliance Semiconductor Inc
Priority date: 2002-07-31
Filing date: 2002-07-31
Publication date: 2006-12-27
Anticipated expiration: 2022-07-31
Also published as: CN1472816A

Abstract

The present invention relates to a nonvolatile static random access memory unit, which has a memory function after a power supply is off. The nonvolatile static random access memory unit comprises a static random access unit and a nonvolatile memory unit and has the random-access characteristic of a static random access memory, and simultaneously, after the power supply is off, data can also be stored in the nonvolatile memory unit, after the power supply is on, the data in the nonvolatile memory unit can be automatically restored to the static random access unit.

Description

Nonvolatile static ROM memories

Technical field

The invention relates to a kind of memory cell of static RAM, particularly a kind of memory cell of Nonvolatile static random access memory.

Background technology

In the digital system running, need often constantly to read and store digital data, therefore the memory element that has memory function can be divided into several classes: random access memory (Random Access Memory), serial access memory (Serial Access Memory), content access memory (Content Access Memory) for realizing the significant components of digital system.

And in semi-conductive memory, using one usually by the formed array of storage element (cell), each unit can store one data.Can be optionally when needs with deposit data in each storage element or from its taking-up, so sort memory be called again random access memory (RandomAccess Memory, RAM), be different from read-only memory (Read Only Memory, ROM).The major advantage of RAM is in the matrix that arbitrary access time is all identical, but its shortcoming is when power supply disappears, and all data all can be lost, and this situation is described to be volatibility (volatile), that is to say that power supply one turns off, the data that leave among the RAM have just disappeared.And the data that leave among the ROM can be preserved always, do not disappear because of power-off.So ROM is also referred to as nonvolatile memory (Nonvolatile Memory).

Therefore, can be divided into volatibility (volatile) and non-volatile (nonvolatile) memory two classes according to the storage characteristics of memory, just behind power-off, the storage data of nonvolatile memory still can continue to be saved its maximum difference.Volatile memory is representative with static RAM (SRAM) with dynamic random access memory (DRAM), but read-only memory (ROM) is arranged nonvolatile memory program read-only memory (PROM), EPROM (Erasable Programmable Read Only Memory) (EPROM), electronics EPROM (Erasable Programmable Read Only Memory) (EEPROM) and flash memory (flash), wherein ROM can only write data, can not revise, EPROM need could change data with ultraviolet ray; EEPROM then utilizes voltage to change data.

But it can't continue to keep the characteristic of data owing to random access memory, and prior art proposes a kind of Nonvolatile static random access memory then, and (Non-volatile SRAM is nvSRAM) to solve the inborn restriction of RAM, to expand the application of RAM.Because at some hand helds or portable digital product all is to be used as its power supply source by battery, in case when battery can't continued power or the situation that can't substitute immediately for charged source under, the data that are stored in the memory just can be lost immediately.In this case, using nvSRAM promptly is a kind of suitable technique solution, include two parts, one is sram cell, and one is the memory cell of tool non-volatile characteristic, and wherein the part of SRAM is when power supply is supplied, be used for temporary transient access data, non-volatile characteristic memory cell part is then in order to storage data when power supply disappears, and when the power supply supply recovers, data can be returned in the part of SRAM.

The key factor of this nvSRAM in research and development be must can be quick and complete before the power supply complete obiteration with data storing in the non-volatile characteristic memory cell, therefore prior art has the nvSRAM that proposes a kind of quick storage capacity, the Nonvolatile static random access memory with high speed storage capacity (Non-volatile Static Random AccessMemory with High Speed STORE Capability) that is provided as U.S. Patent number 6097329, it is to utilize a SRAM memory cell and a nv cell to form a nvSRAM, and the controller when utilizing a controller to be used as removing storage data, to reach the purpose of fast access.

Therefore proposed multiple solution for NVRAM in the prior art, the present invention reintroduces a kind of new-type Nonvolatile static ROM memories, and the transistor size that it used is less, and the speed of access is also than comparatively fast.

Summary of the invention

In sum, main purpose of the present invention is providing a kind of memory cell of nonvolatile RAM, utilize a sram storage element (SRAM cell) and an electric erasing type programmable read only memory memory cell (EEPROM cell), in conjunction with forming a new memory cell, make new memory cell can under information computing environment, have the characteristic of static random-access, before power supply disappears simultaneously, can will remain on data storing in the sram storage element to electric erasing type programmable read only memory memory cell, and when power up is supplied, data are returned back in the above-mentioned sram storage element, in order to avoid the data in sram storage element disappear because power supply disappears.

Because the memory chip that static 6T transistor cell is constituted involves minimum circuit design details and manufacturing process knowledge, therefore be fit to be used as the more uncomplicated digital system of data operation environment, for example memory in mobile phone or the hand held information processor.Another reason is extremely low with static RAM its consumed power when static of the making of CMOS technology, is fit to be applied in battery in support in the non-volatile type memorizer of power supply.

Another object of the present invention is to provide a kind of nonvolatile RAM memory cell with fast access speed, because above-mentioned sram storage element can be the storage architecture of a position of storage (1bit), and what above-mentioned electric erasing type programmable read only memory memory cell was same is the storage architecture of a position (1bit), therefore, before power supply disappears, the data of each can be stored in the corresponding electric erasing type programmable read only memory memory cell immediately in the random access memory, that is the storage architecture of the nonvolatile memory of a correspondence one (Bit By Bit).

For reaching above-mentioned purpose, the invention provides a kind of non-volatile DRAM memory cell and mainly include a sram cell and a non-volatile memory cells, wherein sram cell is in order to receiving one data, to keep this one digit number certificate in a computing environment, and transmits this one digit number according to this computing environment; And non-volatile memory cells is connected with this static random access memory (sram) cell, in order to before power supply disappears, this one digit number certificate in the sram cell is stored to non-volatile memory cells, and after power supply disappears, this one digit number certificate is remained in the non-volatile memory cells, after treating that power supply is supplied again, reply this one digit number certificate to this sram cell.

The invention provides a kind of Nonvolatile static ROM memories, it includes:

One sram cell, include the first transistor, second electric crystal, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor, wherein this first transistor and the 3rd transistor are formed a reverser, this transistor seconds and the 4th transistor are formed another reverser, this the first transistor and the 3rd transistorized grid and this transistor seconds, the 4th transistor and the 6th transistor drain are joined, this transistor seconds and the 4th transistorized grid and this first transistor, the 3rd transistor and the 5th transistor drain are joined, and the grid of the 5th transistor AND gate the 6th electric crystal is connected with a word line; And

One non-volatile memory cells, be connected with this static random access memory (sram) cell, include the 7th transistor AND gate the 8th transistor, wherein the 7th electric crystal and the 8th transistorized grid join, the 7th transistor drain and this first transistor, the 3rd transistor and the 5th transistor drain are joined, and this transistor seconds of the 8th transistor AND gate, the 4th transistor and the 6th transistor drain are joined;

Wherein this sram cell is in order to receive 1 data, temporarily to preserve this 1 bit data, and transmit the normal running of this 1 bit data, this non-volatile memory cells is before power supply disappears, store in this sram cell 1 data (store operation), after power supply disappears, keep this 1 bit data (preserving operation), after treating that power supply is supplied again, reply this one digit number according to this sram cell, (replying operation), and after the answer operation is finished, data are removed (clear operation) in this non-volatile memory cells.

The present invention proposes a kind of new-type Nonvolatile static access memory memory cell, make when power supply disappears, data in static random access memory (sram) cell not reason power supply disappear and disappear, and because the sram storage element of each all has a corresponding memory cell, no matter make when storing or returning back to static random access memory (sram) cell, the mode that is one of a correspondence is carried out, can store fast and reading of data, effectively reduce the consumption of power.

About feature of the present invention and practical manner, cooperate icon to be described in detail as follows now as most preferred embodiment:

Description of drawings

Fig. 1 is the circuit diagram of Nonvolatile static ROM memories of the present invention.

Embodiment

Discuss for convenience and the carrying out of reading, below replace sram storage element with SRAM cell (sram cell), the electric erasing type programmable read only memory memory cell with memory function is then called with EEPROM cell.Usually, memory function that is so-called non-volatile, so EEPROM cell is further called with nv cell (memory cell), wherein nv promptly refers to non-volatile (Non-Volatile).Nonvolatile static random access memory provided by the present invention is then called with nvSRAM.

As shown in Figure 1, the built-up circuit figure of nvSRAM provided by the present invention, include one and receive the SRAM cell 10 of data in the computing environment by bit line (Bit Line), storage architecture for the one digit number certificate, it can temporarily keep these data of, and in the time after a while,, data are sent in the external arithmetic environment according to the desired execution command of central processing unit.In addition, nvSRAM also includes a nv cell 20, is in order to store the data among the SRAM cell 10 before the power supply complete obiteration, and when power supply disappears, can with data recording in nv cell 20, when treating the power up supply, again data be returned among the SRAM cell 10.

As shown in the figure, include six transistor (the first transistor Q1 among the SRAM cell, transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 5th transistor Q5, the 6th transistor Q6), a memory cell for a kind of six transistor architecture, be that a pair of CMOS reverser (Inverter) is connected into flip-flop (Flip Flop), memory node N1, N2 connects a pair of access transistor respectively as the transmission grid, be respectively the 5th transistor Q5, the 6th transistor Q6, Q5, the grid of Q6 connects word line (Word Line), via Q1, Q2 and and read and write between the bit line (Bit Line), write the transmission of data.Wherein Q3 and Q4 are P raceway groove MOS (metal-oxide-semiconductor) transistor (pMOS), and Q1 and Q2 are n raceway groove MOS (metal-oxide-semiconductor) transistor (nMOS), and Q1 and Q3, Q2 and Q4 form the CMOS reverser respectively.

The drain electrode (Drain) of the grid of Q1, Q3 (Gate) and Q2, Q4 is joined, Q2, Q4 grid join with the drain electrode of Q1, Q3, the source electrode of Q3, Q4 (Source) is received power supply and is supplied Vcc, the source electrode of Q1 and Q2 is ground connection then.When data 1 storage (latch) was in SRAM cell 10, Q2 was ON, and Q1 is OFF, and node N1 voltage is Vcc, and N2 voltage is 0.That is when Q1 is OFF and Q2 when being ON, then corresponding representative data 1 is stored among the SRAM cell.

The grid of the 5th transistor Q5 and the 6th transistor Q6 is connected to word line, drain electrode (or source electrode) then is connected respectively to node N1 and N2, source electrode (or drain electrode) is connected respectively to character line, the effect of Q5 and Q6 is as switch, when its state is ON, data can send out by character line, and the state of its ON and OFF is determined by the signal on the word line.When the voltage of word line was drawn high (high levle), access transistor Q5, Q6 just were opened.By word line one data storing is got up, and data passes is gone out by word line.

Include two splitting bars (split gate) transistor npn npn among the nv cell 20, be respectively the 7th transistor Q7 and the 8th transistor Q8, being the transistor that has memory function for a kind of, is to inject the mode disengage with the floating boom (floating gate) of storage between grid and matrix by electronics.Wherein, the control grid of Q7, Q8 joins (Vcg), and its source electrode is be connected together (Vpp), and the drain electrode of Q7 is connected to node N1, and the drain electrode of Q8 is connected to node N2.

The reason of using two transistor Q7, Q8 is because the data of storage are to be stored among N1 and the N2 among the SRAM cell 10, therefore must come the state of corresponding N1 of Q7, Q8 and N2 with two transistors.

Below the mode of operation of whole memory unit is done further explanation.The Nonvolatile static ROM memories that the present invention mentions can 5 volts as working power, also can be with 3 volts as working power.Below discuss based on 3 volts of working powers.

We activate at the beginning from power supply and discuss.When power supply was powered at the beginning, the data that control chip can impel nv cell 20 to be stored in wherein returned back to earlier among the SRAM cell 10.

Source voltage Vcc=1～2 of transistor Q3 and the Q4 of this moment volt, word line voltage Vwl=0 volt, expression SRAM cell 10 at this moment is not selected.Voltage Vcg=4～6 of control gate volt among the nv cell 20, source voltage Vpp=4～6 volt.Under above-mentioned voltage-operated scope, the stored data in last power supply disappearance back can return back to the SRAM cell 10 from nv cell 20 earlier.

After data return back among the SRAM cell 10, then carry out the initialization of nv cell 20, also be about to data deletion among the nv cell 20, with as the storage of data next time.

The electronics of removing among the nv cell 20 is the high voltage differential that utilizes between floating boom and source electrode, reaching electronics penetrates the Oxide dielectric layer with the F-N tunnel type and moves to source electrode, on behalf of the electronics of these data, make do not existed among the 7th transistor Q7 and the 8th transistor Q8, Vcg=-4～-6 volt, voltage Vpp=8～10 of source electrode volt, and the Vcc=2.5 of SRAM cell 10～3.5 volt, Vss=0 volt, word line voltage Vwl=0 volt.

Two memory cell l0, the 20th for two memory cell independently, must avoid interference each other during operation.That is, when SRAM cell 10 when carrying out the arbitrary access read-write operation, nv cell 20 memory cell must remain the state of closing (OFF), and when nv cell 20 was storing and is being returned to data in the SRAM memory cell, SRAM cell was necessary for (OFF) state of closing.Therefore, when SRAM will carry out general read-write operation, with the voltage Vcg=0 volt of control gate, and source voltage Vpp was suspension joint or ground connection (voltage is 0 volt).Because of splitting bar voltage Vcg=0 volt, so nv cell 20 is a closed condition, nv cell 20 does not have the electric current process, so SRAM cell 10 can operate normally.

When Power supply detector senses the power supply disappearance, the meeting controlling signal of sending storage immediately, notice NVRAM stores the data instant among the SRAM cell 10 immediately.

Be stored into to can be considered the nv cell 20 from SRAM cell 10 data are read in SRAM cell 10, and data are write among the nv cell 20, that is nv cell 10 done the operation that writes.

In the time will carrying out write operation to nv cell 20, voltage Vcg=8～10 of nv cell 20 control gates volt, source voltage Vpp=4～6 volt, and the Vwl=0 volt of SRAM cell 10, write operation (Programming Operation) is carried out in Vcc=2.5～3.5 volt under the state of given this voltage.

(N1 is the accurate position of high voltage when the data that store among the SRAM are 1, N2 is 0 volt), node N1 voltage is Vcc=2.5～3.5 volt, therefore the voltage difference of Vpp and VN1 is greatly about 0.5 volt to 2.5 volts, this voltage difference is not enough to produce strong hot carrier, so there is not electronics to exist on the Q7 floating boom yet, therefore on behalf of nv cell, Q7 still ERASE STATE (do not have write data), relative Q8 has 4～6 volts of enough Vpp and VN2 voltage differences, the heat-flash carrier is produced, making has electronics to enter on the floating boom of Q8, is called PROGRAMIMG STATE (representing nv cell that write data is arranged).Therefore, Q7 is ERASE STATE, and Q8 is PROGRAMIMG STATE, represents 1 write.

When the data=0 among the SRAM (N1 is that 0 volt, N2 are the accurate positions of high voltage), node N2 voltage is for being 2.5 volts to 3.5 volts, therefore the voltage difference of Vpp and VN2 is greatly about 0.5 volt～2.5 volts, make that Q8 is ERASE STATE, relative Q7 is PROGRMAING STATE, represents 0 write.

As mentioned above, when power-off, data write among the nv cell 20 from SRAM cell 10, avoid the data in SRAM to disappear because of the disappearance of power supply.

In nv cell 20, data are write back among the SRAM cell 10, be considered as reading of data from nv cell 20.Reply operation and just carried out when the power supply supply recovers again, below explanation 0 and 1 data return back to the operating process of SRAM cell.

At this moment, voltage Vcg=4～6 of control gate volt, voltage Vpp=4～6 of source electrode volt, the Vwl=0 volt of SRAMcell 10, Vcc=1～2 volt.At this moment, the voltage of control gate only has 4～6 volts, so the not operation that can write.

When nv cell 20 storage datas 1, the 7th transistor Q7 is ERASE STATE, and the 8th transistor Q8 is PROGRAMMING STATE, because no electronics injects among the Q7, therefore become conducting (ON) state, Q8 has electronics to inject, and is not conducting (OFF) state, and Q7 has electric current to flow out, Q8 then no current flows out, make node N1 charge to high voltage relatively, N2 is a low-voltage, and representative data 1 returns back among the SRAM cell 10.

When nv cell 20 storage datas 0, the 7th transistor Q7 is PROGRAMMING STATE, and the 8th transistor Q8 is ERASE STATE, owing to there is electronics to inject among the Q7, therefore become conducting (OFF) state, Q8 does not have electronics and injects, and is not conducting (ON) state, and the Q7 no current flows out, Q8 then has electric current to flow out, make that relatively node N1 voltage is 0 volt, N2 charges to high voltage, and representative data 0 returns back among the SRAM cell 10.

Claims

1 one kinds of Nonvolatile static ROM memories is characterized in that including:

One sram cell is in order to receive 1 data, temporarily to preserve this 1 bit data and the normal running that transmits this 1 bit data; And

One non-volatile memory cells, be connected with this static random access memory (sram) cell, this non-volatile memory cells more includes two splitting bar transistor npn npns, in order to before power supply disappears, store the store operation of 1 bit data in this sram cell, after power supply disappears, the preservation operation that keeps this 1 bit data, after treating that power supply is supplied again, replying this 1 bit data to the answer in this sram cell operates, and replying after operation finishes the clear operation that data are removed in this non-volatile memory cells.

2. Nonvolatile static ROM memories as claimed in claim 1, it is characterized in that more including in this sram cell a pair of reverser and two N raceway groove metal-oxide half field effect transistors, the grid of these two N raceway groove metal-oxide half field effect transistors respectively is connected with a word line.

3. Nonvolatile static ROM memories as claimed in claim 1, when it is characterized in that this clear operation, the voltage of the control gate of this splitting bar transistor npn npn is Vcg=-4～-6 volt, and the source voltage of this splitting bar transistor npn npn is Vpp=8～10 volt.

4. Nonvolatile static ROM memories as claimed in claim 1, when it is characterized in that this sram cell normal running, the voltage of the control gate of this splitting bar transistor npn npn is 0 volt, and the source electrode of this splitting bar transistor npn npn is suspension joint or ground connection.

5. Nonvolatile static ROM memories as claimed in claim 1, when it is characterized in that store operation, the voltage of the control gate of this splitting bar transistor npn npn is Vcg=8～10 volt, the voltage Vwl=0 volt of the word line of this sram cell, the voltage of the control gate of this splitting bar transistor npn npn is greater than the voltage of this splitting bar transistor npn npn source electrode.

6. Nonvolatile static ROM memories as claimed in claim 1, when it is characterized in that replying operation, the voltage of the control gate of this splitting bar transistor npn npn divides transistorized source voltage with this and equates to be Vcg=Vpp=4～6 volt, the voltage Vwl=0 volt of the word line of this sram cell.

7. Nonvolatile static ROM memories as claimed in claim 1, when it is characterized in that this answer operation, this clear operation and this store operation, the voltage of the word line of this sram cell is pulled down to low level Vwl=0 volt.

8. Nonvolatile static ROM memories is characterized in that including:

One sram cell, include the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor and the 6th transistor, wherein this first transistor and the 3rd transistor are formed a reverser, this transistor seconds and the 4th transistor are formed another reverser, this the first transistor and the 3rd transistorized grid and this transistor seconds, the 4th transistor and the 6th transistor drain are joined, this transistor seconds and the 4th transistorized grid and this first transistor, the 3rd transistor and the 5th transistor drain are joined, and the 5th transistor AND gate the 6th transistorized grid is connected with a word line; And

One non-volatile memory cells, be connected with this sram cell, include the 7th transistor AND gate the 8th transistor, the 7th transistor AND gate the 8th transistor is the splitting bar transistor npn npn, wherein the 7th transistor AND gate the 8th transistorized grid joins, the 7th transistor drain and this first transistor, the 3rd transistor and the 5th transistor drain are joined, and this transistor seconds of the 8th transistor AND gate, the 4th transistor and the 6th transistor drain are joined;

Wherein this sram cell is in order to receive 1 data, temporarily to preserve this 1 bit data, and transmit the normal running of this 1 bit data, this non-volatile memory cells is before power supply disappears, the data that store in this sram cell 1 are finished store operation, after power supply disappears, keep this 1 bit data to finish and preserve operation, after treating that power supply is supplied again, reply this one digit number and reply operation according to this sram cell, finishing, and replying after operation finishes, data are removed in this non-volatile memory cells finished clear operation.