CN1290250C - Power factor compensation system for motor driving inverter system - Google Patents
Power factor compensation system for motor driving inverter system Download PDFInfo
- Publication number
- CN1290250C CN1290250C CNB001027891A CN00102789A CN1290250C CN 1290250 C CN1290250 C CN 1290250C CN B001027891 A CNB001027891 A CN B001027891A CN 00102789 A CN00102789 A CN 00102789A CN 1290250 C CN1290250 C CN 1290250C
- Authority
- CN
- China
- Prior art keywords
- voltage
- signal
- output
- driver element
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/08—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Control Of Ac Motors In General (AREA)
- Rectifiers (AREA)
Abstract
The present invention relates to a power factor compensation device for a motor driving inverter which can improve a power factor of a voltage and a current inputted to the inverter driving a motor. The present invention detects a zero crossing point of an utility alternating current power, and outputs a driving signal corresponding to a plurality of sine wave form voltage values stored in a memory according to a detection result, when the zero crossing point of the utility alternating current power is detected in a state where the plurality of sine wave form voltage values corresponding to a voltage of the utility alternating current power and frequencies are stored in the memory. A switching transistor is switched according to the driving signal, and the voltage applied to the inverter is switched according to the switching operation, thereby improving the power factor.
Description
Technical field
This is bright to relate to technology of voltage and current that control is input to the inverter of drive motors, particularly relates to a kind of power factor compensation device of motor drive inverter, and it can compensate the power factor of the voltage and current that is input to motor drive inverter.
Background technology
Inverter is used to control motor more and more in family expenses equipment, because it can be energy-conservation and be convenient to output control.The various housed devices that comprise washing machine and refrigerator have adopted and have been used for the inverter of drive motor.
Fig. 1 is a structural representation of common system for motor driving inverter system.As shown in the figure, the AC power 100 of input becomes direct voltage through after the full-wave rectification.The voltage of a choking-winding 112 and smmothing capacitor 113 level and smooth rectifications, and provide it to inverter 120.This level and smooth direct voltage is greater than the peak value of AC supply voltage.Inverter 120 converts level and smooth direct voltage to three-phase alternating-current supply, and provides it to motor 130.With the three-phase alternating-current supply drive motors 130 that converts.
Fig. 2 is the oscillogram of each device in the prior art.First waveform and second waveform are respectively the voltage and current waveforms of AC power.Time (t) is to be determined by the time constant of choking-winding 112 and smmothing capacitor 113, and is set to usually about 1/5 of the AC power cycle.On the other hand, during the time (t), produce the peak value of electric current rapidly.As a result, this peak value can produce noise, and owing to useless power causes damage.Above-mentioned shortcoming is because the power factor that the phase difference between voltage and the electric current produces causes.The 3rd waveform of Fig. 2 is represented the ideal current figure of AC power.As shown in the figure, when the electric current that offers inverter had identical phase place with the AC supply voltage phase place, the loss that is caused by useless power had just disappeared.
In order to produce electric current, in Fig. 3, represented a kind of device that can improve power factor with this waveform.
Fig. 3 is a structural representation, and expression is used for a kind of habitual power factor compensation device of inverter system.Power factor compensation unit 200 herein further comprises the structure of Fig. 1.Power factor compensation unit 200 comprises: choking-winding 112, analog integrated circuit 210, a plurality of resistance R 1-R13, a plurality of capacitor C 1-C3 and a plurality of diode D1, D2.Fig. 4 is the physical circuit figure of analog integrated circuit 210.Analog integrated circuit 210 shown in the figure comprises various logic circuitry.
The output of the direct voltage of bridge diode 111 is by the resistance R 1 of power factor compensation unit 200, after the R2 dividing potential drop by terminal 3. VM1 be input to integrated circuit 210.The voltage that offers choking-winding 112 is input to 5. Idet of terminal by resistance R 5.The voltage of choking-winding 112 is by resistance R 4 and diode D1, and the voltage of bridge diode 111 becomes the internal electric source VCC of integrated circuit 210 by resistance R 3.In addition, the direct voltage that offers inverter 120 by choking-winding 112 and diode D2 is by resistance R 11, after R12 and the R13 dividing potential drop by terminal 1. INV be input to integrated circuit 210.Be subjected to resistance R 7 in time constant, after the control of R8 and capacitor C 2, this voltage is imported into 2. COMP of terminal.In addition, a voltage of corresponding the electric current that offers inverter 120 just the voltage on the capacitor C 3 be imported into 4. CS of terminal.
The various logic circuitry of integrated circuit 210 inside receives these voltage, by 7. voltage of Vout output of terminal with predetermined duty cycle, these logical circuits have comparator 211,216,218,219, demultiplexer 217, inverter 11, NAND gate circuit 213,214, one self starters and a NOR gate circuit 215.
Fig. 5 represents by the voltage waveform after integrated circuit 210 processing.Label ' MO ' represents to be input to from demultiplexer 217 voltage waveform of comparator 216, and 4. ' CS ' expression is input to the voltage waveform of comparator 216 by terminal.As shown in Figure 5, MO and CS are compared, voltage Vout has big duty cycle in the little part of sine wave (right side in the drawings and left side), and has little duty cycle at mid portion.
Voltage Vout is provided for the grid of a switching transistor Q1, makes switching transistor Q1 carry out switch motion repeatedly, thereby eliminates the phase difference between the voltage and current that is input to inverter 120.Therefore, thus habitual power factor compensation device comes the compensation power factor to eliminate loss by further employing power factor compensation unit.Yet it has following shortcoming.
At first, the power factor compensation unit must constantly receive alternating voltage.Secondly, owing to adopted the power factor compensation circuit of simulation, the area of circuit has increased, and also can cause expense to rise thus.
Summary of the invention
Primary and foremost purpose of the present invention is the power factor of bucking-out system, the magnitude of voltage of the corresponding sinusoidal wave form of magnitude of voltage of storage in advance and effective AC power, and switch the voltage that offers inverter according to the phase place of effective AC power, make the magnitude of voltage of the sinusoidal wave form of its corresponding stored.
Another object of the present invention is to prevent to produce noise by the power supply that offers inverter.
For realizing above-mentioned purpose of the present invention, one aspect of the present invention has provided a kind of power factor compensation device that is used for system for motor driving inverter system, and this device comprises: be connected to the inverter on the motor; A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input; A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; An and switching transistor that is connected in parallel with inverter and switches according to drive signal, wherein the PAM driver element comprises: an indication generation unit, be used for receiving the zero passage input, produce an index signal in order, be added in the industrial frequency values of system on the indicated value and the output indicated value; A memory, portion storage within it corresponding a plurality of sinusoidal wave form magnitude of voltage of general AC supply voltage and frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the indicated as indicated address; A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form; One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And a counter, be used for when receiving interrupt signal output counting to the three-phase buffer, according to signal of count value output, and export above-mentioned inhibit signal to the three-phase buffer.
Another aspect of the present invention has provided a kind of power factor compensation device that is used for system for motor driving inverter system, and this device comprises: be connected to the inverter on the motor; A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input; A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And a switching transistor that is connected in parallel with inverter and switches according to drive signal, wherein the PAM driver element comprises: be used for transmitting the zero passage input or the gate of next address signal; The first indication generation unit is used for producing an index signal in proper order according to the output of gate, after adding the industrial frequency of system on the index signal with its output, and output one-period conditioning signal; Second indicates generation unit, is used for adding/subtracting according to the periodic adjustment signal frequency of operation of system, to gate output next address signal; A memory, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the address of appointment as indicated; A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form; One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And counter, be used for when receiving interrupt signal output counting to the three-phase buffer, according to signal of count value output, and export above-mentioned inhibit signal to the three-phase buffer, the first indication generation unit adds/subtracts according to the next address signal and exports an index signal.
Another aspect of the present invention has provided a kind of power factor compensation device that is used for system for motor driving inverter system, and this device comprises: be connected to the inverter on the motor; A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input; A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And a switching transistor that is connected in parallel with inverter and switches according to drive signal, wherein the PAM driver element comprises: be used for transmitting the zero passage input or the gate of next address signal; The first indication generation unit is used for producing an index signal in proper order according to the output of gate, after adding the industrial frequency of system on the index signal with its output, and output one-period conditioning signal; The second indication generation unit, the frequency of operation that adds/subtract system according to the periodic adjustment signal, export the next address signal to gate, and export the one-period variable signal to the first indication generation unit by judging the next address signal whether to produce carry; A memory, be used for the storage of portion within it corresponding the voltage of general alternating voltage and a plurality of sinusoidal wave form magnitude of voltage of frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the address of appointment as indicated; A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form; One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And counter, be used for when receiving interrupt signal output counting to the three-phase buffer, according to signal of count value output, and export above-mentioned inhibit signal to the three-phase buffer, the first indication generation unit adds/subtracts according to next address signal and cycle variable signal and exports an index signal.
Another aspect of the present invention has provided a kind of power factor compensation device that is used for system for motor driving inverter system, and this device comprises: be connected to the inverter on the motor; A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input; A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And a switching transistor that is connected in parallel with inverter and switches according to drive signal, wherein the PAM driver element comprises: a delay cell is used for when receiving the zero passage input the output again after scheduled time of zero passage input delay; A switch periods counting unit is used for according to zero passage input beginning counting operation, and exports a count completion signal when finishing the counting of a switch periods; A memory cell, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and the magnitude of voltage that starts the sine wave output form according to zero passage input that postpones or count completion signal; And a latch units that is used for output drive signal is activated according to the zero passage input, and the time of counting in time that correspondence sinusoidal wave form magnitude of voltage and switch periods counting unit is under an embargo when identical.
Description of drawings
With reference to being used for explaining that accompanying drawing of the present invention can further understand principle of the present invention, but accompanying drawing is not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is a kind of schematic block diagram of habitual system for motor driving inverter system;
Fig. 2 is the oscillogram of each unit in the prior art;
Fig. 3 is the structured flowchart that is used for illustrating a power factor compensation unit in the habitual inverter system;
Fig. 4 is the physical circuit figure of an integrated circuit among Fig. 3;
Fig. 5 is the voltage oscillogram of handling in the integrated circuit of Fig. 3;
Fig. 6 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of first embodiment of the invention;
Fig. 7 is the signal waveforms relevant with the microprocessor among Fig. 6;
Fig. 8 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of second embodiment of the invention;
Fig. 9 is the concrete structure schematic diagram according to a PAM driver element of second embodiment of the invention;
Figure 10 is the concrete structure schematic diagram according to a PAM driver element of third embodiment of the invention;
Figure 11 is the signal output waveform figure of each unit in the third embodiment of the invention;
Figure 12 is the signal output waveform figure of each unit in the fourth embodiment of the invention;
Figure 13 is the concrete structure schematic diagram according to the PAM driver element of fifth embodiment of the invention;
Figure 14 is the oscillogram of each unit among Figure 13;
Figure 15 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of the sixth embodiment of the present invention; And
Figure 16 has represented to be stored in the figure of the sinusoidal wave form magnitude of voltage in the memory of Figure 15.
Embodiment
Fig. 6 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of first embodiment of the invention.As shown in FIG., this power factor compensation device that is used for system for motor driving inverter system comprises: an effective AC power AC; Be used for effective AC power AC is carried out the bridge diode 110 of full-wave rectification; Be connected in series in a choking-winding L10 and a diode D10 of bridge diode 110 outputs one side; Be connected a smmothing capacitor C10 who is used for carrying out smooth operation on the diode D10 output; With the inverter 120 that smmothing capacitor C10 is connected in parallel, be used for pulse width modulation (PWM) and output pulse width modulation signal are carried out in rectification and level and smooth effective AC power AC; Be connected to a motor 130 on inverter 120 outputs; Two resistance R 20 that are one another in series connection and are connected in parallel with bridge diode 110, R21; A microprocessor 300 is used for receiving by resistance R 20, and a voltage of R21 dividing potential drop detects the zero crossing of effective AC power AC voltage, and exports the drive signal Sd that its duty cycle changes along with testing result; And be connected on the choking-winding L10 output and a switching transistor N1 of conducting/shutoff according to drive signal Sd.
Below will be with reference to the working method of Fig. 7 explanation according to this power factor compensation device that is used for system for motor driving inverter system of first embodiment of the invention.Fig. 7 is the signal waveforms relevant with microprocessor.
At this moment, the direct voltage of full-wave rectification is input to microprocessor 300 by resistance R 20 after the R21 dividing potential drop.Microprocessor 300 goes out zero crossing according to the voltage detecting of this dividing potential drop, and produces one in inside and detect pulse, and its waveform is second waveform among Fig. 7 just.
On the other hand, stored the magnitude of voltage of a plurality of sinusoidal wave forms of the voltage of corresponding effectively AC power AC and frequency in advance in microprocessor 300, its waveform is shown in the 3rd waveform among Fig. 7.These magnitudes of voltage are used to determine the duty cycle that outputs to the switch controlling signal on the switching transistor N1.The ON time of switching transistor N1 is determined according to this magnitude of voltage.So-called " sinusoidal wave form " is meant that the voltage graph by AC power AC has sinusoidal wave form, and the voltage graph that is stored in the microprocessor 300 is identical with the voltage graph of general AC power AC.In addition, also the frequency with general AC power AC is identical for the frequency of setting.
When inside had produced a correspondence and the detection pulse of zero crossing, microprocessor 300 just order produced the magnitude of voltage of sinusoidal wave form, and output corresponding the drive signal Sd of multiple voltage value.Drive signal Sd is provided for switching transistor N1 by resistance R 22.When switching transistor N1 was switched, just the direct voltage with full-wave rectification offered inverter 120 off and on.
Above-mentioned operation is to carry out in the half period of the general AC power AC of full-wave rectification, just from carrying out in the detection time to the detection time of next zero crossing of a zero crossing of general AC power AC voltage.Just repeat above-mentioned operation as long as detect zero crossing.So just can make the voltage and current phase place that is input to inverter 120 identical, thereby realize compensation the power factor of the voltage and current that is input to inverter 120 with the voltage and current phase place of general AC power AC.
On the other hand, as mentioned above, microprocessor 300 detects zero crossing, produces the voltage of sinusoidal wave form, and output drive signal Sd.Yet this operation can be carried out independently by various element, will give specific description in the second embodiment of the present invention.
Fig. 8 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of second embodiment of the invention.As shown in FIG., replace the microprocessor 300 of Fig. 6 to detect the zero crossing of general AC power AC with zero passage detection unit 400.In other words, zero passage detection unit 400 detects the zero crossing of general alternating current AC, and to zero passage input signal of a pulse amplitude modulation (PAM) driver element 500 outputs.Replace microprocessors 300 one of output to be used for the drive signal Sd of switching transistor N1 with PAM driver element 500, its duty cycle changes along with detected zero crossing.
On the other hand, a voltage level detection 600 is used to detect a voltage level when switching transistor N1 switches the direct voltage of rectification and offers inverter 120.That is, this voltage level detection 600 will offer the direct voltage dividing potential drop of inverter 120, the voltage Vm of dividing potential drop be outputed to PAM driver element 500, and carry out other function among first embodiment.PAM driver element 500 is according to the voltage level output drive signal Sd that offers inverter 120.That is to say that PAM driver element 500 is according to the zero crossing and the voltage level output drive signal Sd that is input to inverter 120 of general AC power AC.Come driving switch transistor N1 according to drive signal Sd, thereby compensation is input to the power factor of the voltage and current of inverter 120.
Below to describe the mode of operation of PAM driver element 500 with reference to Fig. 9 and 10 in detail.
Fig. 9 is the concrete structure schematic diagram according to a PAM driver element 500 of second embodiment of the invention.As shown in FIG., PAM driver element 500 comprises: an indication generation unit 510 receives the zero crossing input, produces an index signal, and the operation frequency value with system is added on the indicated value and the output indicated value in order; The magnitude of voltage that has the sinusoidal wave form of corresponding general AC power AC voltage in memory 520 in advance, and output is stored in the magnitude of voltage according to the sinusoidal wave form in the indicated address of the index signal of coming self-indication generation unit 510; 530 one of the output of coefficient calculation unit can reflect motor 130 characteristic coefficients, from the branch pressure voltage Vm of the voltage level detection 600 of Fig. 8, the performance of whole system, and the coefficient value of the rating of electric machine; Multiplier 540 multiply by behind this coefficient value the output valve of memory 520 with its output; Three-phase buffer 550 is according to an inhibit signal transmission or cut off output signal from multiplier 540; One interrupts generating unit 560 interrupt signal of output when one that has produced corresponding original system operation frequency values of setting predetermined clock number; A counter 770 starts a counting operation when receiving interrupt signal, load and export the output valve from multiplier 540, and provides above-mentioned inhibit signal according to the value of loading for three-phase buffer 770; And an AND door, be used for receiving output valve, anti-phase and reception zero passage input, and anti-phase and reset signal of reception from counter 770.In the present embodiment, being input to indication generation unit 510 is system operation frequencies with the frequency of interrupting generating unit 560.
Below to describe the mode of operation of PAM driver element 500 in detail.
When the input of input zero passage, indication generating unit 510 is initialised, thereby produces an indication.This indication is added on the system operation frequency and as the index signal of an output.This index signal is a signal that is used to refer to memory 520 addresses.On the other hand, be stored in the magnitude of voltage that produces the sinusoidal wave form of output in the zero crossing in memory 520, just corresponding the detection time from this zero crossing is to the voltage of the sine wave of the detection time of next zero crossing.In most preferred embodiment of the present invention, when the phase place of general AC power AC is 180 °, detect this zero crossing, thereby storage just corresponding sinusoidal wave at 180 ° of magnitudes of voltage of locating.If when the phase place of general AC power AC is 360 °, detect this zero crossing, just need storage corresponding sinusoidal wave at 360 ° of magnitudes of voltage of locating.Can replace memory 520 with PAM or ROM where necessary.When index signal has been indicated the address of memory 520, just export the magnitude of voltage of the sinusoidal wave form of this addressed memory storage.
On the other hand, coefficient calculation unit 530 also need be carried out accurate control operation according to electric system, therefore can not be used.If do not adopt coefficient calculation unit 530, just do not need multiplier 540 yet.This moment, the output voltage with memory 520 was input to buffer 550.
When receiving the interrupt signal of interrupting generating unit 560,570 pairs of numeric counter of counter by 550 inputs of three-phase buffer, and to high level signal of AND door 580 outputs.In addition, counter 570 is also exported a low level inhibit signal to three-phase buffer 550 during counting operation, and exports a high level inhibit signal to three-phase buffer 550 when finishing counting operation.Three-phase buffer 550 transmits the output of multiplier 540 when inhibit signal is in high level, and cuts off this output when inhibit signal is in low level.
AND door 580 is exported to switching transistor N1 with count value as drive signal Sd when the input of reset signal and zero passage all is in low level.That is to say that as long as have one to be high level, AND door 580 just can not output drive signal Sd in systematic reset signal and zero passage input.
When carrying out aforesaid operations, the magnitude of voltage that is stored in the sinusoidal wave form in the memory 520 index signal of generation unit 510 outputs is as indicated exported in order.On the other hand, after having passed through preset time, will detect the next zero crossing of general AC power AC, will import the zero passage input of this zero crossing like this, repeat to export the magnitude of voltage of whole sinusoidal wave forms.
Below to specifically describe a kind of power factor compensation device that is used for the motor driving inverter system according to third embodiment of the invention.Be stored in according to the sine voltage in the memory of second embodiment of the invention worthwhile in, be symmetrical from 0 ° to 90 ° sine voltage value with from 0 ° to 180 ° sine wave.The third embodiment of the present invention has been utilized this characteristics exactly.If on each 180 ° of general AC power AC, can both detect zero crossing, the just sine voltage value of storage between 0 ° to 90 ° in memory, and output repeatedly.
That is to say, according to the 3rd embodiment, under four/one-period (90 °) sine voltage value that correspondence sinusoidal wave (half period of general AC power AC) is stored in state in the memory, if the phase place of general AC power AC is 0 ° to 90 °, just increase in order and the designated memory address, if the phase place of general AC power AC is 90 ° to 180 °, just reduce in order and the designated memory address.Therefore, when detecting zero crossing, each the sine voltage value that is stored in the memory is output twice.Another example is, if detect a zero crossing every 360 ° on general AC power AC, just correspondence need sinusoidal wave 180 ° magnitude of voltage and be stored in the memory and export twice.Consequently, compare with the employed memory of second embodiment, the capacity of memory can dwindle half.But the result who obtains is identical with second embodiment.The mode of operation of the mat woven of fine bamboo strips three embodiment of the present invention below will specifically be described with reference to Figure 10 and 11.
Figure 10 is the concrete structure schematic diagram according to the PAM driver element 500 of third embodiment of the invention.An OR door OR, the first indication generation unit 511 and the second indication generation unit 512 are equivalent to the indication generation unit 510 among second embodiment.The quantity that is stored in the sine voltage value in the memory 520 has only half of the magnitude of voltage quantity that is stored among second embodiment in the memory.Figure 11 is the signal output waveform figure of each unit in the third embodiment of the invention, illustrated state be general AC power AC locate to detect a zero crossing every 180 °, and the magnitude of voltage that correspondence 90 ° of sine waves is stored in the memory.
As shown in figure 10, OR door OR carries out inclusive-OR operation to zero passage input and next address signal, the first indication generation unit 511 receives the output signal of OR door OR, and produce an index signal and one-period conditioning signal in_dir, on index signal, add or deduct the frequency of operation of system by the second indication generation unit 512 according to periodic adjustment signal in_dir, and the next address signal that bears results.With memory 520 storage corresponding the sine voltage value of 90 ° of sine waves, the half period of the general AC power AC of full-wave rectification just.When first one of indicating generation unit 511 to export indicated the address of appointment, memory 520 was just exported the sine voltage value that is stored in this address.On the other hand, used a cycle variable signal out_dir who outputs to the first indication generation unit 511 from the second indication generation unit 512 in the fourth embodiment of the invention that will illustrate hereinafter.
Periodic adjustment signal in_dir herein is a signal that is used for obtaining next storage address, just is used for determining the signal that next storage address increases or subtracts.As shown in figure 11, periodic adjustment signal in_dir is a low level when the phase place of general AC power AC is in 0 ° to 90 °, and is high level when the phase place of general AC power AC is in 90 ° to 180 ° and 270 ° to 360 °.When periodic adjustment signal in_dir was in low level, the second indication generation unit 512 was added in frequency of operation on the current address, and when periodic adjustment signal in_dir was in high level, the second indication generation unit 512 deducted frequency of operation from the current address.Other element all is identical with second embodiment, thereby need not further explanation.The mode of operation of OR door OR and first and second indication generation unit 511,512 below will be described.
When receiving the zero passage input, OR door OR makes 511 initialization of the first indication generation unit to high signal of the first indication generation unit, 511 outputs.The first indication generation unit 511 correspondingly export and is used for the index signal of first address of designated memory 520 and the periodic adjustment signal in_dir of while output low level.Come first address of designated memory 520 according to this index signal, output is stored in the sine voltage value in first address thereupon.Because periodic adjustment signal in_dir is in low level, the second indication generation unit 512 is added in frequency of operation and calculates next address on the current address, and it is outputed to OR door OR.The first indication generation unit 511 is used for the indication of designated memory 520 subsequent address according to one of the output of the next address by OR door OR.The sine voltage value that memory 520 will be stored in the subsequent address outputs to first address.The first indication generation unit 511 remains on low level with periodic adjustment signal in_dir, reaches 90 ° until the phase place of general AC power AC.
Repeating above-mentioned operation, and when obtaining corresponding the magnitude of voltage of 90 ° of sine waves, 511 outputs of the first indication generation unit are used for the index signal of designated memory FA final address and the periodic adjustment signal in_dir of output high level.Signal is exported the sine voltage value that is stored in the FA final address from memory 520 as indicated.Simultaneously, the second indication generation unit 512 deducts frequency of operation according to the periodic adjustment signal in_dir of high level from the current address, calculate next address, and next address is outputed to OR door OR.The first indication generation unit 511 deducts the next address that is subtracted from previous indicated value, and exports this indicated value, and periodic adjustment signal in_dir is remained on high level, reaches 180 ° until the phase place of general AC power AC.For example, when the phase place of general AC power AC is 160 ° (180 °-20 °), just output corresponding the magnitude of voltage of 20 ° of sine waves.
As mentioned above, after having imported zero passage input,, just increase indication if the phase place of general AC power AC is 0 ° to 90 °, and in order output corresponding 0 ° of magnitude of voltage to 90 ° of sine waves.Otherwise, if the phase place of general AC power AC is 90 ° to 180 °, just reduce indication, and output in reverse order corresponding 0 ° of magnitude of voltage to 90 ° of sine waves.Therefore, although be stored in half of sine voltage value that the sine voltage value in the memory 520 only is necessary, still can export the magnitude of voltage that is equivalent to general AC power AC half period (one-period of the general AC power AC of rectification).Therefore, according to this 3rd embodiment, the capacity of memory and second embodiment compared reduced half.But but can obtain the result identical with second embodiment.
Below will be with reference to Figure 10 and 12 power factor compensation devices that are used for the motor driving inverter system that illustrate according to fourth embodiment of the invention.In the 4th embodiment,, just will be stored in the memory and repeat output about 0 ° to 90 ° sine voltage value if locate to detect zero crossing each 360 ° of general AC power AC.
According to the 4th embodiment, under the sine voltage value that correspondence four/one-period of general AC power AC is stored in state in the memory, if the phase place of general AC power AC is 0 ° to 90 ° and 180 ° to 270 °, just increase in order and the designated memory address.If the phase place of general AC power AC is 90 ° to 180 ° and 270 ° to 360 °, just reduce in order and the designated memory address.Therefore, when detecting zero crossing, each the sine voltage value that is stored in the memory is output four times.In the 3rd embodiment, each sine voltage value is output twice, and in the 4th embodiment, each sine voltage value is output four times.
The fourth embodiment of the present invention is to carry out in device shown in Figure 10, below will be illustrated with reference to Figure 12 particularly.Figure 12 is the signal output waveform figure of each unit in the fourth embodiment of the invention, illustrated state be general AC power AC locate to detect a zero crossing every 360 °, and the magnitude of voltage that correspondence 90 ° of sine waves is stored in the memory.
Below to specify the mode of operation of the first indication generation unit 511 and the second indication generation unit 512 of the 4th embodiment.Other element all is identical with the second and the 3rd embodiment, thereby need not further explanation.
The first indication generation unit 511 receives by the next address of OR door OR input with from second and indicates the cycle variable signal out_dir of generation unit 512, output index signal, and output periodic adjustment signal in_dir.The second indication generation unit 512 deducts system according to index signal and periodic adjustment signal in_dir from 511 inputs of the first indication generation unit from index signal frequency of operation, produce the next address signal, whether judgement carry takes place in the next address signal, and to the first indication generation unit, 511 output cycle variable signal out_dir.When carry takes place, with regard to the cycle variable signal out_dir of output low level.Under the situation that carry does not take place, just export the cycle variable signal out_dir of high level.
In order to explain the operation of the first indication generation unit 511, adopted median a, b (not shown) and a polarity number.Median a herein, b temporarily are used for representing the phase place (0 ° to 360 °) of general AC power AC and are stored in the phase place (0 ° to 90 °) of the sine voltage in the memory 520.Adopt polarity number to calculate median a, b.When polarity number was ' 0 ', ' a-b ' operation was then represented in its expression ' a+b ' operation when polarity number is ' 1 '.
When the phase place of general AC power AC meets the phase place of sine voltage, just formed the relation as shown in following table.Mark Pac in the table represents the phase place of general AC power AC.
| The phase place of general AC power AC | a[15:0 ] | b[15:0] | Polarity number | Be stored in the phase place of the sine voltage in the |
| 0 ° to 90 ° | | 0 | 0 | a+b＝Pac+0 |
| 90 ° to 180 ° | 180° | | 1 | a-b＝180-Pac |
| 180 ° to 270 ° | Pac | 180° | 1 | a-b＝Pac-180 |
| 270 ° to 360 ° | 180° | | 1 | a-b＝360-Pac |
In last table, in fact there be not " phase place that is stored in the sine voltage in the memory ", but adopt for convenience.That is to say that the phase place of sine voltage is corresponding a conception of species that is stored in the address of the sine voltage in the memory 520, and the first indication generation unit 511 outputs to a conception of species of the indicated value of memory 520.
Below to explain four kinds of situations according to table.
At first, if the phase place of general AC power AC is 0 ° to 90 °, the first indication generation unit 511 just produces indicated value that should phase place, has so just specified the address of memory 520.Correspondingly export the sine voltage value that is stored in this address therewith.
Secondly, if the phase place of general AC power AC is 160 °, the first indication generation unit 511 is just exported 180 ° to 160 °, just corresponding 20 ° the indicated value of general AC power AC.
The 3rd, if the phase place of general AC power AC is 210 °, the first indication generation unit 511 is just exported 210 ° to 180 °, just corresponding 30 ° the indicated value of general AC power AC.
The 4th, if the phase place of general AC power AC is 340 °, the first indication generation unit 511 is just exported 360 ° to 340 °, just corresponding 20 ° the indicated value of general AC power AC.
As mentioned above, when receiving the zero passage input by OR door OR, the first indication generation unit 511 uses median a+b output indicated value.The second indication generation unit 512 by give/add/deduct that from periodic adjustment signal in_dir the system operation frequency calculates follow-up indicated value next_address, and according to periodic adjustment signal in_dir and follow-up indicated value by give/add/deduct that from follow-up indicated value the system operation frequency calculates cycle variable signal out_dir.
More particularly, when periodic adjustment signal in_dir was ' 0 ', the phase place of general AC power AC was 0 ° to 90 ° and 180 ° to 270 °.At this moment just the system operation frequency is added on the indicated value of input, and is used as follow-up indicated value next_address and is output.If periodic adjustment signal in_dir is ' 1 ', the phase place of general AC power AC is exactly 90 ° to 180 ° and 270 ° to 360 °.At this moment just deduct the system operation frequency, and be used as follow-up indicated value next_address and be output from the indicated value of input.
In addition, if do not produce carry in the process of calculated for subsequent indicated value next_address, the phase place of general AC power AC will be stabilized between 90 ° to 180 ° or 270 ° to 360 °, just exports the cycle variable signal out_dir of high level this moment.If produced carry, the phase place of general AC power AC will surpass 180 ° or 360 °, and this moment is with regard to the cycle variable signal out_dir of output low level.
As indicated above, according to the fourth embodiment of the present invention, the sine voltage value that is stored in the memory is output four times in the one-period (360 °) of general AC power AC, so just can dwindle the capacity of memory.
Although it is in first to the 4th embodiment of the present invention, directly used the detected value of zero crossing, differentiated slightly between the actual zero crossing of general AC power AC and its zero crossing detected value.As shown in Figure 14, the actual zero crossing of general AC power AC produces at a t2 place.Yet because the characteristic of circuit, the zero crossing detected value is detected at a t1 place.Therefore, for compensation power factor exactly, system must come work according to the zero crossing of reality.
Can compensate the error time t2-t1 of zero crossing according to the PAM driver element 500 of fifth embodiment of the invention, and according to the time driving switch transistor N1 of compensation, thereby make system come work according to the zero crossing of reality.Below to describe operation in detail according to the PAM driver element 500 of fifth embodiment of the invention.For convenience of explanation, below hypothesis detects a zero crossing in each cycle of general AC power AC, and the sine voltage value of correspondence the half period of general AC power AC is stored in the memory.
Below to explain the fifth embodiment of the present invention with reference to Figure 13 and 14.Figure 13 is the concrete structure schematic diagram according to the PAM driver element 500 of fifth embodiment of the invention, and Figure 14 is the oscillogram of each unit among Figure 13.
As shown in figure 13, PAM driver element 500 comprises: a delay cell 600 is used for exporting after with zero passage input delay preset time receiving zero passage when input; A switch periods computing unit 700 according to zero passage input beginning counting operation, and is exported a count completion signal Sc when finishing the counting of a switch periods; A memory cell 800, in storage inside many sine voltage values of corresponding general AC power AC voltage and frequency, and the magnitude of voltage that starts its sine wave output form according to zero passage input that postpones or count completion signal Sc; And one according to zero passage input or count completion signal Sc is activated, and the time of counting in correspondence sinusoidal wave form magnitude of voltage time and switch periods counting unit 700 forbidden latch units when identical, is used to export a drive signal Sd.
Delay cell 600 comprises: a delay timer 610 is used for beginning counting operation when receiving the zero passage input; Delay time register 620 with predetermined error time; And through being used for one the first comparator C MP1 of zero passage input of output delay behind the above-mentioned error time.
Switch periods counting unit 700 comprises: according to the first latch LTH1 of zero passage input setting; With the timer 710 that first latch starts, be used for the enabling counting operation; Be used for storing the TOPF register 720 of the time of corresponding switch periods; And one the 3rd comparator C MP3, be used for when gate time is identical with the time in being stored in TOPF register 720, exporting count completion signal Sc.
Memory cell 800 comprises a memory access unit 810 that starts according to zero passage input that postpones or count completion signal Sc, is used to export an address signal and one and reads enabling signal rd_enable; A memory cell 820, many sine voltage values of corresponding general AC power AC voltage and frequency have been stored within it, and be activated and read according to reading enabling signal rd_enable, make its output be stored in voltage according to the sinusoidal wave form in the address of address signal appointment.
Latch units 900 comprises: the second comparator C MP2, be used for the time that correspondence sinusoidal wave form magnitude of voltage was compared with the time of counting in the switch periods counting unit 700, and output result's signal; And second a latch LTH2 who resets according to the output of the second comparator C MP2, be used for output drive signal Sd.
Below to explain the mode of operation of fifth embodiment of the invention.
The zero passage input is input to the first latch LTH1 of switch periods generation unit 700, and is input to an OR door OR1 by the delay timer 610 that AND door AND is imported into delay cell 600.The second latch LTH2 is according to setting from the output of an OR door OR1.Therefore, the output that starts the second latch LTH2 when high level offers switching transistor N1 by a different OR door E-OR and as drive signal N1.
Error time t2-t1 sets in the delay time register 620 of delay cell 600.According to zero passage input after the beginning counting operation, during the error time t2-t1 that in having passed through delay time register 620, set, become high level at time t2 place at delay timer 610 from the output of the first comparator C MP1.The output of the first comparator C MP1 starts memory access unit 810 by the 2nd OR door OR2.Like this, memory access unit 810 is just exported first address signals and is read enabling signal rd_enable to memory 820.Be activated the sine voltage value of memory 820 its storage inside of output of reading.This is on duty with shift register 850 of immigration behind the department of electrical engineering numerical value of setting in the AMP register 830, and be input to the second comparator C MP2.This input value is the time of preparing output high level drive signal Sd, and the time that is used for determining the ON time of switching transistor N1.
The first latch LTH1 of switch periods generation unit 700 receives the zero passage input, starts timer 710 its counting operations of beginning.Count value is imported into the first comparator C MP1 and the 3rd comparator C MP3.When the output valve of count value and shift register 850 was identical, the output of the second comparator C MP2 became high level, and the output of the second latch LTH2 becomes low level, and drive signal Sd is under an embargo when low level.On the other hand, if the count value of timer 710 increases and has reached the scheduled time of setting in the TOPF register 720 always, switch periods just, the output of the 3rd comparator C MP3 will become high level, starts memory access unit 810 with an enabling signal by the 2nd OR door OR2.Like this, memory access unit 810 is just exported second address signals and is read enabling signal rd_enable to memory 820.The switch periods correspondence of setting in TOPF register 720 one-period of drive signal Sd.If supposition switch periods 50 μ sec, and the output valve of shift register 850 is the time that correspondence 30 μ sec, the waveform of drive signal Sd is as shown in figure 14.On the other hand, the level of drive signal Sd can change along with the polarity number of another input that is input to different OR door E_OR.That is to say that drive signal Sd becomes low or high according to polarity number.
Along with memory access unit 810 increments and OPADD signal in proper order one by one, the sine voltage value that is stored in the memory 820 is exported in proper order.Repeated priming drive signal Sd periodically so just.
On the other hand, final address register 860 is with the FA final address value of memory 820, and the FA final address value of just storing the sine voltage value outputs to one the 4th comparator C MP4.If the address of memory access unit 810 outputs is FA final address, the 4th comparator C MP4 just exports a high level mark signal.Memory access unit 810 is successively decreased from this point in order, and OPADD signal one by one.
When the address from memory access unit 810 inputs was ' 00h ', the output of the 5th comparator C MP5 became high level.At this moment, the first latch LTH1 is reset, and stops the operation of timer 710.In fact, when the sine voltage value in being stored in memory 820 was repeated to export, the operation of PAM driver element 500 was stopped, when the follow-up zero passage input of input till, in order to avoid system's generation abnormal operation.
In addition, prevent owing to wrong zero passage input appears in the noise that produces unusually with the 6th comparator C MP6 on the input that is connected to AND door AND.If being input to four high positions of the address of memory access unit 810 is ' 0h ', the 6th comparator C MP6 is just to AND door AND output high level output signal.
Below to explain a kind of power factor compensation device that is used for system for motor driving inverter system with reference to Figure 15 and Figure 16 according to sixth embodiment of the invention.Although being the frequency according to general AC power AC in first to the 5th embodiment of the present invention, the sine voltage value is stored in the memory, in the sixth embodiment of the present invention, and the operation of system and the frequency-independent of general AC power AC.Figure 15 is the structural representation according to a kind of power factor compensation device that is used for system for motor driving inverter system of sixth embodiment of the invention.In the present embodiment, compare, further comprise a frequency judging unit 700 with the power factor compensation device that is used for system for motor driving inverter system according to second embodiment of the invention shown in Figure 8.In addition, store the sine voltage value with a memory (not shown) of PAM driver element 500 with the frequency form in the table shown in Figure 16.
On the other hand, if the sampling period of supposition sine voltage value is constant,, just must change the quantity of sine voltage value if the frequency of general AC power AC changes.For example, if the frequency of general AC power AC is 60Hz, be 200 if adopt the sine voltage value quantity in this sampling period, so, if the frequency of general AC power AC is 50Hz, the quantity of sine voltage value is exactly 160.
With frequency judging unit 700 according to current detection to zero crossing and the preceding once detected zero crossing frequency of judging the general AC power AC of input, and to PAM driver element 500 its testing results of output.PAM driver element 500 is specified the corresponding memory address according to the frequency of judging, thereby output is stored in the sine voltage value in the assigned address.
For example, be 60Hz if frequency judging unit 700 is judged the frequency of general AC power AC, PAM driver element 500 is just at first specified an address 0005, and next specifies an address 0011.Otherwise, be 50Hz if judge the frequency of general AC power AC, PAM driver element 500 is just at first specified an address 0004, and next specifies an address 0010.
Because the present invention has multiple avatar not breaking away under its principle or the condition of essential characteristic, specific description is only arranged in addition, the above embodiments should be understood that not to be subjected to the restriction of any details mentioned above, but should be considered to all to belong within the scope that its principle and claims are defined, therefore, drop on the scope that all interior changes of claims scope and modification or the form equivalent with it all should belong to claims.
Claims (27)
1. power factor compensation device, be used for a kind of motor driving inverter system, in said motor driving inverter system general AC power is carried out rectification/level and smooth, and come drive motor with pulse width modulation, described power compensating device comprises:
Be connected to the inverter on the motor;
A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input;
A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And
A switching transistor that is connected in parallel with inverter and switches according to drive signal,
Wherein the PAM driver element comprises:
An indication generation unit is used for receiving zero passage input, produces an index signal in order, is added on the indicated value the industrial frequency values of system and the output indicated value;
A memory, portion storage within it corresponding a plurality of sinusoidal wave form magnitude of voltage of general AC supply voltage and frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the indicated as indicated address;
A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form;
One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And
A counter is used for when receiving interrupt signal the output counting to the three-phase buffer, according to signal of count value output, and exports above-mentioned inhibit signal to the three-phase buffer.
2. according to the device of claim 1, further comprise a voltage level detection, be used for detecting the commutated direct current that offers inverter and press, and to the voltage of a dividing potential drop of PAM driver element output, the PAM driver element is exported its drive signal according to the level of branch pressure voltage.
3. according to the device of claim 1, the PAM driver element further comprises:
A coefficient calculation unit is used at voltage and the coefficient value that can reflect the motor characteristic coefficient of receiving a dividing potential drop of output when pressing from the commutated direct current that offers inverter; And
A multiplier is used for outputing it to the three-phase buffer after sinusoidal wave form magnitude of voltage with memory output multiply by described coefficient value.
4. according to the device of claim 1, the PAM driver element further comprises a gate, is used for transmitting from the signal of counter output when the input of systematic reset signal and zero passage all is in low level.
5. according to the device of claim 1, further comprise a frequency judging unit, be used for according to current detection to zero crossing and the preceding once detected zero crossing frequency of judging the general AC power of input, and export its testing result to the PAM driver element, the PAM driver element comes the address of designated memory according to the frequency of judging, thereby output is stored in the sine voltage value in the assigned address.
6. power factor compensation device, be used for a kind of motor driving inverter system, in said motor driving inverter system general AC power is carried out rectification/level and smooth, and come drive motor with pulse width modulation, described power compensating device comprises:
Be connected to the inverter on the motor;
A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input;
A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And
A switching transistor that is connected in parallel with inverter and switches according to drive signal,
Wherein the PAM driver element comprises:
Be used for transmitting the zero passage input or the gate of next address signal;
The first indication generation unit is used for producing an index signal in proper order according to the output of gate, after adding the industrial frequency of system on the index signal with its output, and output one-period conditioning signal;
Second indicates generation unit, is used for adding/subtracting according to the periodic adjustment signal frequency of operation of system, to gate output next address signal;
A memory, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the address of appointment as indicated;
A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form;
One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And
A counter, be used for when receiving interrupt signal output counting to the three-phase buffer, according to signal of count value output, and export above-mentioned inhibit signal to the three-phase buffer, the first indication generation unit adds/subtracts according to the next address signal and exports an index signal.
7. according to the device of claim 6, further comprise a voltage level detection, be used for detecting the commutated direct current that offers inverter and press, and to the voltage of a dividing potential drop of PAM driver element output, the PAM driver element is exported its drive signal according to the level of branch pressure voltage.
8. according to the device of claim 6, wherein the PAM driver element further comprises:
A coefficient calculation unit is used at voltage and the coefficient value that can reflect the motor characteristic coefficient of receiving a dividing potential drop of output when pressing from the commutated direct current that offers inverter; And
A multiplier is used for outputing it to the three-phase buffer after sinusoidal wave form magnitude of voltage with memory output multiply by this coefficient value.
9. according to the device of claim 6, wherein the PAM driver element further comprises a gate, is used for transmitting from the signal of counter output when the input of systematic reset signal and zero passage all is in low level.
10. according to the device of claim 6, further comprise a frequency judging unit, be used for according to current detection to zero crossing and the preceding once detected zero crossing frequency of judging the general AC power of input, and export its testing result to the PAM driver element, the PAM driver element comes the address of designated memory according to the frequency of judging, thereby output is stored in the sine voltage value in the assigned address.
11. power factor compensation device, be used for a kind of motor driving inverter system, in said motor driving inverter system general AC power is carried out rectification/level and smooth, and come drive motor with pulse width modulation, described power compensating device comprises:
Be connected to the inverter on the motor;
A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input;
A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And
A switching transistor that is connected in parallel with inverter and switches according to drive signal,
Wherein the PAM driver element comprises:
Be used for transmitting the zero passage input or the gate of next address signal;
The first indication generation unit is used for producing an index signal in proper order according to the output of gate, after adding the industrial frequency of system on the index signal with its output, and output one-period conditioning signal;
The second indication generation unit, the frequency of operation that adds/subtract system according to the periodic adjustment signal, export the next address signal to gate, and export the one-period variable signal to the first indication generation unit by judging the next address signal whether to produce carry;
A memory, be used for the storage of portion within it corresponding the voltage of general alternating voltage and a plurality of sinusoidal wave form magnitude of voltage of frequency, and output is stored in the magnitude of voltage of the sinusoidal wave form in the address of appointment as indicated;
A three-phase buffer is used for according to an inhibit signal transmission or the magnitude of voltage that cuts off sinusoidal wave form;
One interrupts generating unit, is used for producing an interrupt signal according to the industrial frequency of system; And
A counter, be used for when receiving interrupt signal output counting to the three-phase buffer, according to signal of count value output, and export above-mentioned inhibit signal to the three-phase buffer, the first indication generation unit adds/subtracts according to next address signal and cycle variable signal and exports an index signal.
12. device according to claim 11, further comprise a voltage level detection, be used for detecting the commutated direct current that offers inverter and press, and to the voltage of a dividing potential drop of PAM driver element output, the PAM driver element is exported its drive signal according to the level of branch pressure voltage.
13. according to the device of claim 11, wherein the PAM driver element further comprises:
A coefficient calculation unit is used at voltage and the coefficient value that can reflect the motor characteristic coefficient of receiving a dividing potential drop of output when pressing from the commutated direct current that offers inverter; And
A multiplier is used for outputing it to the three-phase buffer after sinusoidal wave form magnitude of voltage with memory output multiply by this coefficient value.
14. according to the device of claim 11, wherein the PAM driver element further comprises a gate, is used for transmitting from the signal of counter output when the input of systematic reset signal and zero passage all is in low level.
15. device according to claim 11, further comprise a frequency judging unit, be used for according to current detection to zero crossing and the preceding once detected zero crossing frequency of judging the general AC power of input, and export its testing result to the PAM driver element, the PAM driver element comes the address of designated memory according to the frequency of judging, thereby output is stored in the sine voltage value in the assigned address.
16. power factor compensation device, be used for a kind of motor driving inverter system, in said motor driving inverter system general AC power is carried out rectification/level and smooth, and come drive motor with pulse width modulation, described power compensating device comprises:
Be connected to the inverter on the motor;
A zero passage detection unit is used for detecting the zero crossing of general AC power and exports a zero passage input;
A PAM driver element, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and in order output corresponding the drive signal of a plurality of sinusoidal wave form magnitudes of voltage; And
A switching transistor that is connected in parallel with inverter and switches according to drive signal,
Wherein the PAM driver element comprises:
A delay cell is used for when receiving the zero passage input zero passage input delay being exported after a scheduled time again;
A switch periods counting unit is used for according to zero passage input beginning counting operation, and exports a count completion signal when finishing the counting of a switch periods;
A memory cell, be used for the storage of portion within it corresponding the voltage of general AC power and a plurality of sinusoidal wave form magnitude of voltage of frequency, and the magnitude of voltage that starts the sine wave output form according to zero passage input that postpones or count completion signal; And
A latch units that is used for output drive signal is activated according to the zero passage input, and the time of counting in time that correspondence sinusoidal wave form magnitude of voltage and switch periods counting unit is under an embargo when identical.
17. device according to claim 16, further comprise a voltage level detection, be used for detecting the commutated direct current that offers inverter and press, and to the voltage of a dividing potential drop of PAM driver element output, the PAM driver element is exported its drive signal according to the level of branch pressure voltage.
18. according to the device of claim 16, wherein delay cell comprises:
A delay timer is used for beginning counting operation when receiving the zero passage input;
Delay time register with predetermined error time; And
Through being used for first comparator of zero passage input of output delay behind the described error time.
19. according to the device of claim 16, wherein switch periods counting unit comprises:
The first latch LTH1 according to ground zero input setting;
With the timer that first latch starts, be used for the enabling counting operation;
Be used for storing the TOPF register of the time of corresponding switch periods; And
One the 3rd comparator is used for exporting count completion signal when gate time is identical with the time in being stored in the TOPF register.
20. according to the device of claim 16, wherein memory cell comprises:
A memory access unit that starts according to zero passage input that postpones or count completion signal is used to export an address signal and one and reads enabling signal; And
A memory cell, many sine voltage values of corresponding general AC power AC voltage and frequency have been used for storing within it, and be activated and read according to reading enabling signal, make its output be stored in voltage according to the sinusoidal wave form in the address of address signal appointment.
21. according to the device of claim 16, wherein latch units comprises:
The time of counting in second comparator, the time that is used for correspondence sinusoidal wave form magnitude of voltage and switch periods counting unit compares, and output result's signal; And
One is activated according to zero passage input, and second latch that resets according to the output of second comparator, is used for output drive signal.
22. according to the device of claim 16, wherein the PAM driver element further comprises:
Be used for an AMP register of store electricity motivation coefficient value;
A multiplier is used for sinusoidal wave form magnitude of voltage be multiply by the coefficient value of motor; And
A shift register is used for output valve to multiplier and is shifted and it is outputed to latch units, and latch units is compared the time of counting in the switch periods counting unit and the time of corresponding shift register output valve.
23. the device according to claim 20 further comprises:
A final address register is used for the FA final address value of output storage; And
If one the 4th comparator identical with the address of final address register output from the address of memory access unit input, is just exported a mark signal; Memory access unit receives described mark signal one by one, reduces and the OPADD signal.
24. according to the device of claim 20, further comprise the 5th comparator, signal of forbidding latch units of output when being used for address in memory access unit input less than first address.
25. the device according to claim 20 further comprises:
The 6th comparator is used to judge whether the address of memory access unit input is first address, and exports a consequential signal; And
A gate is used for importing to delay cell output zero passage at the output time that receives from the 6th comparator.
26. according to the device of claim 16, wherein the level from the drive signal of latch units output changes along with a polarity number.
27. device according to claim 16, further comprise a frequency judging unit, be used for according to current detection to zero crossing and the preceding once detected zero crossing frequency of judging the general AC power of input, and export its testing result to the PAM driver element, the PAM driver element comes the address of designated memory according to the frequency of judging, thereby output is stored in the sine voltage value in the assigned address.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990000281A KR100351140B1 (en) | 1999-01-08 | 1999-01-08 | Power factor correction apparatus of inverter |
| KR281/1999 | 1999-01-08 | ||
| KR281/99 | 1999-01-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1264215A CN1264215A (en) | 2000-08-23 |
| CN1290250C true CN1290250C (en) | 2006-12-13 |
Family
ID=19570853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001027891A Expired - Fee Related CN1290250C (en) | 1999-01-08 | 2000-01-08 | Power factor compensation system for motor driving inverter system |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4430169B2 (en) |
| KR (1) | KR100351140B1 (en) |
| CN (1) | CN1290250C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102474173A (en) * | 2009-07-23 | 2012-05-23 | 特里多尼克有限两合公司 | Method and circuit for correcting power factor |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7298124B2 (en) * | 2004-12-01 | 2007-11-20 | Semiconductor Components Industries, L.L.C. | PWM regulator with discontinuous mode and method therefor |
| DE102004025597B4 (en) * | 2004-05-25 | 2014-08-21 | Tridonic Gmbh & Co Kg | Power Factor Correction Method and Circuit (PFC) |
| KR101075222B1 (en) * | 2004-10-29 | 2011-10-19 | 삼성전자주식회사 | Apparatus and method of power factor correction |
| ES2735810T3 (en) * | 2004-12-15 | 2019-12-20 | Fujitsu General Ltd | Power supply device |
| EP2013963B1 (en) * | 2006-04-25 | 2012-08-01 | Philips Intellectual Property & Standards GmbH | Power inverter control device for switching point determination |
| JP5798342B2 (en) * | 2010-03-09 | 2015-10-21 | ランドリー グレイ リチャード | Power factor compensation method |
| KR101251477B1 (en) * | 2012-12-13 | 2013-04-05 | 김영준 | Energy saving alternatives for electric motors including low-cost power factor correction |
| CN103595268B (en) * | 2013-11-26 | 2017-01-25 | 中国人民解放军重庆通信学院 | Frequency converter |
| JP6265297B1 (en) * | 2016-09-30 | 2018-01-24 | ダイキン工業株式会社 | Control device for direct power converter. |
-
1999
- 1999-01-08 KR KR1019990000281A patent/KR100351140B1/en not_active IP Right Cessation
- 1999-09-17 JP JP26404499A patent/JP4430169B2/en not_active Expired - Fee Related
-
2000
- 2000-01-08 CN CNB001027891A patent/CN1290250C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102474173A (en) * | 2009-07-23 | 2012-05-23 | 特里多尼克有限两合公司 | Method and circuit for correcting power factor |
| CN102474173B (en) * | 2009-07-23 | 2015-04-01 | 特里多尼克有限两合公司 | Method and circuit for correcting power factor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000209874A (en) | 2000-07-28 |
| KR100351140B1 (en) | 2002-09-09 |
| CN1264215A (en) | 2000-08-23 |
| KR20000050417A (en) | 2000-08-05 |
| JP4430169B2 (en) | 2010-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1290250C (en) | Power factor compensation system for motor driving inverter system | |
| CN1064122C (en) | Control method and apparatus for controlling motors of air conditioner | |
| CN1056710C (en) | Electrical drive arrangement | |
| CN1035709C (en) | Voltage-type pwm converter/inverter system and process for controlling the same | |
| CN102237848B (en) | Output current distortion compensating apparatus in inverter | |
| CN101040428A (en) | Power supply circuit protecting method and apparatus for the same | |
| JP5283752B2 (en) | Motor drive device | |
| US7852032B2 (en) | AD conversion control circuit and related arts | |
| CN101183844B (en) | Motor drive apparatus and method | |
| CN1306340A (en) | Device for detecting rotor position of brushless d.c. motor | |
| JP5557660B2 (en) | Power conversion device and equipment using the same | |
| CN1018413B (en) | Pwm conversion current apparatus | |
| EP2922193A1 (en) | Power conversion apparatus and control method for power conversion apparatus | |
| US8270187B2 (en) | Electric power supply circuit with PAM waveform correction | |
| CN106533226A (en) | Neutral-point voltage balance control method of three-level converter | |
| AU2008242030B2 (en) | Electric power supply circuit | |
| CA2965299A1 (en) | Regenerative rectifier for a motor control drive | |
| CN102097958B (en) | Power supply circuit, motor drive device using the same and refrigeration device | |
| CN110535375A (en) | Motor drive and electric motor drive method | |
| CN1709010A (en) | Induction heating cooking appliance | |
| CN106655953A (en) | Electrolytic-capacitor-free motor driving system and field weakening control method and device thereof | |
| JPH0974790A (en) | Inverter apparatus | |
| CN106160588A (en) | High-precision Motor Driving System And Method Thereof | |
| CN210053343U (en) | Drive control circuit and household electrical appliance | |
| JPH10146090A (en) | Inverter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20061213 Termination date: 20100208 |