CN1290035A

CN1290035A - Method for generating contact between bit lines and performing ion implantation

Info

Publication number: CN1290035A
Application number: CN 00117612
Authority: CN
Inventors: 谢咏芬
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2000-05-24
Filing date: 2000-05-24
Publication date: 2001-04-04

Abstract

A method for ion implantation on semiconductor substrate includes such steps as forming the first surface layer on partial surface of substrate, and implanting ions into substrate through said the first surface layer. The minimal thickness of the first surface layer is 10% less than t, where t is determined by an invented equation.

Description

Form the bit line contact and carry out the method that ion injects

The application is dividing an application of No. 97110966 application proposing on April 29th, 1997.

The present invention relates to a kind of method that ion injects of on the semiconductor-based end, carrying out, relate to particularly that a kind of utilization is controlled at the configuration of surface (morphology) of intrabasement injection outline line (implantation profile) of semiconductor and the method for the formation of restriction defective.

The storage density of integrated circuit memory has a kind of trend that continues to increase, to seek the increase of memory data output on single wafer.Compared with the suitable memory capacity that on a plurality of wafers, is provided, the memory of single higher density provides memory more closely, and with regard to the angle of unit bit, its cost is also lower, roughly, the element of these higher storage density is compared with more early stage low-density wafer, the performance that has suitable precision usually or more progress greatly.All the time, the increase of integrated circuit component density has in part because of reduction such as the physical dimension of line and transistor gate, and the cause that reduces to constitute the separation distance between the structure member of integrated circuit component.The reduction of circuit structure size normally is used for satisfying the Design Rule that dwindles of making integrated circuit component.

At dynamic random access memory (Dynamic Random-Access Memories; DRAM) in, the storage of data normally utilizes among a formed capacitor array on the semiconductor substrate surface, to each electric capacity optionally charge or discharge realize.Under the most situation, the single bit of binary data is stored within the electric capacity, and the state that its electric capacity has been put behind the electricity is represented logical zero, and the charged state of electric capacity is then represented logical one.Under a given operating voltage, in the electrode separation distance that can make stably, and be applied to usually under the dielectric constant of interelectrode capacitor dielectric of charge storaging capacitor, the surface area of the electrode of memory capacitor has determined it can be stored in the amount of the electric charge in the electric capacity.The reading and write action and utilize and optionally charge storaging capacitor to be coupled on the bit lines of memory so that charge transfer is entered charge storaging capacitor, or transferred out by charge storaging capacitor and to carry out.Typically use field-effect transistor (FET, field effect transistor) and charge storaging capacitor optionally is coupled on the bit line.Bit line contact one of is normally moved in source/drain electrode of transmission FET, and charge storaging capacitor then is made into usually with another the source/drain electrode that transmits FET and contacts.Word-line signal then is supplied to the grid of FET, is connected to bit line with the electrode with charge storaging capacitor via transmission FET, so that carry out the charge transfer between charge storaging capacitor and the bit line.

Fig. 1 shows the cross-sectional view of two memory cell of existing DRAM in the production process interstage in a schematic way.DRAM memory cell among the figure is made in the P type substrate 10, and it comprises and can completely cut off the thick field oxide region of opening 12 with other contiguous memory cell.Utilization just can form a grid oxic horizon 14 with a part of heated oxide in the active element district between the field oxide region 12, and polygate electrodes 16 then is formed on the grid oxic horizon 14.Two shown gate electrodes 16 are respectively the section construction of two independent transmission FET of two memory cell among the figure among Fig. 1.Polygate electrodes 16 utilizes the deposition unadulterated polysilicon of one deck in substrate and forms, typically use low-pressure chemical vapor deposition (LPCVD, low pressure chemical vapor deposition) method deposits, again impurity is injected polysilicon, and make impurity activation, have conductivity so that make polysilicon layer become.Gate electrode then utilizes existing photoetching technique to carry out imaging again.On polygate electrodes 16, provide one deck Si oxide 18, so as in follow-up processing step the grill-protected electrode, and this oxide layer 18 also is used as etch stop layer in the follow-up etching step of being everlasting.When carrying out source/drain electrode injection technology step (back will be discussed), also provide in connection with the side wall oxide of gate electrode and construct 20 at interval.When gate electrode 16 formed, the connecting line 22 that different gate electrodes are coupled together also formed on field oxide region 12 simultaneously.Because connecting line is normally made among the same process step of gate electrode 16 simultaneously being used for forming, therefore connecting line can have structure similarly, constitute by the polysilicon lines 22 that utilizes oxide skin(coating) 24 to be covered, and have the side wall oxide spacer structure 26 that forms along connecting line 22.

Source/

drain region

28,30 and 32 through mixing is formed at the both sides of polygate electrodes 16, so that define the channel region of transmission FET.Transmission FET common source/drain region 30 as the usefulness of the bit line contact of two shown among figure memory cell.Be mainly used in the little Design Rule memory transistor in the purposes of patterns such as modern memory and logic element, can use the structure of lightly doped drain (LDD, lightly-doped drain) usually.Source/

drain region

28,30 and 32 normally makes with the technology of two steps, and the dopant with relatively low degree injects to start with earlier, and it can be aimed at automatically with polygate electrodes 16.Utilize at first deposition one deck CVD oxide on element again, then oxide skin(coating) is carried out anisotropy and eat-back, so that the substrate on source/

drain region

28,30 and 32 is come out, so that spacer oxide district 20 is formed at the both sides of gate electrode 16.The etch-back of CVD oxide skin(coating) is in the both sides of polygate electrodes 16, and the both sides of polysilicon connecting line 22, has all produced spacer oxide district 20.After spacer oxide district 20 has been formed at the both sides of polygate electrodes 16, secondary higher concentration ion injecting program just can with spacer oxide district 20 self-aligning modes under, carry out at source/

drain region

28,30 and 32, so that finish the making of source/drain region.

After the transmission FET of DRAM memory cell forms, utilize the CVD method, the silicon oxide layer 34 that has insulating properties in the textural deposition one of Fig. 1 earlier is so that form contacting of charge storaging capacitor and bit line.The structure of its formation is shown among Fig. 2.Utilization is carried out existing photoetching treatment technology to silicon oxide layer 34, can form contact hole 36, so that expose the source/

drain region

28,30 and 32 of substrate.Utilize LPCVD with reference to figure 3 this moment, and the polysilicon 38 of one deck undoped then is deposited on the surface of element, and also is deposited within the contact hole 36, and contact with source/

drain region

28,30 and 32 formation.Polysilicon layer 38 can form the part of the bottom electrode of DRAM charge storing unit storage capacitors.This layer injects with ion and mixes, and anneals.Afterwards again with photoetching technique to bottom electrode 38 compositions.A dielectric layer 40 of electric capacity, such as the double-decker of the oxide of the nitride of silicon and silicon, just can be formed on the surface of bottom electrode 38 this moment.Utilize the deposition of one deck polysilicon again, mix and imaging, just can form the top electrode 42 of electric capacity, produce structure shown among Fig. 4.

Then, utilize blanket-deposited (blanket depositing) to form an inner layer dielectric material, textural such as in Fig. 4 utilizes the CVD program atmospheric pressure under, with the one deck that gas was deposited in the TEOS source glass through doping.Utilize existing photoetching technique again, in dielectric layer 44, leave a bit line contacting window 46, so that expose common source/drain electrode contact 30.Then, normally utilize extra bit line contact ions injecting program is provided, and the metal sputtering layer of one layer or more then is provided again, perhaps utilize the CVD program, on the surface of structure sheaf 44, in the scope of the shown contact hole 46 of Fig. 5, deposit, just can form bit line contact 50.This bit line then carries out imaging again, and follow-up processing step, so that finish the making of element.

The Design Rule standard that element in the construction drawing 5 uses is if increase, just can be to many structures shown among Fig. 5, with and the technology of making produce comparatively strict requirement.Because the memory cell of size reduction is used more shallow and narrow source/drain region, by contrast so the formation of source/drain region becomes even more important.Just more need this moment to control the diffusion of injecting energy and source/drain region, so that can make undersized element.Also need in addition to keep source/drain region, so that keep the high-performance of these structures with high conductivity.And main points keeping high conductivity degree are, will avoid the formation of defect sturcture in source/drain region.

Impurity is being injected at the semiconductor-based end, and substrate is annealed so that activate the technical process of the dopant that injects, the lattice defect structure that may have multiple kenel forms.The dose concentration that employed ion injects when making many semiconductor circuit assemblies may make that the crystal silicon semiconductor substrate that ion injected is decrystallized.Substrate must be carried out annealing in process continuously, is activated so that ion is injected, and will make non-crystalline areas that crystallization again (recrystallize) takes place usually.The meeting of crystallization again of the silicon base of process ion injecting program is with extension (SPE, the generation of solid-phaseepitaxial) regrowth (regrowth) situation of solid phase.In the program of SPE regrowth, substrate is heated to a temperature under this base material fusing point.Crystal growth takes place with the form of solid-state transmission (solid state transport), and can carry out the amorphous fraction of crystallization (have through inject or without injecting) part and substrate material by substrate, the interface between the zone that is injected into.(occurs incrementally) little by little takes place in crystallization again, and the crystallization direction again of the non-crystalline areas that each is cumulative is to be determined by the crystal lattice orientation (orientation) in the crystalline region of crystallization generation again.Like this, at the crystal lattice orientation of the crystalline substrate at the interface of crystal region and non-crystalline areas, just can determine the direction of SPE regrowth.

Because the interface shape of non-crystalline areas, the SPE regrowth will might be accomplished along different lattice planes.Multiple result of study points out that the SPE regrowth that takes place along different lattice planes can cause defective in crystal.For example,, can in silicon metal substrate again, form and extend the defect sturcture of launching with the appearance of the growth leading edge (growthfront) on lattice plane corresponding to neither.Because inject and other technologies, the residual defect of other forms also may be brought in the lattice structure.For example, the appearance of grid layer and sidewall separate layer in substrate may cause compression stress on the material of its liner, particularly in follow-up heating process step.The appearance of this stress may produce the defective such as dislocation (dislocations), and may cause dislocation to amplify the phenomenon of (dislocation multiplication).

Usually, the defective of projection range defects (PRD, projected range defects) and scope tail end defective kenels such as (ERD, end of range defects) may form in the injection of substrate and tempering zone.PRD and ERD are secondary defect (secondary defects) (dislocation or line defect), and wherein PRD appears at the zone of injecting ion concentration near maximum, and ERD then appears near the amorphous-crystalizing interface place after injecting.This class defective should be that promptly, perpendicular to the regrowth of silicon face, and these defectives may comprise the dislocation loop (dislocation loops) that is imbedded in the injection region because the vertical SPE regrowth of amorphous silicon causes.The position of PRD and ERD and density are relevant with energy and concentration when injecting ion.The another kind of relevant defective form of regrowth that becomes the silicon of noncrystalline state with seeing through the ion injection is mask edge defective (MED, mask edge defects).MED is the crystallization leading edge again owing to vertical and side direction SPE regrowth, its outstanding dislocation that is caused.During the technology of tempering and crystallization again, become extra extension crystal layer because the outstanding formed dislocation of SPE regrowth leading edge is tended to pinching, these defectives then may have grown into before and by appearance are and the similar a kind of structure of crystal grain boundary (grain boundary).The defect sturcture that this extension launches, if be that main direction along electric current occurs, just can influence the conveying of electronics.This defect structure may be in the lateral edge near the injection region, at substrate surface or near substrate surface, normally another structure part in connection with substrate surface forms on crystalline substrates surface again, and may cause the problem of junction leakage (junction lenkage).

The objective of the invention is to overcome the shortcoming of above-mentioned prior art, propose a kind of ion injection method, so that caused defective is reduced to minimum in the later annealing in process of ion-implanted semiconductor substrate.

For achieving the above object, the present invention proposes the method that a kind of formation is connected to the bit line contact of source, and its step comprises: a substrate is provided, has source in it; One sagging part is provided in substrate; Via sinking partly with the source ion implantation utmost point/drain region; With formation one bit line, it contacts with source/drain regions.

The present invention provides a kind of method that ion injects of carrying out on the other hand on the semiconductor-based end, its step comprises: the substrate with a surface is provided; By removing material on this surface to define a first area; Via the first area ion is injected substrate; With temper is carried out in substrate.

Embodiments of the invention comprise and for example prevent to become the method that Si semiconductor substrate that amorphous stops forms defective when the crystallization again because of ion injects, some preferred embodiment of the present invention comprises a kind of control method of crystallization circle crystalline form shape again, so that the regrowth of SPE can mainly take place along one group of preferred direction, these execute in the example certain some a superficial layer is provided in its substrate, see through this superficial layer and can carry out the program that ion injects, the chosen degree of depth that limits ion injection substrate inside of the thickness of superficial layer, therefore, the thickness of superficial layer, configuration of surface or other specific selecting can make the interface between structural substrates and the amorphous injection zone have best shape.Inject the suitable selection of outline line, the SPE regrowth can be limited in specific better direction, row becomes may damage the possibility of the defect sturcture of performance when having lowered crystallization again.

The contact wire utilization of memory element provides the substrate fabrication with source/Lou Jishi to form in other embodiment, in substrate, be formed with sagging part, and the part of see through sinking injects, so that ion is injected in the source/drain region of substrate, so that strengthen the conductivity of bit line contact.Injection zone carries out temper again, forms the bit line that contacts with source/drain region with the depression office on substrate surface.

Embodiments of the invention will carry out exemplary detailed description with reference to the accompanying drawings, and accompanying drawing is the diagram of illustrative nature, and wherein part is not according to scale.In the accompanying drawing:

Fig. 1-5 is that a prior art DRAM is at the cross-sectional view of its each manufacturing process in the stage;

Fig. 6 shows the cross-sectional view of an ion implanted region of bit line contact;

The cross-sectional view of the engagement edge defective that the injection region of Fig. 7 displayed map 6 forms during crystallization and tempering again;

Fig. 8 is a cross-sectional view, and its demonstration has intrabasement a kind of injection outline line on general planar surface;

Fig. 9 shows the cross-sectional view of the substrate with a superficial layer that can inject for penetrating;

Figure 10 shows various sizes relevant when being injected in the substrate with penetrating a superficial layer;

Figure 11 shows the cross-sectional view that has a substrate of curved surface part according to embodiments of the invention;

Figure 12 shows the cross-sectional view that has a substrate of a curved surface and a curved surface layer according to embodiments of the invention;

Figure 13 shows the cross-sectional view that has a substrate of a general planar surface and a curved surface layer according to embodiments of the invention;

Figure 14 shows the cross-sectional view of a DRAM when the interstage of its technical process according to an embodiment of the invention;

Figure 15 is according to embodiments of the invention, comprises the cross-sectional view of a DRAM of the bit line contact of making; With

Figure 16 shows according to embodiments of the invention, the cross-sectional view of a DRAM who penetrates when having a curved surface for injection when the interstage of its technical process.

At first, the step that three kinds of ions inject can be accepted in typical bit line contact zone 30 as shown in Figure 5 in typical production process, and one to three kind of annealing steps.Usually it is necessary having a kind of temper step at least, is used for infusion is given the electricity activation, and recovers because caused some lattice damage of ion implantation step at least.High density, the typical implantation concentration of shallow junction element may cause a part or whole part decrystallized of contact zone.In this case, can carry out the annealing in process program, so that make non-crystallization region crystallization again.Crystallization is undertaken by solid phase epitaxial regrowth (SPE) again, and the conversion of solid phase has wherein taken place, and by this conversion, non-crystalline areas is via at the interface atom transmission and tissue again between amorphous and the crystal region, and is converted into a kind of crystal structure.Crystallization can be carried out towards the direction on the border that is approximately perpendicular to non-crystalline areas again.Like this, the orientation in each territory, progressive recrystallization zone is to determine according to the orientation that crystallization again begins the crystal region that carries out.Its result, between the crystalline portion of substrate and amorphous fraction at the interface the orientation of crystalline substrates has just determined crystallization again to carry out the crystallization direction of being followed.

The crystallization again of amorphous silicon region may cause the formation of number of drawbacks.Projection range defects (PRD) and scope tail end defective (ERD) are at the SPE of amorphous silicon again during the crystallization, formed defective in the injection zone of substrate (normally dislocation loop).PRD appears at the zone of injecting ion concentration near maximum, and ERD then appears near the amorphous-crystalizing interface place after injecting.This class defective is because the vertical SPE regrowth of amorphous silicon causes.The position of PRD and ERD and density are relevant with energy and concentration when injecting ion.The another kind of relevant defective form of regrowth that becomes the silicon of noncrystalline state with seeing through the ion injection is mask edge defective (MED).The MED defective appears at the corner near the territory, recrystallization zone usually, below mask edge, or near the mask edge place.During the crystallization again of non-crystalline areas, the formation of MED is decided with the direction of lattice regrowth.On different lattice direction, the speed of SPE regrowth is different, and the formation that it is believed that MED is to be caused by the outstanding of the crystallization leading edge again of vertical and side direction SPE regrowth.

Be presented among Fig. 6 and 7 in the bit line contact zone of injection and annealing in process, it is to have a utilization such as photoetching technique (diagram person) or directly carrying out in the substrate 110 of particle beams injection technique and the injection zone that defines that the situation that the mask edge defective forms, its intermediate ion are injected.The program of injecting is normally perpendicular to substrate 110 surfaces, carries out towards direction 112, and it has formed injection and amorphous area 114.As shown among Fig. 6, the shape of injection region is similar to a kind of Gaussian Profile (Gaussian distribution), and its maximum implantation concentration appears in the broadest part in zone 114.During annealing in process, the crystallization meeting is owing to solid phase epitaxy (SPE) regrowth of carrying out along interface between the crystalline portion of substrate and the non-crystalline areas takes place again.Crystallization takes place according to level again, and the crystallization direction again of its each layer is determined by the orientation of the crystal region that crystallization again takes place.Like this, the direction of crystal growth is just decided by the orientation of crystal region at the interface.

As shown in Figure 7, crystallization can take place on many directions again, comprise vertically along [001] direction, and laterally along [110] direction.Crystallization beginning at the interface between intrabasement crystal region and crystal region normally again, and take place towards different directions with different speed.When the crystal leading edge towards the different directions growth crossed one another, defective can generate, and the junction of fixation (pinned) between the leading edge of crystal growth, as arrow among Fig. 7 113 and 115 positions that indicated.When the growth of crystal is advanced through amorphous area; defective can accumulate; and during the crystallization again crystal growth leading edge infall the plane and fixation gets off, in substrate, caused to extend the defect structure 116 that launches, it can extend the edge near surface texture 111 usually.

Utilize the degree of depth and the shape of non-crystalline areas in the control substrate, the formation of defective 116 as shown in Figure 7 just can reduce.Injecting with the suitable design of crystallization procedure again to provide a kind of technical process, and it can help the particular growth direction in the crystallization procedure again.In certain embodiments, the direction that needs regrowth mainly towards, perhaps be defined in and comprise [100], [111], [211], the direction of [311] and [511] etc.[100] and the angle between other directions can calculate or measure.With regard to a cubic crystal, the angle between [100] and [111] direction approximately is 54.7 degree.In fact find that with regard to the substrate that a slice is oriented to [100] direction, the angle between the regrowth direction greatly about 54.7 degree or more hour just can prevent the generation of edge defect.[100] direction and [211], [311], and the angle between the directions such as [511] is all less than 54.7 degree, wherein the angle between [100] and [211] direction is about 35.3 degree, [100] and the angle between [311] direction be about 25.2 degree, the angle between [100] and [511] direction then is about 15.8 and spends.The present invention develops kinds of processes, can guarantee that crystallization again forms the brilliant figure directions that are less than or equal to 54.7 degree between the direction of crystallization and [100] direction again along its each and carries out.

In certain embodiments, can be formed on the surface of substrate, make the injection region be positioned at superficial layer partly, be positioned at substrate partly with polysilicon or such as a superficial layer of a kind of material of megohmite insulants such as Si oxide.This layer preferably has roughly homogeneous thickness.Utilize the thickness of control table surface layer, the shape of intrabasement recrystallization zone just can be controlled.Main points of the present invention are to provide a kind of method, its can the decision table surface layer minimum thickness, so that guarantee that the regrowth leading edge of crystal can be according to user's selection, and to avoid forming the also little angle of regrowth interplanar maximum angle of extending the defect sturcture of opening and intersect than according with.This method describes with reference to accompanying drawing shown among the figure 8 in the back.Ion perpendicular to the substrate surface 122 of general planar on direction 124 injects outline line 120, can a Gaussian Profile be described, as shown in Figure 8.Ion injects outline line 120 and extends into substrate along direction 124, and laterally scatters to Breadth Maximum at the intrabasement intermediate depth place that is injected into.Inject the position of the spike concentration of ion and stretch along a line 126-126 ', it roughly approaches or is in the Breadth Maximum part of outline line 120.The outline line of this two-dimensional space can utilize a projection scope Rp, along a projection standard deviation Δ Rp of directions X, and along a projection standard deviation Δ Y of Y direction and describe its characteristic.These are apart from the characteristic of representing the ion injecting program, and can be subjected to specific ion, substrate, and the mobility scale of injecting energy of ions and ion energy influences.The outline line that it is believed that amorphous area has the general shape identical with the implantation concentration characteristic curve, and wherein the size of amorphous area is determined by a transition energy.

In order to control amorphous area, so that when crystallization again, the regrowth meeting takes place towards preventing the direction that edge defect forms, the program of injecting can penetrate as shown in Figure 9, the superficial layer 128 of uniform thickness and carrying out in fact, the injection distribution 130 of its part is positioned within the superficial layer 128, and the injection distribution 130 of a part then is positioned at substrate 132.Superficial layer can adopt multiple material, such as, polysilicon is such as other conductors of refractory metal or metal silicide, the constituent of Si oxide and various glass etc.When the present invention was applied to the bit line contact zone, preferably superficial layer was the conductor such as polysilicon, such as titanium, and tungsten, the refractory metal of tantalum, or the metal silicide of refractory metal etc.Utilize this mode, before forming remaining bit line contact, just need not remove scalping.The present invention has observed with regard to some embodiment, and the intersection between the regrowth direction is 54.7 degree or more hour, the formation situation of edge defect can be reduced to minimum.In order to determine needed surface layer thickness t, the spatial distribution of injecting outline line is assumed that it approximately is a kind of oval-shaped configuration.When θ=54.7 are spent, the oval formed right-angled triangle of radius, the edge of the end of superficial layer 128 and injection distribution 130 can be used to determine to be formed at the thickness t of the superficial layer 128 in the substrate 132.As shown in Figure 10, the radius d of ellipse utilized the following formula decision when θ=54.7 were spent:

d=[(ΔY?sinθ) ²+(ΔRp?cosθ) ²] ^0．5???????????????????(1)

Wherein Δ Y is the projection standard deviation along the y direction, and Δ Rp then is the projection standard deviation along the x direction.In addition:

t-Rp=dcosθ??????????????????????????????????????????(2)

Wherein Rp is for injecting the projection scope of the degree of depth, separates following formula again in the hope of thickness t:

t=dcosθ+Rp。(3)

In following formula, radius d substitution can be got:

t=Rp+cosθ[[(ΔY?sinθ) ²+(ΔRp?cosθ) ²] ^0．5]。(4)

When θ=54.7 are spent:

t=Rp+0．578[[(ΔY) ²(0．666)+(ΔRp) ²(0．334)] ^0．5]。(5)

Rp, Δ Y and Δ Rp employed energy when injecting is decided.The results are shown in Table 1 for some element.With regard to the number purpose ion samples with various ion implantation energies, minimal surface layer thickness t calculates, and its value is listed in the table 1.

Table 1

Energy	(KeV)	????20	????40	????60	????80
Energy	(KeV)	????20	????40	????60	????80	????As	??Rp(A) ?ΔRp ?ΔY ??t	????150 ????56 ????41 ????177	????262 ????96 ????69 ????308	????368 ????133 ????96 ????431	????473 ????169 ????121 ????553
????B	??Rp ??ΔRp ??ΔY ???t	????658 ????270 ????290 ???822	????1277 ????423 ????483 ????1545	????1847 ????526 ????638 ????2195	????2380 ????605 ????761 ????2792	????As	??Rp(A) ?ΔRp ?ΔY ??t	????150 ????56 ????41 ????177	????262 ????96 ????69 ????308	????368 ????133 ????96 ????431	????473 ????169 ????121 ????553
????B	??Rp ??ΔRp ??ΔY ???t	????658 ????270 ????290 ???822	????1277 ????423 ????483 ????1545	????1847 ????526 ????638 ????2195	????2380 ????605 ????761 ????2792	????P	???Rp ??ΔRp ??ΔY ???t	????253 ????114 ????94 ????311	????488 ????201 ????175 ????594	????729 ????288 ????249 ????881	????974 ????367 ????323 ????1170
????Sb	????Rp ???ΔRp ???ΔY ????t	????130 ????39 ????30 ????149	????220 ????68 ????49 ????252	????299 ????92 ????66 ????343	????375 ????115 ????82 ????430	????P	???Rp ??ΔRp ??ΔY ???t	????253 ????114 ????94 ????311	????488 ????201 ????175 ????594	????729 ????288 ????249 ????881	????974 ????367 ????323 ????1170

Listed in the table 1 20,40,60 with the 80KeV energy under with As, B is when P and Sb ion inject a silicon base, with dust (, the angstrom) Rp of the surface layer thickness t of Ji Suaning, published values and the evaluation of Δ Y and Δ Rp.

Though be appreciated that listed thickness t is to extend the required minimum value of launching of defect structure for avoiding forming in the table 1, t is a kind of optimum thickness value often.Because the variation of normal procedure, the time regular meeting change of surface layer thickness appears.Under most of situation, surface layer thickness t has about 10% or lower mobility scale.With regard to a given injection energy, when the thickness t of superficial layer becomes big, be injected into intrabasement accumulated dose and become less, and the conductivity of contact zone is had less influence.Therefore, if if possible, the thickness of superficial layer need be maintained on the fractional value usually, though with regard to the element function of integral body, this is not the factor of a sensitivity.

As shown in table 1, for example, with regard to the example that use As injects under the energy of 20KeV, the thickness of superficial layer 128 should be at least 177 dusts among Figure 10.When used thickness was the superficial layer of at least 177 dusts, because the angle between [100] direction and the crystallization regrowth direction is 54.7 degree or littler, the formation situation of mask edge defective just can reduce.The shape of amorphous area that its result forms can be controlled the direction of regrowth, so that because the reciprocation between vertical and the side direction SPE regrowth forms, comprise that the situation of MED defective can be reduced to minimum.Other embodiment of the present invention can provide different θ numerical value, such as, decide with the orientation and the crystal structure of substrate.

Embodiments of the invention can use the configuration of surface of multiple substrate surface and superficial layer.For example, a kind of substrate can be when initial be made of the part of sinking on its surface.In addition, the substrate with general planar surface also can be removed the part material so that form a sagging part in processing step.For example, shown as Figure 11, a substrate 130 can have sagging part 136, so that obtain an injection zone 134 at a similar interface of its shape and sagging part 136.Be shown in the injection zone 134 among Figure 11 and since again during the crystallization geometry of regrowth leading edge so, can cause some advantage.The amorphous injection region 134 of substrate 130 and the angle between the crystal region can be utilized control the sink curvature of part 136 and change.Utilize control curvature, again during the crystallization vertically and the reciprocation between the side direction SPE regrowth minimize.Some embodiment of the present invention has a sagging part under the original flat surface of the substrate of extending, and this part of sinking is defined by intilted sidewall region 137 and more smooth middle section 139, as shown in figure 11.

Sagging part 136 in the substrate 130 is passable, and for example, under the established situation of bit line contacting window of the existing source/drain region of transmitting FET, utilization is carried out an isotropic etch step and formed.In some preferred embodiment, the part of sinking is along the shape that can be depression on the minimum part on its length direction, and along can being crooked fully shape on its length direction, the zone that perhaps can have general planar in central authorities, but then crooked at two ends.According to employed etching solution, have the surface of concave shape in fact, then more smooth or more crooked outward appearance can be arranged.Formed sagging part can incision (undercut) extend the sidewall that bit line contacts the insulating barrier of top.In certain embodiments, a target is a surface angle of avoiding precipitous.After etching step was finished, the program of injection just can be carried out, so that form injection region 134.Injection region 134 has the interface that forms with the remainder of substrate, and it is similar to curved surface 136 on geometrical configuration, and can cause the fixation reciprocation of minimum defective between side direction and vertical solid phase epitaxial regrowth zone.Its result, the situation that defective forms has reduced.

For further shape and the degree of depth of control one injection region, before injection, a superficial layer 146 can fixation in one of substrate 140 roughly on the top of sunk surface 142, situation as shown in figure 12.If according to other mode, a kind of element similar to Fig. 7 can have a substrate surface 152 of general planar, and then there is the roughly superficial layer 156 of concave shape of tool its top, as shown in Figure 13.This curved surface layer 156 can utilize, such as, a superficial layer of deposition general planar in substrate, and re-use isotropic etching liquid a part of etching of superficial layer is removed.Follow-up injecting program just can cause an injection zone 154 in substrate 150, its interface between amorphous injection region 154 and crystalline substrates 150 is with the mode bending similar to the curvature of superficial layer 156.

Figure 14 shows a DRAM embodiment who makes according to embodiments of the invention.DRAM unit shown among the figure makes in a P type substrate 50, and comprises field oxide region 52, so that open with the memory cell of adjacency is isolated.56 of polygate electrodes are formed on the gate oxide layers 54.Lightly doped source/

drain region

68,70 and 72 is formed at the both sides of polygate electrodes 56, to define the channel region of transmission FET.Common source/drain region 70 of transmission FET is as the bit line contact of two transmission FET shown in the figure.Source/

drain region

68,70 and 72 through mixing can make in the technical process of one two step again, and at first the dopant with relatively low degree injects beginning, and it can be aimed at automatically with polygate electrodes 56.Then utilize at first deposition one deck CVD oxide on element again, then again oxide skin(coating) is carried out anisotropy and eat-back,, be adjacent to the gate electrode place so that sidewall oxide spacer district 64 is formed on so that the substrate on source/

drain region

68,70 and 72 is come out.Follow secondary higher concentration ion injecting program can with spacer oxide district 64 self-aligning modes under, carry out at source/

drain region

68,70 and 72.When gate electrode 56 formed, the connecting line 60 that different gate electrodes are coupled together also formed on field oxide region 52 simultaneously.Similarly, when side wall oxide was constructed 64 formation at interval, side wall oxide was constructed 66 at interval and is also formed along connecting line 60.

After transmission FET forms, just can form storage capacitors and contact with bit line.According to embodiments of the invention, the technology such as photoetching and anisotropic etching is used on source/surface, drain region, can open a bit line contacting window through element, expose source/drain region 70 so that see through contact hole 80.Then a superficial layer 82 can be deposited on the surface of source/drain region 70, and sees through the step that this layer once injects, so that strengthen the conductivity of bit line contact further.The thickness of superficial layer can be relevant with the degree of desired restriction regrowth direction, and can utilize aforesaid formula (1)-(5) to decide one-tenth-value thickness 1/10.Carry out one to multiple time annealing in process step afterwards again, so that the ion that activation is injected, and make non-crystalline areas crystallization again.As the superficial layer 82 that insulating barrier uses, before bit line contact 84 forms in contact hole 80, preferably remove earlier.Material in conductivity is used for forming among other embodiment on surface 82, preferably this material should be retained on its original position, so that lower the number of times of processing step.Bit line contact 84 (seeing Figure 15) can or be formed in the contact hole 80 with CVD method deposition and the metal on the part surface of element constitutes by the one layer or more sputter.

In another embodiment, can form a kind of DRAM structure similar to Figure 14, its surface 86 has the curved surface form, sees through the program that this surface can be injected, so that the shape of control injection region.This structure can utilize and at first use mask, and utilizes anisotropic etching solution that the part corrosion of contact hole 80 is formed.After carrying out the anisotropic etching step, the bottom of contact hole 80 just can have more smooth surface relatively.Then just can carry out another time etching step, use isotropic etchant, so that form curved surface 86, as shown in figure 16 such as the plasma that obtains by SF6.Utilize through curved surface 86 and inject, the injection region can so that after carrying out temper, reach the direction of minimum degree and crystallization again takes place along the formation that can make edge defect as desirably having similar curved boundaries.

DRAM among Figure 14 can have a superficial layer, sees through the program that this layer can inject, and is similar to superficial layer 146 shown among Figure 12.This curved surface layer can utilize, for example, and to carrying out and describe similar etching in the surface at Figure 16, and deposited surface layer and obtaining on curved surface again.The needed minimum thickness of this superficial layer can utilize aforementioned formula (1)-(5) and determine.Similarly, the substrate of DRAM also can have the surface of general planar, and has one deck curved surface layer similar to the superficial layer 156 among Figure 13.Should be pointed out that the embodiment that carries out various processing steps, it comprises, for example, the needed multiple etching step of substrate surface and superficial layer is because its additional complexity and its need the more time, so be not best mode.

Though the present invention is directed to the explanation of the method that DRAM structure among Figure 14 to 16 carried out preventing that defective from forming, method as described herein still can be applicable to other structure and processing step.For example; embodiments of the invention also can be applied to the injecting program of mask or maskless (injection of direct ion bundle); because the injection region that utilizes the maskless injecting program to be caused, the configuration of surface that it obtained can be identical with the configuration of surface of utilizing the existing injection region that injecting program obtained of having used mask.In addition, though the present invention is described with reference to some preferred embodiment, should be appreciated that scope of the present invention is not limited on these certain embodiments.On the contrary, category of the present invention should be limited by appended claim.

Claims

1. a formation is connected to the method for the bit line contact of source, and its step comprises:

One substrate is provided, has source in it;

One sagging part is provided in substrate;

Via sinking partly with the source ion implantation utmost point/drain region; With

Form a bit line, it contacts with source/drain regions.

2. the method for claim 1, its step also are included in ion divided via depression implements temper after injecting Yuan Ji/Lou Jishi.

3. the method for claim 1, wherein the Surface Vertical of substrate is in [100] lattice direction.

4. the method for claim 1, the part utilization of wherein sinking is carried out etching at least a portion of substrate with an isotropic etching Huaihe River and is formed.

5. the method for claim 1, its step also comprises:

On dividing, the depression of substrate provides a superficial layer; With

Via superficial layer with the source ion implantation utmost point/drain region.

6. method as claimed in claim 5, it also comprises willing surface layer and source/drain regions to be carried out the step of temper afterwards by removing in the substrate again.

7. method as claimed in claim 5, it also comprises source/drain regions is carried out temper, afterwards again with superficial layer by the step of removing in the substrate.

8. one kind is carried out the method that ion injects on the semiconductor-based end, and its step comprises:

Substrate with a surface is provided;

By removing material on this surface to define a first area;

Via the first area ion is injected substrate; With

Temper is carried out in substrate.

9. method as claimed in claim 8, wherein the first area has the shape of depression.

10. method as claimed in claim 8 is comprised with the step that defines a first area by removal material on this surface wherein forming a sagging part that it has the core between sidewall sections and the sidewall sections.

11. method as claimed in claim 10 comprises that also the additional step that forms the part of sinking is so that the shape of this core is more smooth than the shape of sidewall sections.

12. method as claimed in claim 8 also is included in the additional step that a superficial layer is provided in the first area, this superficial layer has homogeneous thickness in the scope of first area.

13. method as claimed in claim 12, wherein the thickness of superficial layer is determined by the following step:

Selecting a required angle θ again between the crystallization direction;

The decision ion flows into the projection scope of the distance R p of substrate;

Decision is along the projection standard deviation Δ Rp of a first axle direction;

Decision is along the projection standard deviation Δ Y of monic second axis direction; With

Separate the thickness t of following equation in the hope of superficial layer:

t=Rp+cosθ[[(ΔY?sinθ) ²+(ΔRp?cosθ) ²] ^0．5]

14. method as claimed in claim 8, it also comprises the following steps:

One superficial layer was provided on the first area earlier before via the first area ion being injected substrate; With

Via superficial layer and first area ion is injected in the substrate.

15. method as claimed in claim 14, it also comprises material by the step of removing in the superficial layer.