CN1286147C - Multi-layer structure with dislocation defect retardation - Google Patents
Multi-layer structure with dislocation defect retardation Download PDFInfo
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- CN1286147C CN1286147C CN02131671.6A CN02131671A CN1286147C CN 1286147 C CN1286147 C CN 1286147C CN 02131671 A CN02131671 A CN 02131671A CN 1286147 C CN1286147 C CN 1286147C
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- silicon
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- germanide layer
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Abstract
The present invention provides a multilayer structure with dislocation defect retardation. According to the structure of the present invention, firstly, a multilayer structure similar to a sandwich is formed on a silicon base plate; the multilayer structure is formed on the silicon base plate by the alternation of a silicon-germanium layer and a silicon layer; the dislocation is limited in an area by the similar sandwich structure; subsequently, a thick silicon-germanium layer and a thin silicon layer are formed on the similar sandwich structure. Because the dislocation defect is limited in the multilayer structure similar to a sandwich, the dislocation defect of the thin silicon layer structure can be largely reduced.
Description
Invention field
The invention relates to a kind of on the silicon substrate wafer, the silicon layer structure of the wide lattice constant of building crystal to grow tool, particularly relevant for a kind of on the wafer of silicon substrate, the low dislocation defective of building crystal to grow one tool and have the silicon layer structure of wide lattice constant.
Background of invention
Since first integrated circuit was at first invented in nineteen sixty in Christian era, component count during semiconductor is made on the one chip, promptly grow up fast, along with the semiconductor fabrication of present stage has marched toward great scale integrated circuit (ultra large scale integration with astonishing speed; ULSI) even the more highdensity epoch, the component count on the one chip also by in the past thousands of assemblies, increases to millions of assemblies, even can reach and make the tens million of or density of more a plurality of assemblies on the one chip.Assembly on the integrated circuit such as electric capacity, transistor, and conductor online etc., must cooperate the increase of density and dwindle, along with the reduction of each assembly usable floor area, its challenge and degree of difficulty greatly increase.Along with one of the challenge of semiconductor subassembly integration after increasing, promptly be to increase the actively service speed of lifting subassembly further behind the degree of assembly as the back.
Because the migration rate (mobility) of transistorized operating current size and electronics and to apply voltage relevant, so the practice traditionally promptly is to improve towards this two direction.But use to increase when applying voltage method and improving the transistor service speed, tend to follow the increase of consumed power.Therefore the another kind of method of normal use is the migration rate of managing to increase electronics.
Not limiting under the spirit of the present invention, below is example with a mos field effect transistor (MOSFET), introduces the problem that background of the present invention and tradition are met with in making.
Generally speaking, under certain applying bias, the operating current size of MOS transistor can be proportional to the migration rate of electronics, yet the migration rate of electronics is relevant with the essence of material, therefore how to increase electron transfer rate under same material essence and promptly becomes engineer's matter of utmost importance to be solved.Traditional practice is, be used in building crystal to grow one deck silicon germanide layer on the silicon substrate, growth one deck thin silicone layer on silicon germanide layer again, the main purpose of this kind practice is to utilize the lattice of silicon germanide layer broad, the lattice of thin silicone layer is drawn back, with the channel region of this layer,, promote service speed indirectly then to increase the migration rate of electronics as MOS transistor.
See also shown in Figure 1 because the lattice parameter (a of silicon
Si) less than the lattice parameter (a of germanium
Ge) about 4.2%, therefore, on silicon substrate at first building crystal to grow one deck silicon germanide layer as resilient coating, the main purpose of this step, be on the pure silicon substrate, utilize building crystal to grow one deck silicon germanide layer, allow grow up thin silicone layer lattice on this silicon germanide layer utilize this step with increasing, and for fear of because of the rapid variation of lattice, and cause dislocation to increase, therefore build the silicon germanide layer of crystalline substance, its germanium composition is that gradually the step increases to the composition size of being scheduled to along with brilliant thickness of heap of stone, yet in facing on the face of connecing of silicon layer and silicon germanide layer, it can bear the number that the silicon germanide layer thickness that dislocation does not take place can depend upon the germanium composition, that is it should be certain.See also shown in Figure 2, it is presented on the silicon substrate, building crystal to grow one silicon germanide layer, when the brilliant SiGe thickness of build is still in critical range, it faces the face of connecing still can keep the kenel of connecting airtight, that is does not have dislocation to produce, yet if the SiGe thickness that institute build crystalline substance during above critical range, see also shown in Figure 3ly, it faces the face of connecing will produce dislocation.
Suppose that its germanium composition of being scheduled to of employed silicon germanide layer is 20%, that is its silicon crystal lattice width of desiring to draw back is to equal Si
0.8Ge
0.2Width, wherein the germanium composition is many more, the lattice width can be big more, right germanium composition is many more, required building crystal to grow silicon germanide layer thickness needs big more.The practice traditionally is, consult Fig. 4, at first on silicon substrate building crystal to grow one layer thickness about the silicon germanide layer of 2 μ m to 3 μ m as resilient coating, that is allow the face of connecing that faces of silicon substrate and SiGe bed thickness, can not produce too much dislocation because unexpected lattice parameter difference is excessive, wherein the germanium composition of building crystal to grow is progressive to increase to 20% by 0.When the germanium composition reaches 20%, can allow Si
0.8Ge
0.2Silicon germanide layer continue to become to be about 1 μ m, it is to produce not have a silicon germanide layer of dislocation defects that this step mainly acts on, follow growth one deck thin silicone layer on silicon germanide layer again, about 200 dusts of its thickness, usually this layer thickness will can not produce under the critical thickness of dislocation, and so can allow brilliant thin silicone layer thereon of heap of stone neither have a dislocation has the lattice parameter of broad again.
Right traditional structure that the practice produced, still can cause the too much shortcoming of dislocation defects to exist, mainly be because when carrying out the growth of resilient coating silicon germanide layer, because the thickness of this layer has surpassed critical thickness usually, germanium composition with 20% is an example, usually only below 0.4 μ m, therefore traditional practice can produce a large amount of dislocation defects to its critical thickness that does not produce dislocation in the buffering silicon germanide layer.
Summary of the invention
The present invention proposes a kind of sandwich construction that can reduce dislocation defects on silicon substrate, comprises at least: a silicon layer is formed on this silicon substrate; One silicon kind layer is formed on this silicon substrate; One sandwich construction is formed on this silicon kind layer, and this sandwich construction is to replace storehouse by silicon germanide layer and silicon layer to form, and wherein the bottom of this sandwich construction is a silicon germanide layer, and top layer is a silicon layer; One first silicon germanide layer is formed on this sandwich construction, as a stress release layer; And one thin silicone layer be formed on this first silicon germanide layer.Wherein this first silicon germanide layer thickness is between 1000 dust to 50000 dusts.Wherein the acceptable growth thickness of this thin silicone layer needs less than its critical thickness.Wherein its silicon germanide layer and silicon layer replace the storehouse number of times and are at least twice in this sandwich construction.Silicon germanide layer thickness in the wherein above-mentioned sandwich construction is all less than its critical thickness.Silicon layer thickness in the wherein above-mentioned sandwich construction is all less than its critical thickness.
A kind of sandwich construction that reduces dislocation defects that the present invention proposes comprises: a silicon substrate at least; First silicon germanide layer is formed on this silicon substrate, and wherein this first silicon germanide layer thickness is less than its critical thickness; First silicon layer is formed on this first silicon germanide layer, and wherein this first silicon layer thickness is less than its critical thickness; Second silicon germanide layer is formed on this first silicon layer, and wherein this second silicon germanide layer thickness is less than its critical thickness; Second silicon layer is formed on this second silicon germanide layer, and wherein this second silicon layer thickness is less than its critical thickness; The 3rd silicon germanide layer is formed on this second silicon germanide layer; And one thin silicone layer be formed on the 3rd silicon germanide layer, wherein the acceptable growth thickness of this thin silicone layer needs less than its critical thickness.Wherein the 3rd silicon germanide layer thickness is between 1000 dust to 50000 dusts.
Because the unmatched relation of lattice, cause the known technology can't be properly, growth one silicon germanide layer on Silicon Wafer, allow the thin silicone layer of growing up thereon amplify spacing of lattice, therefore the present invention proposes a kind of new building crystal to grow condition, in order to the issuable too much dislocation defects of classical production process, is confined in a certain epitaxial layer, and be unlikely the defect source that becomes follow-up epitaxial layer, and can reduce the desired thickness of resilient coating.
In the manufacturing of silicon substrate, because the crystalline substance heterogeneous of heap of stone between silicon germanide layer and the silicon substrate may cause the lattice dislocation, and the dislocation of above-mentioned lattice also is to cause one of the major reason of defective in the chip, therefore according to preferred embodiment of the present invention, a kind of sandwich construction that reduces dislocation defects is proposed, at first on silicon substrate, form silicon germanide layer structure and silicon structure in regular turn, wherein the thickness of this silicon germanide layer structure and silicon structure all need be lower than its critical thickness, and so-called critical thickness promptly is that it faces the face of connecing and does not produce the receptible maximum ga(u)ge of dislocation in heterogeneous crystalline substance of heap of stone, then in regular turn on silicon structure, the brilliant silicon germanide layer structure that forms of heap of stone once more respectively, silicon structure, silicon germanide layer structure and silicon structure, form sandwich construction, and the thickness of whole sandwich construction is from 300 dust to 1 μ m.Utilize sandwich construction of the present invention, dislocation defects can be limited in the simple layer.In building crystal to grow one deck silicon germanide layer structure thereon, wherein this silicon germanide layer structural thickness can be between 1000 dusts to 5 micron (μ m) at last.Then, building crystal to grow one layer thickness is approximately from the thin silicone layer of 100 dust to 500 dusts thereon again, and this layer thickness will can not produce under the critical thickness of dislocation usually.
Structure of the present invention can be as shown in the formula described:
Substrate+{ Si
0.75Ge
0.25(100 dust)+Si (150 dust) } 3periods+Si
0.75Ge
0.25(6000 dust)+thin silicone layer (200 dust)
But sandwich construction of the present invention can be shown in down by a general formula:
Substrate+{ Si
1-xGe
x(＜critical thickness 〉)+Si (＜critical thickness) } n periods (n 〉=2)+Si
1-xGe
x(1000 dust to 50000 dust)+thin silicone layer (＜critical thickness 〉)
The accompanying drawing simple declaration
Follow-up explanation is cooperated following accompanying drawing, can have more clearly for feature of the present invention and understand, wherein:
Fig. 1 is a comparison diagram for the pass of the atomic lattice constant of silicon materials and germanium material;
Fig. 2 is building crystal to grow one silicon germanide layer on a silicon substrate, and when the brilliant SiGe thickness of build was in critical range, it faced the schematic diagram between the face of connecing;
Fig. 3 is building crystal to grow one silicon germanide layer on a silicon substrate, when the brilliant SiGe thickness of build exceeds critical range, its face between the face of connecing schematic diagram;
Fig. 4 is for traditionally on silicon substrate during the building crystal to grow silicon germanide layer, employed crystal bar spare of heap of stone;
Fig. 5 is the silicon germanide layer of preferred embodiment according to the present invention building crystal to grow multilayer on silicon substrate and the wafer profile after the silicon layer; And
Fig. 6 by according to preferred embodiment of the present invention in having formed sandwich construction of the present invention in facing the issuable dislocation defects schematic diagram of the face of connecing.
Summary of the invention
Under the situation that does not limit spirit of the present invention and range of application, below promptly with an embodiment, introduce enforcement of the present invention; Be familiar with this those skilled in the art, after understanding spirit of the present invention, but when adopting said method in the silicon layer of the low dislocation defective of various building crystal to grow.Utilize structure of the present invention, during the building crystal to grow of the silicon germanide layer on carrying out silicon substrate, and unlike as the conventional art, be to adopt gradual growth and the structure that produces simple layer, the present invention adopts multilayered structure, utilize structure of the present invention dislocation defects can be confined to appoint two-layer in, and unlike as traditional single layer structure, dislocation defects can up extend because of gradual change.Application of the present invention is as the embodiment that is not limited only to the following stated.
Semi-conducting material is seemingly perfect with its appearance of perusal; Reality not so, semiconductor crystal contains many defectives, these defectives can be categorized as point defect, line defect and planar defect.These defectives have very significant effects to the character of semi-conducting material.Wherein line defect generally is commonly referred to as " dislocation " (dislocation).The generation of dislocation is main with when building crystal to grow, different crystal lattice difference produces stress and causes distortion relevant, that is deflection is bigger, dislocation also just the more, and dislocation is the one dimension defective, in crystalline material, return and cause lattice to turn round, and this line promptly is called dislocation line (Disclocation Line) along a line generation song.
In the manufacturing of silicon substrate, because the crystalline substance heterogeneous of heap of stone between silicon germanide layer and the silicon substrate may cause the lattice dislocation, and the dislocation of above-mentioned lattice also is to cause one of the major reason of defective in the chip, so select just to become very important in order to the material as resilient coating.Germanium (Ge) is utilized to as its material in the structure that a preferred embodiment of the present invention is proposed.The lattice constant of germanium (Ge) is 5.64 dusts (angstroms), and the lattice constant of silicon then is about 5.43 dusts, so the lattice dislocation is approximately at 4 two (4.2%) of percentage.Therefore a preferred embodiment of the present invention is how the resilient coating that SiGe constituted to be incorporated on the chip of silicon substrate, to minimize the problem of dislocation defective.
Because in the structure that a preferred embodiment of the present invention is proposed, avoided lattice dislocation, that is the rolling up of dislocation defects, and therefore the yield of the integrated circuit of manufacturing (chip) also promotes.Structure proposed by the invention can be integrated silicon germanide layer thereon, and reduces the dislocation defects that is produced, and therefore can utilize structure of the present invention, become to grow low defective thereon, and the thin silicone layer of tool broad spacing of lattice.According to a preferred embodiment of the present invention, this thin silicone layer can be used as the channel region of MOS transistor, to promote the service speed of MOS transistor.
According to the structure that a preferred embodiment of the present invention is proposed, its first step is to form a silicon kind layer on substrate 30, and then forming one deck silicon germanide layer structure 32 thereon, wherein according to this preferred embodiment, this silicon germanide layer structure 32 is by Si
0.75Ge
0.25Constitute, and its thickness is about 100 dusts, but it should be noted that, the proportion of composing of this silicon germanide layer 32 can the change according to lattice size between between desired lattice, because the lattice constant of germanium (Ge) is 5.64 dusts (angstroms), the lattice constant of silicon then is about 5.43 dusts, and lattice misplaces and is approximately at 4 two (4.2%) of percentage each other, so silicon germanide layer structure 32 its lattice constants can be shown below:
Si
1-xGe
xThe lattice constant size=(1+0.042X) * (the lattice constant size of Si)
Therefore the germanium that institute's desire adds in the silicon germanide layer 32 becomes component, can obtain according to desired lattice constant size according to following formula, on the other hand, the thickness that this silicon germanide layer 32 is grown up, need less than critical thickness, and so-called critical thickness promptly is in the facing on the face of connecing of substrate 30 and silicon germanide layer structure 32, and it can bear in the maximum ga(u)ge that faces the silicon germanide layer structure 32 that dislocation does not take place on the face of connecing.
Then on this silicon germanide layer structure 32, building crystal to grow one silicon structure 34, wherein according to this preferred embodiment, the thickness of this silicon structure 34 is about 150 dusts, but it should be noted that the thickness that this silicon structure 34 is grown up, and is not limited to 150 dusts, as long as the thickness of being grown up is less than critical thickness, and so-called critical thickness promptly is in the facing on the face of connecing of silicon germanide layer structure 32 and silicon structure 34, and it can bear in the maximum ga(u)ge that faces the silicon structure 34 that dislocation does not take place on the face of connecing.
Then complying with above-mentioned described preferred embodiment condition of the present invention, in regular turn on silicon structure 34, brilliant silicon germanide layer structure 36, silicon structure 38, silicon germanide layer structure 40 and the silicon structure 42 of forming of heap of stone once more respectively, form sandwich construction, and the thickness of whole sandwich construction is approximately from 300 dusts to 1 micron (μ m).Utilize sandwich construction of the present invention, dislocation defects can be limited in the simple layer.In other words, as shown in Figure 6, it wherein is on the silicon structure 34 in regular turn on the silicon germanide layer structure 32 and silicon germanide layer structure 36, suppose wherein silicon germanide layer structure 32 and 34 generations of silicon structure, one dislocation defects 46, coated by isostructural silicon germanide layer owing to it is two-layer up and down, so this dislocation defects will be limited in 34 of silicon structures.
Please consult Fig. 5, when after finishing whole sandwich construction on the silicon substrate 30, can be in building crystal to grow one deck silicon germanide layer structure 44 on the silicon structure 42 of the superiors, wherein this silicon germanide layer structure 44 is by Si
0.75Ge
0.25Constitute, and its thickness can be between 1000 dusts to 5 micron (μ m), but is about 6000 dusts according to its thickness of this preferred embodiment, this layer is a stress release layer.Then, building crystal to grow one layer thickness is about the thin silicone layer 48 of 200 dusts thereon again, and this layer thickness will can not produce under the critical thickness of dislocation usually, and so can allow brilliant thin silicone layer thereon of heap of stone neither have a dislocation has the lattice parameter of broad again.This thin silicone layer 48 can be used as the channel region of MOS transistor, because it has the general also big lattice constant of silicon substrate, therefore can promote Electron drift speed, and then promote service speed.According to Fig. 6 because possible dislocation defects all is restricted in the sandwich construction of the present invention, so the thin silicone layer 48 of its top layer therewith silicon germanide layer structure 44 avoided the lattice dislocation, so therefore the yield of the chip of its manufacturing also promotes.But it should be noted that sandwich construction of the present invention, the repeating of its silicon germanide layer and the silicon layer step of growing up is respectively three times with preferred embodiment of the present invention, but as long as the step of the growing up effect of inventing more than twice easy attainable cost respectively.
The structure of the preferred embodiment of the invention described above can following formula be represented:
Substrate+{ Si
0.75Ge
0.25(100 dust)+Si (150 dust) } 3periods+Si
0.75Ge
0.25(6000 dust)+thin silicone layer (200 dust)
But sandwich construction of the present invention can be shown in down by a general formula:
Substrate+{ Si
1-xGe
x(＜critical thickness 〉)+Si (＜critical thickness) } n periods (n 〉=2)+Si
1-xGe
x(1000 dust to 50000 dust)+thin silicone layer (＜critical thickness 〉)
The present invention and tradition make maximum different be in, the silicon germanide layer structure that tradition is made is with Si
0.75Ge
0.25Being example, is to form according to following described method, and the source of germanium (Ge) is adjusted to 25% by 0% gradually, so more near the silicon germanide layer structure of substrate, the concentration of its silicon composition is big more, and away from the silicon germanide layer structure of substrate, the concentration of its germanium composition is big more more.Because it is not sandwich construction, that is itself and but sandwich construction of the present invention, so the dislocation that it produced can not be confined in one deck as the present invention.
According to the present invention, can replace by other material in order to the material of making as sandwich construction of the present invention, as long as the lattice constant of the component of the lattice constant silicon substrate of its component does not differ too greatly.Thin speech, the composition of sandwich construction of the present invention can be with other material replacement that comprises first material, and wherein the lattice constant of the component of the lattice constant that had of first material and substrate (for example silicon substrate) does not differ too big.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, the for example material that sandwich construction of the present invention comprised or the change of the ratio of its component, more than revise all is to utilize after the present invention discloses, all be familiar with this technical staff institute easily full of beard and, no matter whether it describes identical with this specification, neither spirit of the present invention and the scope of taking off is so all should be included in the following claim.
Claims (5)
1. sandwich construction that can reduce dislocation defects on silicon substrate comprises at least:
One silicon layer is formed on this silicon substrate;
One silicon kind layer is formed on this silicon substrate;
One sandwich construction is formed on this silicon kind layer, this sandwich construction is to replace storehouse by silicon germanide layer and silicon layer to form, wherein the bottom of this sandwich construction is a silicon germanide layer, and top layer is a silicon layer, and wherein those silicon germanide layer thickness and this silicon layer thickness are all less than its critical thickness;
One first silicon germanide layer is formed on this sandwich construction, as a stress release layer; And
One thin silicone layer is formed on this first silicon germanide layer, and wherein this thin silicone layer growth thickness is less than its critical thickness.
2. structure as claimed in claim 1, wherein this first silicon germanide layer thickness is between 1000 dust to 50000 dusts.
3. structure as claimed in claim 1, wherein its silicon germanide layer and silicon layer replace the storehouse number of times and are at least twice in this sandwich construction.
4. sandwich construction that can reduce dislocation defects comprises at least:
One silicon substrate;
First silicon germanide layer is formed on this silicon substrate, and wherein this first silicon germanide layer thickness is less than its critical thickness;
First silicon layer is formed on this first silicon germanide layer, and wherein this first silicon layer thickness is less than its critical thickness;
Second silicon germanide layer is formed on this first silicon layer, and wherein this second silicon germanide layer thickness is less than its critical thickness;
Second silicon layer is formed on this second silicon germanide layer, and wherein this second silicon layer thickness is less than its critical thickness;
The 3rd silicon germanide layer is formed on this second silicon germanide layer; And
One thin silicone layer is formed on the 3rd silicon germanide layer, and wherein the acceptable growth thickness of this thin silicone layer needs less than its critical thickness.
5. structure as claimed in claim 4, wherein the 3rd silicon germanide layer thickness is between 1000 dust to 50000 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02131671.6A CN1286147C (en) | 2002-09-11 | 2002-09-11 | Multi-layer structure with dislocation defect retardation |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02131671.6A CN1286147C (en) | 2002-09-11 | 2002-09-11 | Multi-layer structure with dislocation defect retardation |
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| Publication Number | Publication Date |
|---|---|
| CN1482651A CN1482651A (en) | 2004-03-17 |
| CN1286147C true CN1286147C (en) | 2006-11-22 |
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|---|---|---|---|
| CN02131671.6A Expired - Lifetime CN1286147C (en) | 2002-09-11 | 2002-09-11 | Multi-layer structure with dislocation defect retardation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8344447B2 (en) | 2007-04-05 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon layer for stopping dislocation propagation |
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2002
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