CN1286028C - Datatransmission control system and data transmission control method - Google Patents
Datatransmission control system and data transmission control method Download PDFInfo
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- CN1286028C CN1286028C CN 03149703 CN03149703A CN1286028C CN 1286028 C CN1286028 C CN 1286028C CN 03149703 CN03149703 CN 03149703 CN 03149703 A CN03149703 A CN 03149703A CN 1286028 C CN1286028 C CN 1286028C
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Abstract
The present invention discloses a data transmission control device which is applied to data exchange between a controller and at least one I/O module. The data transmission control device comprises an address arbitration circuit, a logic control circuit, an address bus switching circuit, a data bus switching circuit, a chip selection circuit and a shared memory. The present invention realizes the quick data exchange between the controller and the I/O module by using the shared memory and combining the strict logic control by the logic control circuit and greatly increases the communication speed between the controller and the I/O module; simultaneously, because the present invention adopts the common shared memory, the hardware cost is greatly lowered.
Description
Technical field
The invention belongs to the control technology field, particularly relevant for carrying out data transfer control system and data transfer control method between a kind of controller and the I/O module.
Background technology
Control system is widely used in industries such as machine-building, electric power, weaving.In control system, the exchanges data speed between controller and the I/O module directly has influence on the real-time of control system.The data transfer controller that is used for carrying out between controller and the I/O module data transmission at present has following several usually.
First kind of data transfer controller comprises special integrated circuit and dual port RAM, and it adopts the Data Transmission Controlling mode based on parallel bus, and exchanges data is carried out in dual port RAM.Integrated most of circuit of parallel bus in the special chip in this device makes it open poor, owing to it has also adopted expensive dual port RAM, makes its cost also higher.
Second kind of data transfer controller comprises dual port RAM and the very high cpu chip of serial communication speed.It adopts the communication data transmission control mode based on universal serial bus, also carries out exchanges data in double port memory.This device makes its cost also very high owing to adopted higher high-performance CPU of price and dual port RAM.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of lower-cost data transfer control system and realization rapid data method for communicating of carrying out rapid data communication between controller and I/O module.
A kind of data transfer control system, this system comprises controller, at least one I/O module, this system also comprises and I/O module data transfer controller one to one, this device comprises:
The address arbitration circuit, its input end is connected with described controller, and output terminal is connected with logic control circuit, is used to judge whether described controller chooses pairing I/O module;
Shared storage, described shared storage are the single port storer, and link address bus converting circuit, data bus switching circuit, chip select circuit are used to finish the exchanges data between described controller and the I/O module;
Address bus switching circuit, input end is connected with logic control circuit, simultaneously, connect described I/O module, described controller and described shared storage, be used for address bus with described shared storage and switch to and have the right to operate the controller of shared storage or the address bus of I/O module;
Data bus switching circuit, input end is connected with logic control circuit, simultaneously, connect described controller, described I/O module and described shared storage, be used for data bus with described shared storage and switch to and have the right to operate the controller of shared storage or the data bus of I/O module;
Chip select circuit, its input end connects controller respectively, logic control circuit is connected and the I/O module, its output terminal connects described shared storage, be used to determine that described controller still is that described I/O module is chosen described shared storage, determine described shared storage is carried out write operation or read operation;
Logic control circuit, its input end connects described controller respectively, I/O module and address arbitration circuit, its output terminal connects described address bus switching circuit respectively, data bus switching circuit and chip select circuit, be used to receive the request signal of described controller and described I/O module solicit operation shared storage, determine that controller still is an I/O module operation shared storage, and send and control signal to described address bus switching circuit, described data bus switching circuit and described chip select circuit, control foregoing circuit correspondence is finished the address bus blocked operation, data bus blocked operation and sheet selection operation.
Described address arbitration circuit comprises the first input end A and the second input end B, and first input end A is used to receive the signal a of controller output, the signal b that the second input end B determined when being used to receive motherboard and powering on.This system comprises 2N I/O module, and then described each I/O module is provided with the input end of 2N root address wire as the address arbitration circuit of I/O module, and wherein the first input end A and the second input end B are provided with N root address wire respectively, and described N is a positive integer.
A kind of data transfer control method of using above-mentioned data transfer control system, this method comprise controller function shared storage and two processes of I/O module operation shared storage;
(1) process of controller function shared storage
(1) controller sends the request that requires the operation shared storage;
(2) when logic control circuit 2 was judged the IO module not at the operation shared storage, logic control circuit sent and allows signal to send control signal to controller and to address bus switching circuit, data bus switching circuit and chip select circuit;
(3) address bus switching circuit, data bus switching circuit receive the control signal that described logic control circuit sends, and respectively address bus, data bus are switched to the address bus and the data bus of controller;
(4) chip select circuit receives the control signal that described logic control circuit sends, and determines that controller carries out read operation or write operation to it, and selects sheet the result to be sent to shared storage;
(5) controller and shared storage carry out exchanges data;
(2) process of I/O module operation shared storage
(6) the I/O module is sent the request that requires the operation shared storage to logic control circuit;
(7) when logic control circuit 2 was judged controller 7 not at the operation shared storage, logic control circuit sent and allows signal to the I/O module, and sends control signal to address bus switching circuit, data bus switching circuit and chip select circuit;
(8) address bus switching circuit, data bus switching circuit receive the control signal that logic control circuit sends, and respectively address bus, data bus are switched to the address bus and the data bus of I/O module;
(9) chip select circuit receives the control signal that logic control circuit sends, and affirmation I/O module is carried out read operation or write operation to it, and selects sheet the result to be sent to shared storage;
(10) shared storage and described I/O module are carried out exchanges data.
Step (1) further comprises: (1.1) controller is chosen the I/O module, and arbitration circuit sends the signal of choosing this I/O module to the address of this I/O module; (1.2) described address arbitration circuit is received this selected signal a, and b compares with signal, and when signal a was identical with b, then described address arbitration circuit sent a selected signal to logic control circuit.
Also comprise between step (1) and (2): after logic control circuit is received the selected signal that described address arbitration circuit sends, whether detect the I/O module at the operation shared storage, if not, carry out step (2), do not allow to operate the signal of shared storage to controller otherwise logic control circuit sends one.
Step (2) also further comprises: (2-1) controller is inquired about controller and whether is sent the permission signal in a default time interval, if carry out step (3), otherwise carry out step (2-2); (2-2) judge the number of times whether number of times of inquiry equals to set, if then the next I/O module of controller function is carried out step (1), if not, carries out step (2-1).
Also comprise between step (6) and the step (7): after logic control circuit is received the request signal that the I/O module sends, judge that whether controller is at the operation shared storage, if, logic control circuit sends one and does not allow to operate the signal of shared storage to the I/O module, otherwise logic control circuit further detects the application whether controller is sending the operation shared storage, if logic control circuit sends a signal that does not allow to operate shared storage to the I/O module, otherwise carry out step (7).
The present invention uses the logic control of shared storage in conjunction with the logic control circuit strictness, realize the exchanges data between controller and the I/O module, accelerated the communication speed between controller and the I/O module greatly, because the present invention can adopt common single port shared storage, its hardware cost is reduced greatly simultaneously.
Description of drawings
Fig. 1 is the overall schematic of an embodiment of data transfer control system among the present invention.
Fig. 2 is the structural representation of address of the present invention arbitration circuit.
Fig. 3 is the structural representation of chip select circuit of the present invention.
Fig. 4 sends the process flow diagram of operation shared storage request for controller of the present invention.
Fig. 5 is the process flow diagram of controller function shared storage of the present invention.
Fig. 6 is the process flow diagram of I/O module operation shared storage of the present invention.
Fig. 7 carries out the integrated circuit synoptic diagram of the data transfer control system of data transmission for a controller of the present invention and a plurality of I/O module.
Fig. 8 is the synoptic diagram of another embodiment of data transfer control system of the present invention.
Embodiment
See also Fig. 1, data transfer control system comprises control 7, I/O module 8 and I/O module data transfer controller 100 one to one, mainly comprises address arbitration circuit 1, logic control circuit 2, address bus switching circuit 3, data bus switching circuit 4, chip select circuit 5 and shared storage 6.Wherein:
Address bus switching circuit 3 is connected with controller 7, I/O module 8 and logic control circuit 2 respectively, is used for address bus is switched to the controller 7 or the I/O module 8 of having the right to operate shared storage 6.When controller 7 obtained the right of operation shared storage 6, this address bus converting circuit 3 switched to the address bus on the shared storage 6 address bus of controller 7; When I/O module 8 obtained the power of operation shared storage 6, this address bus converting circuit 3 switched to the address bus on the shared storage 6 address bus of I/O module 8.Judgement is to be control signal output decision by logic control circuit 2 by controller 7 or by the right that I/O module 8 obtains operation shared storages 6.
Data bus switching circuit 4 connects controller 7, I/O module 8 and logic control circuit 2 respectively, is used for data bus switched to having the right to obtain the controller 7 of shared storage 6 or the address bus of I/O module 8.When controller 7 obtained the power of operation shared storage 6, this data bus switching circuit 4 switched to the data bus on the shared storage 6 data bus of controller 7; When I/O module 8 obtained the power of operation shared storage 6, this data bus switching circuit 4 switched to the data bus on the shared storage 6 data bus of I/O module 8; Judgement is to be control signal output decision by logic control circuit 2 by controller 7 or by the right that I/O module 8 obtains operation shared storages 6.
Chip select circuit 5, its input end connects controller 7, I/O module 8 and logic control circuit 2 respectively, its output terminal is connected to shared storage 6, be used for determining that a certain moment is that controller 7 chooses shared storage or I/O module 8 to choose shared storage 6, determine that simultaneously this constantly carries out read operation or write operation to shared storage 6, and the result who determines is exported in the shared storage 6.See also Fig. 3, be the structural representation of chip select circuit 5 of the present invention.Chip select circuit 5 can adopt logical device to realize its circuit function.Signal f and signal g are respectively the chip selection signal of controller 7 outputs and the chip selection signal of I/O module 8 outputs, its signal h, i, j is the output by logic control circuit 2, signal h represents the state (promptly " reading " still " writing " state of state) of the read-write operation that 7 pairs of shared storages of controller 6 carry out, signal i represents the state (promptly " reading " still " writing " state of state) of the read-write operation that 8 pairs of shared storages of I/O module 6 carry out, signal j is the output control signal of logic control circuit 2, signal k and signal l be chip select circuit 5 export shared storage 6 to, signal k determines that having the right to operate shared storage 6 is controller 7 or I/O module 8, and signal l determines that the operation that shared storage 6 is carried out is read operation or write operation.For example, if be provided with when signal j is high level, I/O module 8 is chosen in expression, and during for low level, controller 7 is chosen in expression.When signal j is high level, signal k=signal g, signal l=signal i; When pin H is low level, signal k=signal f, signal l=signal h.
Shared storage 6 is used to finish the exchanges data between controller 7 and the I/O module 8, and shared storage 6 can adopt common single port storer, reaches the effect that reduces cost.
The data transfer control method that carries out data communication between controller 7 of the present invention and the I/O module 8 comprises two processes: the process of (one) controller 7 operation shared storages 6; (2) process of I/O module 8 operation shared storages 6.
Please refer to Fig. 4, Fig. 5, be the process of controller 7 operation shared storages 6.Comprising:
S110: controller 7 sends the request that requires operation shared storage 6, further comprises:
S112: controller 7 is chosen I/O module 8, sends signal a to the address of this I/O module 8 arbitration circuit 1;
S114: address arbitration circuit 1 judges whether signal a is consistent with signal b, if consistent, then carry out step S116, otherwise carries out step S118;
S116: address arbitration circuit 1 sends a high level signal to logic control circuit 2, shows that these I/O module 8 controlled devices 7 choose, and then carries out step S120;
S118: address arbitration circuit 1 sends low level signal to logic control circuit 2, the logical signal e of logic control circuit 2 outputs is a low level, controller 7 is inquired about logical signal e one time at interval every one section Preset Time, when inquiry times more than or equal to time of a certain numerical value or inquiry time value more than or equal to certain setting, controller 7 withdraws from this step;
S120: logic control circuit 1 judges whether to operate shared storage 6, if carry out step S170, otherwise carries out step S130; This I/O module 8 can be divided into following four kinds of situations:
B-1, when controller 7 is chosen this I/O module 8, I/O module 8 is being operated shared storage 6, promptly carries out step S170;
B-2, when controller 7 is chosen this I/O module 8, I/O module 8 at operation shared storage 6, is not carried out step S130;
B-3, when controller 7 is chosen I/O module 8, I/O module 8 is not operated shared storage 6.But in the process of controller 7 operation shared storages 6, I/O module 8 is sent the application of operation shared storage 6, output logic signal c is a high level, at this moment, controller 7 continues operation shared storage 6, logic control circuit 2 output logic signal d are low level, and I/O module 8 can not obtain the right of shared storage 6;
When b-4, controller 7 are chosen I/O module 8, I/O module 8 is the shared storage 6 of application operation simultaneously also, at this moment, controller 7 operation shared storages 6 preferential I/O module 8 control shared storages 6, logic control circuit 2 can detect this I/O module 2 not at operation shared storage 6, carries out step S130;
S130: logic control circuit 2 send logical signal e be the permission signal of high level to controller 7, and send control signal to address bus switching circuit 3, data bus switching circuit 4 and chip select circuit 5 respectively;
S140: address bus switching circuit 3, data bus switching circuit 4 are received the control signal that logic control circuit 2 sends, and respectively the address bus on the shared storage 6 and data bus are switched to the address bus and the data bus of controller 7;
S150: chip select circuit 5 receives the control signal that logic control circuit 2 sends, and determines it is controller 7 control shared storages 6, and determines it is carried out read operation or write operation, and select sheet the result to give shared storage 6;
S160: shared storage 6 and controller 7 carry out exchanges data, and exchanges data comprises that controller 7 sense data and controller 7 from shared storage 6 write data to shared storage 6, and the signal that is sent by chip select circuit 5 is determined.End operation shared storage 6 in very short time can allow this I/O module 8 more behind the new data, and the data in the shared storage 6 that can upgrade in time are so that controller 6 can in time read;
S170: if logic control circuit 2 detects I/O module 8 at operation shared storage 6, then sending logical signal e is that low level is to controller 7;
S180: whether controller is low level every a Preset Time time query logic signal e, if then carry out step S190, otherwise carries out step S140;
S190: the number of times whether time of judge waiting for equals to set more than or equal to the number of times of time of setting or inquiry, if then finish, otherwise carry out step S180.
Please refer to Fig. 6, be the process flow diagram of I/O module 8 operation shared storages 6.
During S210:I/O module 8 application operation shared storages 6, send the request that requires the operation shared storage to logic control circuit 2, promptly I/O module 8 is to the logical signal c of logic control circuit 2 output high level;
S215: whether this logic control circuit 2 judges controller 7 at operation shared storage 6, if, carry out step S270, if not, then carry out step S220;
S220: logic control circuit 2 further judges whether controller 7 proposes to operate the application of shared storage 6, promptly whether detects the selected signal of the high level that address arbitration circuit 1 sends, if carry out step S270, otherwise carry out step S230;
S230: it is that high level is to I/O module 8 that logic control circuit 2 sends logical signal d;
S240: address bus switching circuit 3, data bus switching circuit 4 are received the control signal that logic control circuit 2 sends, and respectively the address bus on the shared storage 6 and data bus are switched to the address bus and the data bus of I/O module 8;
S250: chip select circuit 5 is determined it is I/O module 8 control shared storages 6, and is determined it is carried out read operation or write operation, and chip selection signal is sent to shared storage 6 according to the control signal that logic control circuit 2 sends;
S260: shared storage 6 and I/O module 8 are carried out exchanges data;
S270: controller 7 is being operated shared storage 6, controller 7 is applying for operating shared storage 6 if logic control circuit 2 detects, and then sending logical signal d is that low level is to I/O module 8;
S280:I/O module 8 detects whether logical signal d is low level, if then carry out step S290, otherwise carry out step S240;
S290: the time of judge waiting for whether more than or equal to the time of setting or the number of times of detection more than or equal to the number of setting, if then then carry out other operation, otherwise carry out step S280.
More than disclosed controller 7 and I/O module 8 carry out the data transfer control method of exchanges data.Specifically, can comprise (1) I/O module 8 write data to shared storage 6 and controller 7 sense data from shared storage 6; (2) controller 7 write data to shared storage 6 and I/O module 8 sense data from shared storage 6.
See also Fig. 7, for a controller 7 and a plurality of I/O module in this system are carried out exchanges data.Data transfer controller 100 in the system and I/O module can be corresponding one by one.There is 2N I/O module in this system, and then each I/O module is provided with the input end of 2N root address wire as the address arbitration circuit of I/O module, and wherein the first input end A and the second input end B are provided with N root address wire respectively, and N is a positive integer, as N be 1,2....Getting 3 with N is example, and controller and 8 I/O modules are carried out exchanges data and carried out exchanges data by 8 data transfer controllers 100.8 block I/O modules in the system, be respectively I/O module a, I/O module b.......I/O module h, each I/O module has an address arbitration circuit, correspondingly, 8 and I/O module corresponding address arbitration circuit are arranged in this system, address arbitration circuit a, arbitration circuit b...... address, address arbitration circuit h.On each I/O module motherboard 6 tracks are set and are used for address selection, wherein three address wires are determined its level according to the different addresses of each I/O module assignment after system powers on, and other three address wires select signal output to determine by controller address.
Controller and each I/O module are carried out the method for exchanges data, and be open in above-mentioned steps S100 and S200.Controller is determined an I/O module, send request, receive behind the permission signal that the logic control circuit of this I/O module correspondence sends with corresponding shared storage and carry out exchanges data, when not obtaining the right of operation shared storage, controller then the next I/O module of operation.Controller can adopt polling mode and each I/O module to carry out exchanges data.
See also Fig. 8, be the structural representation of data transfer control system second embodiment of the present invention.This data transfer control system comprises controller, several I/O modules, and I/O module data transfer controller 100 one to one.
This device comprises:
The address arbitration circuit, the input end of the address arbitration circuit of each I/O module is connected to same bus, and described bus connects described controller again, is used to judge whether described controller chooses pairing I/O module;
Shared storage is used to finish the exchanges data between described controller and the I/O module;
Address bus switching circuit connects described I/O module, described controller and described shared storage respectively, is used for address bus with described shared storage and switches to and have the right to operate the controller of shared storage or the address bus of I/O module;
Data bus switching circuit connects described controller, described I/O module and described shared storage respectively, is used for data bus with described shared storage and switches to and have the right to operate the controller of shared storage or the data bus of I/O module;
Chip select circuit, its input end connects controller and I/O module respectively, be used to determine that described controller still is that described I/O module chooses shared storage with determining shared storage to be carried out write operation or read operation, and a result who determines is exported to described shared storage;
Logic control circuit, its input end connects described controller respectively, I/O module and described address arbitration circuit, its output terminal connects described address bus switching circuit respectively, data bus switching circuit and chip select circuit, be used to receive the request signal of described controller and described I/O module solicit operation shared storage, determine that controller still is an I/O module operation shared storage, and send and control signal to described address bus switching circuit, described data bus switching circuit and described chip select circuit, the control foregoing circuit is finished corresponding address bus blocked operation, data bus blocked operation and sheet selection operation.It is similar that this data transfer controller middle controller and I/O module are carried out the method and the embodiment 1 of Data Transmission Controlling.Repeating part is not giving unnecessary details.
Though the present invention with at least one preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (8)
1, a kind of data transfer control system, this system comprises controller, at least one I/O module, it is characterized in that, this system comprises also and I/O module data transfer controller one to one that this device comprises:
The address arbitration circuit, its input end is connected with described controller, and output terminal is connected with logic control circuit, is used to judge whether described controller chooses pairing I/O module;
Shared storage, described shared storage are the single port storer, and link address bus converting circuit, data bus switching circuit, chip select circuit are used to finish the exchanges data between described controller and the I/O module;
Address bus switching circuit, input end is connected with logic control circuit, simultaneously, connect described I/O module, described controller and described shared storage, be used for address bus with described shared storage and switch to and have the right to operate the controller of shared storage or the address bus of I/O module;
Data bus switching circuit, input end is connected with logic control circuit, simultaneously, connect described controller, described I/O module and described shared storage, be used for data bus with described shared storage and switch to and have the right to operate the controller of shared storage or the data bus of I/O module;
Chip select circuit, its input end connects controller respectively, logic control circuit is connected and the I/O module, its output terminal connects described shared storage, be used to determine that described controller still is that described I/O module is chosen described shared storage, determine described shared storage is carried out write operation or read operation;
Logic control circuit, its input end connects described controller respectively, I/O module and address arbitration circuit, its output terminal connects described address bus switching circuit respectively, data bus switching circuit and chip select circuit, be used to receive the request signal of described controller and described I/O module solicit operation shared storage, determine that controller still is an I/O module operation shared storage, and send and control signal to described address bus switching circuit, described data bus switching circuit and described chip select circuit, control foregoing circuit correspondence is finished the address bus blocked operation, data bus blocked operation and sheet selection operation.
2, data transfer control system as claimed in claim 1, it is characterized in that, described address arbitration circuit comprises the first input end A and the second input end B, and first input end A is used to receive the signal a of controller output, the signal b that the second input end B determined when being used to receive motherboard and powering on.
3, data transfer control system as claimed in claim 2 is characterized in that, this system comprises 2
NIndividual I/O module, then described each I/O module is provided with the input end of 2N root address wire as the address arbitration circuit of I/O module, and wherein the first input end A and the second input end B are provided with N root address wire respectively, and described N is a positive integer.
4, a kind of data transfer control method of data transfer control system of application rights requirement 1 is characterized in that this method comprises controller function shared storage and two processes of I/O module operation shared storage;
(1) process of controller function shared storage
(1) controller sends the request that requires the operation shared storage;
(2) when logic control circuit 2 was judged the IO module not at the operation shared storage, logic control circuit sent and allows signal to send control signal to controller and to address bus switching circuit, data bus switching circuit and chip select circuit;
(3) address bus switching circuit, data bus switching circuit receive the control signal that described logic control circuit sends, and respectively address bus, data bus are switched to the address bus and the data bus of controller;
(4) chip select circuit receives the control signal that described logic control circuit sends, and determines that controller carries out read operation or write operation to it, and selects sheet the result to be sent to shared storage;
(5) controller and shared storage carry out exchanges data;
(2) process of I/O module operation shared storage
(6) the I/O module is sent the request that requires the operation shared storage to logic control circuit;
(7) when logic control circuit 2 was judged controller 7 not at the operation shared storage, logic control circuit sent and allows signal to the I/O module, and sends control signal to address bus switching circuit, data bus switching circuit and chip select circuit;
(8) address bus switching circuit, data bus switching circuit receive the control signal that logic control circuit sends, and respectively address bus, data bus are switched to the address bus and the data bus of I/O module;
(9) chip select circuit receives the control signal that logic control circuit sends, and affirmation I/O module is carried out read operation or write operation to it, and selects sheet the result to be sent to shared storage;
(10) shared storage and described I/O module are carried out exchanges data.
5, data transfer control method as claimed in claim 4 is characterized in that, step (1) further comprises:
(1.1) controller is chosen the I/O module, and arbitration circuit sends the signal of choosing this I/O module to the address of this I/O module;
(1.2) described address arbitration circuit is received this selected signal a, and b compares with signal, and when signal a was identical with b, then described address arbitration circuit sent a selected signal to logic control circuit.
6, data transfer control method as claimed in claim 5 is characterized in that, also comprises between step (1) and (2):
After logic control circuit is received the selected signal that described address arbitration circuit sends, whether detect the I/O module at the operation shared storage, if not, carry out step (2), do not allow to operate the signal of shared storage to controller otherwise logic control circuit sends one.
7, data transfer control method as claimed in claim 6 is characterized in that, step (2) also further comprises:
(2-1) controller is inquired about controller and whether is sent the permission signal in a default time interval, if carry out step (3), otherwise carry out step (2-2);
(2-2) judge the number of times whether number of times of inquiry equals to set, if then the next I/O module of controller function is carried out step (1), if not, carries out step (2-1).
8, data transfer control method as claimed in claim 4 is characterized in that, also comprises between step (6) and the step (7):
After logic control circuit is received the request signal that the I/O module sends, judge that whether controller is at the operation shared storage, if, logic control circuit sends one and does not allow to operate the signal of shared storage to the I/O module, otherwise whether the further detection of logic control circuit receives the address arbitration circuit and sends the permission signal, if logic control circuit sends a signal that does not allow to operate shared storage to the I/O module, otherwise carry out step (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03149703 CN1286028C (en) | 2003-08-04 | 2003-08-04 | Datatransmission control system and data transmission control method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03149703 CN1286028C (en) | 2003-08-04 | 2003-08-04 | Datatransmission control system and data transmission control method |
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| CN1580985A CN1580985A (en) | 2005-02-16 |
| CN1286028C true CN1286028C (en) | 2006-11-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567259A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Low-power-consumption buffer device orienting to high-speed communication interface |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103336486B (en) * | 2012-12-19 | 2015-11-18 | 惠州市亿能电子有限公司 | A kind of battery modules address distribution method of battery energy storage system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567259A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | Low-power-consumption buffer device orienting to high-speed communication interface |
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| CN1580985A (en) | 2005-02-16 |
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