CN1284813A - Multifunctional character superposing display circuit in digital video system - Google Patents
Multifunctional character superposing display circuit in digital video system Download PDFInfo
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Abstract
The multifunctional character superposing display circuit has the functions of fringing character, low background treatment of image around characters, fade-in and fade-out and color control of character, programmed control and/or automatic control of brightness, etc. The circuit combined OSD technology and digital video system closely to make the video system with rich display functions and excellent visual effect. The present invention makes the system become more fiexible and universal while raising its integrated level, and may be applied in the design of ICs for digital video system partially or even completely as well as realized in the disign of programmable logic device.
Description
The present invention relates to digital video technology, be specifically related to a kind of multifunctional character superposing display circuit that uses in the Digital Video System that is applicable to, more particularly, relate to a kind ofly have that the character fringing is handled, multifunctional character superposing display circuit in the Digital Video System of function such as the control of the program control of be fade-in fade-out control and character color, the brightness of low background process, the character of image around the character/automatically.
In traditional video system, the screen character Presentation Function is to be finished by the overlaying character demonstration of special use (being called for short OSD down) chip, fixing, simple function can only be provided, the resource that offers high-rise exploitation is also less relatively, for example is difficult to realize that the character fringing is handled, the program control of be fade-in fade-out control and character color, the brightness of low background process, the character of image around the character/function such as control etc. automatically.Because user extendible leeway when the video system of design oneself is limited, especially in the Digital Video System Design process, the external hanging type structure of OSD has restricted the raising of entire system function.
The object of the present invention is to provide multifunctional character superposing display circuit in a kind of Digital Video System, OSD technology and Digital Video System are combined closely, utilize Digital Signal Processing to make OSD have abundant Presentation Function and visual effect, when increasing system flexibility and versatility, improve the integrated level of system, more particularly the purpose of this invention is to provide a kind of multifunctional character superposing display circuit, can provide the character fringing to handle, the low background process of image around the character, the program control of be fade-in fade-out control and the character color and the brightness of menu character/functions such as automatic control, and can be all or part of employing in the integrated circuit (IC) design process of Digital Video System, also can in programmable logic device, design and finish.
The object of the present invention is achieved like this, construct multifunctional character superposing display circuit in a kind of Digital Video System, can accept the outer CPU instruction and realize multi-functional video character overlaying function, it is characterized in that comprising the cpu instruction decoder 2 that described cpu instruction is decoded, character signal generator 3, fringing signal generator 4 and visual character attribute controller 1, described character signal generator 3 receive clocks and synchronizing signal output to fringing signal generator 4 with the character signal that produces, and described visual character attribute controller 1 receives the signal of digital rgb signal and 4 outputs of fringing signal generator and exports the digital rgb signal.
According to circuit provided by the invention, it is characterized in that, described character signal generator 3 comprises the display buffer 31 that is used to deposit character code and character attibute, be used to deposit the library stores device 32 of character display dot array data, described library stores device 32 is programmable, can include a plurality of character patterns storehouse, each Dot Matrix Library can be switched and load as required.
According to circuit provided by the invention, it is characterized in that, described character signal generator 3 has two kinds of operating states, at the character show state, produce the explicit address that is synchronized with row, field sync signal by sequence circuit, by specific compound mode addressing display buffer 31 and library stores district 32, output character point signal; At the character programming state, take over the address bus and the data/address bus in display buffer 31 and library stores district 32 respectively by outer CPU, it is carried out the renewal operation of data, and the switching of described two kinds of operating states of described character signal generator 3 is by instruction decoder 2 controls.
According to circuit provided by the invention, it is characterized in that described fringing signal generator 4 is invalid and with any one of the position of adjacent 8 directions of this point or produce the fringing signal when point signal is effective more than one in current display dot itself.
According to circuit provided by the invention, it is characterized in that, described fringing signal generator 4 comprises: first line buffer 401, second line buffer 402, the the 1st to the 9th character point buffer 403-411, the character point signal of character point signal generator is at first through 2 line buffers 401, after 402 time-delays, produce the parallel character point signal HD0 of adjacent 3 row, HD1, HD2, three line data are separately again after 3 character point buffer time-delays, each produces 3 adjacent parallel by character point signal P1～P9 of horizontal direction, the character point signal is added the current some P5 point signal of time-delay input and the character attibute data of 2 pixels through 1 row, when showing with the assurance character, its color, background attribute and fringing signal and character point signal are consistent.
According to circuit provided by the invention, it is characterized in that, described character attibute controller 1 comprises background attenuation coefficient multiplier 101, low background control switch 102, fringing signaling switch 103, character point signaling switch 104, mean flow rate detecting unit 105, mean flow rate control switch 106, mean flow rate multiplier 107, character color selected cell 108, transparent control switch 109, adder 110, coefficient of transparency multiplier 111, complement multiplication device 112, complement code generator 113, wherein, background attenuation coefficient multiplier 101 is used for background attenuation coefficient and video input signals carried out multiplying and the result is sent the A input of described low background control switch 102, the B input receiver, video input signal of described low background control switch 102, the output of described low background control switch 102 is connected with the B input of described fringing signaling switch 103, the input of the A input of described fringing signaling switch 103 has the fringing signal and its output is connected to the A input of character point signaling switch 104, the video input signals of 105 pairs of inputs of described mean flow rate detecting unit averages the A input that brightness detected and this detection signal was input to mean flow rate control switch 106, the B input of described mean flow rate control switch 106 receives its output signal of character luminance factor then becomes mean flow rate multiplier 107 respectively with the output signal of character color selected cell 108 two input signals, and the output of mean flow rate multiplier 107 is connected to the A input of transparent control switch 109, the input of complement multiplication device 112, another input of complement multiplication device 112 receives the output of complement code generator 113, described complement code generator 113 is used to produce the complement code of coefficient of transparency, coefficient of transparency multiplier 111 multiplies each other coefficient of transparency and vision signal and consequential signal is input to an input of transparent signal adder 110, another input of described transparent signal adder 110 receives the output signal of described complement multiplication device 112, and the output signal of transparent signal adder 110 is transported to the B input of transparent control switch 109, the output of transparent control switch 109 is connected to the B input of described character point signaling switch 104, and described character color selected cell 108 is used for selecting corresponding color according to the character color position of character attibute from the color parameter that presets.
According to circuit provided by the invention, it is characterized in that, under the low background signal that described low background control switch 102 produces in the background attribute position by character code is controlled, with video input signals with carry out multiplying by the low background coefficient of outer CPU setting, export ratio is in the video data of low background system.
According to circuit provided by the invention, it is characterized in that described mean flow rate testing circuit 105 comprises: single pixel brightness computing unit is used for the brightness according to this pixel of digital rgb calculated signals of each pixel; The pixel brightness unit that adds up, zone is used for the dateout from described single pixel computing unit is added up; Zone leveling brightness temporary storage location is used for temporary accumulation result data from the described unit that adds up; First control unit is used in described zone first pixel constantly, to the unit zero clearing that adds up of described regional pixel brightness; Second control unit is used in described zone last pixel constantly, and the add up data of unit of described regional pixel brightness are delivered to described zone leveling brightness temporary storage location.
According to circuit provided by the invention, it is characterized in that, described single pixel computing unit comprises adder 151 and removes 4 dividers 152, three inputs of described adder 151 are imported R, G, B signal in the described digital rgb signal respectively, fixed numbers of another input input of described adder 151, the output of described adder 151 is connected to the described input that removes 4 dividers 152, and the described output that removes 4 dividers 152 provides signal to the described regional pixel unit that adds up.
According to circuit provided by the invention, it is characterized in that, the described regional pixel brightness unit that adds up comprises an adder 153, first Double Port Random Memory 156, the first input end mouth input of described adder 153 is from the data of described single pixel brightness computing unit 152, second port input of described adder 153 is from the storage data of described first Double Port Random Memory 156, and the output of described adder 153 is connected to first port of described first Double Port Random Memory 156.
According to mean flow rate testing circuit provided by the invention, it is characterized in that, described zone leveling brightness temporary storage location comprises second Double Port Random Memory 159, wherein first port is a write port, be used to import from the add up most-significant byte of data of unit 156 of described regional pixel, wherein the average brightness of 8 of second port outputs.
According to mean flow rate testing circuit provided by the invention, it is characterized in that, described first control unit comprise one with 154 and one at door or 157, described or the door 157 input area pixel count signals, described output with door 154 is connected second port of described adder 153, described and door 154 first input end and second port of described first Double Port Random Memory 156, described second input with door 154 is connected to output described or door 157, described or door 157 input area pixel count signals.
According to circuit provided by the invention, it is characterized in that described regional pixel count signal can be provided by the low level of level numeral clock signal and vertical digital clock signal.
According to mean flow rate testing circuit provided by the invention, it is characterized in that, described second control unit comprises one and door 158, described with the door 158 input area pixel count signals, the data that described output end signal with door 158 is controlled described second Double Port Random Memory 159 write, and the clock sync signal that the data of described second Double Port Random Memory 159 write or read is the address signal of character buffer.
Implement multifunctional character superposing display circuit in the Digital Video System provided by the invention, produce in character signal, character attibute chemical control system, the character fringing is handled, the low background process of image around the character, the aspects such as the control of being fade-in fade-out of control of the program control of character color and brightness/automatically and menu character provide prior art the more superior performance that do not possess or compare, OSD technology and Digital Video System are combined closely, utilize Digital Signal Processing to make OSD have abundant Presentation Function and visual effect, when increasing system flexibility and versatility, improve the integrated level of system, this multifunctional character superposing display circuit can all or part ofly be applied in the integrated circuit (IC) design process of Digital Video System, also can design in programmable logic device and finish.
Below in conjunction with drawings and Examples, further specify characteristics of the present invention, in the accompanying drawing:
Fig. 1 is the The general frame of multifunctional character superposing display circuit provided by the invention;
Fig. 2 is the schematic diagram of the character signal generator of explanation graphics mode;
Fig. 3 is the schematic diagram of the character signal generator of explanatory text mode;
Fig. 4 is the schematic diagram of the formation and the implication thereof of description character code;
Fig. 5 is the schematic diagram that explanation produces the fringing signal conditioning;
Fig. 6 is the principle schematic that detects the fringing signal;
Fig. 7 is the block diagram of the fringing signal processing circuit that proposes of the present invention;
Fig. 8 is the character signal generator circuit block diagram that the present invention proposes;
Fig. 9 is the character attibute control circuit that the present invention proposes;
Figure 10 is the mean flow rate testing circuit that the present invention proposes.
Circuit of the present invention can be used in the Digital Video System need be on image overlaying character show the occasion of (OSD), its way circuit block diagram as shown in Figure 1, this circuit can be accepted the instruction of outer CPU (not shown) various video character overlaying function is provided, this circuit mainly comprises character signal generator 3, fringing signal generator 4, character attibute controller 1 and cpu instruction decoder 2, wherein cpu instruction decoder 2 is used to explain the instruction of CPU, produces parameter required in other module and control signal.Below will elaborate to principle of the present invention according to each functions of modules block diagram.1, adopt text mode to produce character signal
The generation of character signal has 2 kinds of modes: 1) graphics mode; 2) text mode.Fig. 2 and Fig. 3 show the circuit structure of 2 kinds of modes respectively.
Graphics mode character display shown in Figure 2 is meant the character that shows on the screen, its each put each memory cell in the corresponding display buffer, by each the order output in the display timing generator circuit 201 control display buffers 202, the corresponding character signal of character pattern that can obtain and write at output just.In this manner, owing to the state of 202 each unit, display buffer all can be programmed arbitrarily by outer CPU, thus under the support of software, can show the figure and the character of any specific, but this kind mode has 2 weak points: 1) hardware spending is big.Because the corresponding memory cell of each pixel adds additional informations such as character attibute, just needs a large amount of display buffers, will take a large amount of integrated circuit (IC) chip resources like this.2) software overhead is big.Owing to all must operate the control of each character display, so the software execution cycle is long to each position of forming this character pattern, under the prerequisite of assurance character renewal speed, will be very high to the rate request of CPU and related hardware.
Text mode character display shown in Figure 3 is meant that 31 of display buffers deposit character code, during demonstration, the character code of output goes addressing to deposit the library stores device 32 of character pattern according to the display timing generator generator, the corresponding dot matrix signal of character library 32 outputs that is addressed forms each of character, CPU is to the control of display buffer 31 like this, only at character code, the hardware and software expense all can be very little.Capacity as for character pattern storehouse 32, only need the data of can storage system used character pattern to get final product, and can be according to shielding the character kind together, grouping forms a plurality of character patterns storehouse, reload when needed, can further reduce the resource occupation of hardware like this, be particularly suitable for the limited occasion of screen output character kind.Therefore, it is the best approach of simplifying hardware and software that the text display mode cooperates dot matrix word library able to programme, and simultaneously, because the programmability of dot matrix word library, therefore the Hanzify that shows is able to simple realization.
Circuit of the present invention adopts text mode shown in Figure 3 to produce character signal, i.e. the display buffer mode of separating with dot matrix word library can reduce the expense of hardware and software.In addition, by to the reloading of character library district, can show multiple additional character, and be easy to realize Hanzify.2, character attibute and character-coded Synchronous Processing
Circuit of the present invention adopts character attibute and character-coded Synchronous Processing, makes that the character Presentation Function is abundanter, also is character color control, image hangs down background process, the character fringing produces, the program control of character brightness/control automatically, and the effect of being fade-in fade-out of menu provides support.
Specifically, in the character mode character display process that the present invention adopts, in the display buffer, deposit and represent each to want the data of character display to become character code, it is made of character code and character attibute, Fig. 4 shows the formation and the implication of 8 character codes, character code is meant the serial number of character in current dot matrix word library, has determined the shape of character, and character attibute is meant the Show Color coding of this character and whether the low background control of image is arranged.Pressing Fig. 4 definition, determined that with screen character kind be 32, is 4 kinds with screen character color kind.3, fringing signal processing
After the synthetic demonstration of character and image, when the brightness of the brightness of picture material and character is close, can make character be difficult to distinguish, the function of character fringing is to form shade one around the dot matrix that character shows, makes character can both make its clear-cut as seen under any image brightness background.
The logical condition that the fringing signal produces is: at a time, as P5 point among Fig. 5, position (P1～P4 when 8 directions adjacent with this point, P6～P9), when having one or more character point signal effective, then the P5 point just should produce the fringing signal, certainly, when effective, then do not belong to this situation as the character point signal in this position own.Fig. 6 shows the circuit logic relation that produces the fringing signal at the P5 point.
Fig. 7 shows the principle of character fringing signal generating circuit, and wherein 401,402 is line buffer, and 403-411 is the character point buffer.From the character point signal of character signal generator (Fig. 8) at first after 401,402 time-delays of 2 line buffers, produce parallel character point signal HD0, HD1, the HD2 of adjacent 3 row, wherein HD0 is defined as next line, HD1 is a current line, HD2 is a lastrow, 3 line data are separately again after 3 character point buffer time-delays, each produces 3 adjacent parallel by character point signal P1～P9 of horizontal direction, P5 is defined as current point among the figure, other is 8 adjacent on its screen character point signals, therefore, the logical circuit relation that produces the fringing signal on the P5 position is illustrated as Fig. 6.Because the P5 point is actually input traffic and has passed through the 1 capable time-delay that adds 2 pixels, in order to be synchronized with the fringing signal, character point signal and character attibute signal also should be made Synchronous Processing on time relationship, so the character point signal is directly taken from P5, and 3 signals of character attibute also all add 2 picture element time-delays through 1 row, finish this function by line buffer among the figure 412, character point buffer 413 and 414, in the time of could guaranteeing that like this character shows, its color, background attribute and fringing signal and character point signal are consistent.4, the low background process of image
The low background process of image is meant near the character viewing area, and the content of image shows in the low contrast mode, weakening the influence of image to character, thereby can more vivo give prominence to the character display effect, especially is adapted to the occasion of menu multirow character demonstration.
About the low background control theory of image, in number of patent application is 94116694,2 publication " character information processing circuit ", a kind of analog control method has been proposed, its low background control signal is the character background blanking signal that results from special-purpose OSD chip output, the parameter of low background is to regulate in the potentiometer mode, but does not consider that level cooperates and the insertion problems such as image fault that character produced.
The present invention adopts digitalized processing method fully, and the low background coefficient of image can be provided with arbitrarily by cpu instruction.Concrete grammar is: under low background signal control, the low background coefficient that digital of digital video data and CPU are provided with carries out multiplying, export ratio is in the video data of low background system, the contrast and the color of therefore low background image all can be provided with arbitrarily, also can not produce the other problems such as level cooperation that analogy method is brought.The low background control signal of image is that the background attribute position by character code produces, can be by software setting.5, character signal generator
Fig. 8 shows the circuit block diagram that produces character point signal and character attibute signal, and wherein display buffer 31 is used to deposit the character display code, comprises character code and character attibute; Character pattern storehouse 32 is used to deposit the dot array data of character display.
The character signal generator has 2 kinds of operating states:
1) character show state is synchronized with showing of row, field sync signal by the sequence circuit generation
Show the address, by specific compound mode addressing display buffer 31 and library stores
2) character programming state: be to take over display buffer 31 and word respectively by outer CPU
The address bus in library storage district 32 and data/address bus carry out the renewal of data to it
Operation.
The switching of two kinds of operating states of character signal generator is that CPU controls by instruction decoder 2, when being in the character show state, MUX 35 is selected B, viewing area write data switch 36 ends, MUX 37 is selected B, character library write data switch 38 ends, and this moment, display buffer 31 and library stores district 32 all were in the state of reading.
Above character show state has produced the character point signal and the character attibute signal that are synchronized with input timing, through follow-up synthetic processing can be on image steady display.
The character programming state is divided into 2 kinds of situations again:
1) to the programming of character library, so that show different character set.
2), make on the screen position of appointment, to show appointment to the programming of display buffer 31
Character.
Programming to character library 32, at first select A by CPU control MUX 37, the character library write address of appointment is connected on the address bus of character library 32,38 conductings of control character library write data switch, the character library write data of appointment is added on the data/address bus in character library district 32, sends character library by CPU then and write enable signal, data designated is written in the unit of library stores district 32 appointments and goes, the multi-pass operation of said process can be finished the programming to whole character library.
When character library is programmed, for prevent that occurring random character on the screen disturbs, and can close character signal in follow-up character attibute control circuit.Because the design of each character repertoire is to organize with the character set that the screen demonstration is comprised by system, each is with all characters in the menu of screen demonstration, be combined in the corresponding character library, therefore change character library and can under replacing menu situation, carry out, close the scintillation that character can not produce character this moment.
Programming to display buffer 31, also be to finish by the method for switching address bus and data/address bus, but can not adopt the above-mentioned method that character shows of closing to the programming of display buffer 31, otherwise can cause that other character that shows with screen produces the light and shade flicker, and CPU is to the random operation of display buffer 31, can interrupt normal character again and show, will cause the interference of the random character of screen.Disturb and flicker for eliminating, the present invention has designed a kind of flyback operation control circuit, guarantees all operations of display buffer 31 is carried out in the flyback of line period.Its principle is: when CPU writes display buffer 31, just offer the address and the data message of display buffer 31 by instruction decoder 2 lockings, do not control MUX 35 and switch 36 actions, enable flyback control circuit 30 subsequently, this circuit is remembered this state, wait in the next horizontal synchronizing pulse arriving, the A channel of gating MUX 35 is also opened switch 36, send write signal simultaneously to display buffer district 31, finish after the write operation, and get back to reset condition immediately, when next line trace is come then, character just shows and is updated.
The speed that CPU is write the display buffer has certain restriction herein, because every row can only write 1 data, for guaranteeing that each data reliably writes in the display buffer district 31, the write operation of CPU should have the interval greater than 1 line period in time, this speed is equivalent to every field energy and upgrades 200～300 characters, can reach subjective live effect.6, visual character attribute control circuit
Fig. 9 is the theory diagram of character attibute control circuit provided by the invention, this circuit has functions such as the control of character background, the insertion of fringing signal, the insertion of character point signal, wherein the control of character point signal comprises that color attribute is selected, character brightness is program control/the character logics such as control of being fade-in fade-out is set automatically.
The color of character is controlled by 2 color attribute position B6, B5 (see figure 4)s in the character code, selects one from 4 colors that preset, and in the alphabet with the screen demonstration, each character can have 4 kinds of colors selections, and under CPU control, these 4 kinds are preset color can be 2
24I.e. combination in any in 16,000,000 looks.Character brightness can be regulated by CPU, and under the different images situation, suitable character brightness both can guarantee clear and legible, can image not exerted an influence because of bright excessively character again.In addition, each character brightness also can have been carried out automatic adjusting respectively according to the mean picture brightness in character position zone among the present invention, to realize best character display effect.The character transparent effect is the occasion of being fade-in fade-out that is used for menu, in character and image light and shade alternation procedure, character should have transparent effect, just in character brightness change procedure, the brightness of the picture signal under the character point signal also changes simultaneously, but the brightness of the two changes in the opposite direction, and luminance factor is complement code each other.
Among Fig. 9, multiplier 101 and MUX 102 are formed low background and are produced circuit.An input of multiplier 101 flows from inputting video data, and another input is the background attenuation coefficient that is preset by CPU.
The video data of multiplier 101 output, its contrast will be lower than the input data, when comprising low background control signal in the character attibute that shows, then control MUX 102 and will select A channels, export this low contrast background signal.
MUX 103 is used to produce character fringing data, under fringing signal controlling from accompanying drawing 6, select A channel in good time, in video data stream, insert character fringing data, the big I of these fringing data is preset at suitable numerical value by CPU, to form best character recognition effect.
MUX 104 is used to insert the character point data, under character point signal controlling from accompanying drawing 6, select the B passage in good time, in video data stream, insert the character point data, the attribute of the data based character display of this character point and cpu instruction control can present different character display effects: the 1) variation of character color; 2) variation of character brightness; 3) character transparency change.
The selection of character color is that their control MUX 108 are selected one as character color from the color that 4 CPU preset by 2 color control bits decision of character attibute.Character brightness is regulated by multiplier 107, and it will obtain required brightness character data from the character color data of MUX 108 outputs and the multiplication of decision character brightness, be inserted in the video data stream through MUX 109 and 104.The coefficient of this decision character brightness can be the character luminance factor that CPU presets, and also can be the respective value in the character position mean picture brightness, and this is that CPU selects by control MUX 106.
Select the B passages when variable connector 106, when promptly selecting character luminance factor that CPU presets, all the brightness of character display will be unified; Select A channel when variable connector 106, when promptly selecting the output of mean flow rate testing circuit, the character luminance factor that joins multiplier 107 will be regulated automatically with the mean flow rate of image, to produce adaptive character brightness data.
The character transparent effect is the occasion of being fade-in fade-out that is used for menu, in character and image light and shade alternation procedure, character should have transparent effect, method is: under CPU control, character signal data and image signal data are weighted summation, among Fig. 9, multiplier 111 and 112 is respectively the weighting multiplier of picture signal and character signal, the two weight coefficient is complement code each other, by CPU control, 2 road signal plus after the weighting, under CPU control, MUX 109 is selected the output of B passage, under the character point signal switches, transparent character signal is inserted in the video data stream.
7, image averaging brightness detects
It is to be the zone with 16 * 16 pixels that mean picture brightness detects, this area image numerical value is carried out arithmetic average, its output valve is corresponding to the size of a last field picture mean flow rate, because image correlation in time, this value can be used as the luminance factor when the front court character.Because mean flow rate is 16 * 16 be surveyed area, so the brightness of each point is constant in each character, the character brightness on the diverse location then is to change and the self adaptation adjusting with locational mean picture brightness separately.
Figure 10 shows the internal structure of mean flow rate testing circuit in the embodiment of the invention, wherein adder 151 is with R, G, B three chromatic numbers are according to addition, its output is considered as in the image brightness value, double port memory 156 addresses are identical with the character display buffer, storage is the accumulated value of 16 * 16 each pixel brightness of zone in the dual port RAM 156, be used for double port memory 156 with door 154 and insert initial value 0 at first pixel of surveyed area, dual port RAM 159 is by controlling write operations with door 158, in the most-significant byte value of last pixel location of surveyed area with the accumulated value of dual port RAM 156, promptly the average brightness in 16 * 16 zones deposits in the dual port RAM 159, because dual port RAM 159 address buss also are identical with the display buffer regional address, so, the image brightness mean value and the character of RAM159 output are synchronous, remove multiplication coefficient with this numerical value as character brightness, can the brightness of Synchronization Control character.
It should be noted that adder 151 inputs except three road RGB data, increased by one road 0FFH constant numerical value, this is to provide minimum value to character brightness multiplication coefficient, and when very low, character still can show with 1/4th high-high brightness with convenient mean picture brightness.
During system design, consider the data synchronization problem, because the two-forty of video data, the pile line operation of data is the effective ways that improve arithmetic speed, but the pile line operation meeting causes the time-delay of data, therefore when image synthesizes with character, should add the synchronizing relay identical, guarantee the continuity of image with inflow line length.
The behavioral illustrations of the above embodiment of the present invention is as follows: 1) character pattern structure: 16 (V) * 16 (H); 2) with screen character display kind: 32 kinds; 3) with screen character color number: 4 kinds; 4) with the screen image background effect: a kind.
Claims (14)
1, multifunctional character superposing display circuit in a kind of Digital Video System, can accept the outer CPU instruction and realize various video character overlaying function, it is characterized in that comprising the cpu instruction decoder 2 that described cpu instruction is decoded, can be according to CPU character signal generator 3, fringing signal generator 4 and visual character attribute controller 1, described character signal generator 3 receive clocks and synchronizing signal output to fringing signal generator 4 with the character signal that produces, and described visual character attribute controller 1 receives the signal of digital rgb signal and 4 outputs of fringing signal generator and exports the digital rgb signal.
2, circuit according to claim 1, it is characterized in that, described character signal generator 3 comprises and is used to deposit the character-coded display buffer 31 that comprises character code and character attibute, be used to deposit the library stores device 32 of character display dot array data, described library stores device 32 is programmable, can include a plurality of character patterns storehouse, each Dot Matrix Library can be switched and load as required.
3, circuit according to claim 1, it is characterized in that, described character signal generator 3 has two kinds of operating states, at the character show state, produce the explicit address that is synchronized with row, field sync signal by sequence circuit, by specific compound mode addressing display buffer 31 and library stores district 32, output character point signal; At the character programming state, take over the address bus and the data/address bus in display buffer 31 and library stores district 32 respectively by outer CPU, to its renewal operation of carrying out data, the switching of described two kinds of operating states of described character signal generator 3 is controlled by instruction decoder 2 by outer CPU.
4, circuit according to claim 1 is characterized in that, described fringing signal generator 4 is invalid and with any one of the position of adjacent 8 directions of this point or produce the fringing signal when point signal is effective more than one in current display dot itself.
5, circuit according to claim 4, it is characterized in that, described fringing signal generator 4 comprises: first line buffer 401, second line buffer 402, first to the 9th character point buffer 403-411, the input of character point signal is at first through 2 line buffers 401, after 402 time-delays, produce the parallel character point signal HD0 of adjacent 3 row, HD1, HD2, three line data are separately again after 3 character point buffer time-delays, each produces 3 adjacent parallel by character point signal P1～P9 of horizontal direction, the character point signal is added the current some P1 point signal of time-delay input and the character attibute data of 2 pixels through 1 row, when showing with the assurance character, its color, background attribute and fringing signal and character point signal are consistent.
6, circuit according to claim 1, it is characterized in that, described character attibute controller 1 comprises background attenuation coefficient multiplier 101, low background control switch 102, fringing signaling switch 103, character point signaling switch 104, mean flow rate detecting unit 105, mean flow rate control switch 106, mean flow rate multiplier 107, character color selected cell 108, transparent control switch 109, adder 110, coefficient of transparency multiplier 111, complement multiplication device 112, complement code generator 113, wherein, background attenuation coefficient multiplier 101 is used for background attenuation coefficient and video input signals carried out multiplying and the result is sent the A input of described low background control switch 102, the B input receiver, video input signal of described low background control switch 102, the output of described low background control switch 102 is connected with the B input of described fringing signaling switch 103, the input of the A input of described fringing signaling switch 103 has the fringing signal and its output is connected to the A input of character point signaling switch 104, the video input signals of 105 pairs of inputs of described mean flow rate detecting unit averages the A input that brightness detected and this detection signal was input to mean flow rate control switch 106, the B input of described mean flow rate control switch 106 receives its output signal of character luminance factor then becomes mean flow rate multiplier 107 respectively with the output signal of character color selected cell 108 two input signals, and the output of mean flow rate multiplier 107 is connected to the A input of transparent control switch 109, the input of complement multiplication device 112, another input of complement multiplication device 112 receives the output of complement code generator 113, described complement code generator 113 is used to produce the complement code of coefficient of transparency, coefficient of transparency multiplier 111 multiplies each other coefficient of transparency and vision signal and consequential signal is input to an input of transparent signal adder 110, another input of described transparent signal adder 110 receives the output signal of described complement multiplication device 112, and the output signal of transparent signal adder 110 is transported to the B input of transparent control switch 109, the output of transparent control switch 109 is connected to the B input of described character point signaling switch 104, and described character color selected cell 108 is used for selecting corresponding color according to the character color position of character attibute from the color parameter that presets.
7, circuit according to claim 6, it is characterized in that, under the low background signal that described low background control switch 102 produces in the background attribute position by character code is controlled, video input signals and the low background coefficient that is provided with by CPU are carried out multiplying, and export ratio is in the video data of low background system.
8, circuit according to claim 6 is characterized in that, described mean flow rate testing circuit 105 comprises: single pixel brightness computing unit is used for the brightness according to this pixel of digital rgb calculated signals of each pixel; The pixel brightness unit that adds up, zone is used for the dateout from described single pixel computing unit is added up; Zone leveling brightness temporary storage location is used for temporary accumulation result data from the described unit that adds up; First control unit is used in described zone first pixel constantly, to the unit zero clearing that adds up of described regional pixel brightness; Second control unit is used in described zone last pixel constantly, and the add up data of unit of described regional pixel brightness are delivered to described zone leveling brightness temporary storage location.
9, circuit according to claim 8, it is characterized in that, described single pixel computing unit comprises adder 151 and removes 4 dividers 152, three inputs of described adder 151 are imported R, G, B signal in the described digital rgb signal respectively, fixed numbers of another input input of described adder 151, the output of described adder is connected to the described input that removes 4 divisions 152, and the described output that removes 4 dividers 152 provides signal to the described regional pixel unit that adds up.
10, circuit according to claim 8, it is characterized in that, the described regional pixel brightness unit that adds up comprises an adder 153, first Double Port Random Memory 156, the first input end mouth input of described adder 153 is from the data of described single pixel brightness computing unit 152, second port input of described adder 153 is from the storage data of described first Double Port Random Memory 156, and the output of described adder 153 is connected to first port of described first Double Port Random Memory 156.
11, mean flow rate testing circuit according to claim 8, it is characterized in that, described zone leveling brightness temporary storage location comprises second Double Port Random Memory 159, wherein first port is a write port, be used to import from the add up most-significant byte of data of unit 156 of described regional pixel, wherein the average brightness of 8 of second port outputs.
12, mean flow rate testing circuit according to claim 8, it is characterized in that, described first control unit comprise one with 154 and one at door or 157, described or the door 157 input area pixel count signals, described output with door 154 is connected second port of described adder 153, described and door 154 first input end and second port of described first Double Port Random Memory 156, described second input with door 154 is connected to output described or door 157, described or door 157 input area pixel count signals.
13, circuit according to claim 8 is characterized in that, described regional pixel count signal can be provided by the low level of level numeral clock signal and vertical digital clock signal.
14, mean flow rate testing circuit according to claim 8, it is characterized in that, described second control unit comprises one and door 158, described with the door 158 input area pixel count signals, the data that described output end signal with door 158 is controlled described second Double Port Random Memory 159 write, and the clock sync signal that the data of described second Double Port Random Memory 159 write or read is the address signal of character buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99117696 CN1284813A (en) | 1999-08-17 | 1999-08-17 | Multifunctional character superposing display circuit in digital video system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99117696 CN1284813A (en) | 1999-08-17 | 1999-08-17 | Multifunctional character superposing display circuit in digital video system |
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| Publication Number | Publication Date |
|---|---|
| CN1284813A true CN1284813A (en) | 2001-02-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99117696 Pending CN1284813A (en) | 1999-08-17 | 1999-08-17 | Multifunctional character superposing display circuit in digital video system |
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| CN (1) | CN1284813A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100399408C (en) * | 2005-09-27 | 2008-07-02 | 友达光电股份有限公司 | Driver and related driving module, display system and electronic device |
| CN100526969C (en) * | 2007-11-12 | 2009-08-12 | 中国科学院长春光学精密机械与物理研究所 | Multifunctional integrated digital picture processing system |
| CN102439559A (en) * | 2011-09-16 | 2012-05-02 | 华为终端有限公司 | Character display method and device |
| CN101753902B (en) * | 2008-12-10 | 2012-05-16 | 晨星软件研发(深圳)有限公司 | Device and method for automatically regulating display information on screen |
| CN104023182A (en) * | 2013-12-16 | 2014-09-03 | 天津天地伟业数码科技有限公司 | Character superimposition device and superposition method based on FPGA |
| CN104469210A (en) * | 2014-11-25 | 2015-03-25 | 冯为心 | Edging method used for SDI high-definition video character superimposition |
| CN107155074A (en) * | 2017-05-17 | 2017-09-12 | 威创集团股份有限公司 | Video Character Superpose method and system |
-
1999
- 1999-08-17 CN CN 99117696 patent/CN1284813A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100399408C (en) * | 2005-09-27 | 2008-07-02 | 友达光电股份有限公司 | Driver and related driving module, display system and electronic device |
| CN100526969C (en) * | 2007-11-12 | 2009-08-12 | 中国科学院长春光学精密机械与物理研究所 | Multifunctional integrated digital picture processing system |
| CN101753902B (en) * | 2008-12-10 | 2012-05-16 | 晨星软件研发(深圳)有限公司 | Device and method for automatically regulating display information on screen |
| CN102439559A (en) * | 2011-09-16 | 2012-05-02 | 华为终端有限公司 | Character display method and device |
| WO2011157250A3 (en) * | 2011-09-16 | 2012-10-11 | 华为终端有限公司 | Character display method and device |
| US8599212B2 (en) | 2011-09-16 | 2013-12-03 | Huawei Device Co., Ltd. | Character display method and apparatus |
| CN102439559B (en) * | 2011-09-16 | 2014-08-06 | 华为终端有限公司 | Character display method and device |
| CN104023182A (en) * | 2013-12-16 | 2014-09-03 | 天津天地伟业数码科技有限公司 | Character superimposition device and superposition method based on FPGA |
| CN104469210A (en) * | 2014-11-25 | 2015-03-25 | 冯为心 | Edging method used for SDI high-definition video character superimposition |
| CN107155074A (en) * | 2017-05-17 | 2017-09-12 | 威创集团股份有限公司 | Video Character Superpose method and system |
| WO2018209824A1 (en) * | 2017-05-17 | 2018-11-22 | 威创集团股份有限公司 | Video character superimposition method and system |
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