CN1282895A - Dual-CPU motherboard with use of single CPU without terminal card - Google Patents
Dual-CPU motherboard with use of single CPU without terminal card Download PDFInfo
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- CN1282895A CN1282895A CN 99111057 CN99111057A CN1282895A CN 1282895 A CN1282895 A CN 1282895A CN 99111057 CN99111057 CN 99111057 CN 99111057 A CN99111057 A CN 99111057A CN 1282895 A CN1282895 A CN 1282895A
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Abstract
A dual-CPU motherboard able to make single CPU run normally without additional terminal card is composed of two CPU sockets, relative peripherals, a terminal device whose one port is connected to the CPU control bus in two CPU sockets and a switch device between power supply and another port of said terminal device. If only one CPU is configured, the said switch device is turned on to make said terminal device play its role.
Description
The present invention relates to a kind of central processing unit (CPU) motherboard, particularly relate to a kind of terminal card that need not install additional and can use the normal two central processing unit motherboards that move of single central processing unit.
When using the central processing unit of intel pentium II (Intel Pentium II) grade, in order to satisfy the requirement of control signal specification, must install terminal resistance additional, and be connected to a terminal voltage source, to guarantee regular event at the two ends of signal wire.
With Pentium II processor, central processing unit itself promptly has one group of terminating circuit, so in use, and existence that also must other one group of terminating circuit.And on being applied in two central processing unit motherboards the time, one group of extra terminating circuit is present on another central processing unit, so can guarantee that action is normal when using two central processing unit.Yet when only using a central processing unit on two central processing unit motherboards, another untapped cpu socket must install the requirement that a terminal card just can meet the control signal specification additional, guarantees that central processing unit is working properly.
For the user, when on two central processing unit motherboards, using single central processing unit, need install a terminal card additional, therefore can cause very big inconvenience.If in the time of on two central processing unit motherboards, using single central processing unit, can use terminal card, then can avoid user's puzzlement.
For this reason, the purpose of this invention is to provide a kind of pair of central processing unit motherboard, can under the situation that need not install terminal card additional, only use a central processing unit job, and guarantee that central processing unit is working properly, avoid making troubles to the user.
For achieving the above object, central processing unit motherboard provided by the invention comprises:
Two cpu sockets that are used to dispose central processing unit, and relevant peripheral unit;
It is characterized in that also comprising:
One end device, one end are coupled on the control bus of above-mentioned two cpu sockets corresponding to central processing unit;
One switch controlling device is disposed between the other end of a supply unit and above-mentioned end device; Wherein, when above-mentioned cpu socket only disposed a central processing unit, above-mentioned switch controlling device will conducting.
Above-mentioned switch controlling device receives a signal specific, and when disposing central processing unit on above-mentioned two cpu sockets, above-mentioned signal specific is positioned at one first level, and above-mentioned switch controlling device is opened circuit; When not disposing central processing unit on above-mentioned any cpu socket, above-mentioned signal specific is positioned at second level, and makes above-mentioned switch controlling device conducting.
Above-mentioned motherboard is from the optional one of above-mentioned two cpu sockets, with its corresponding to the signal of the SLOTOCC# output terminal of central processing unit as above-mentioned signal specific, when disposing central processing unit on the above-mentioned cpu socket, above-mentioned signal specific is a low level, and above-mentioned switch controlling device is opened circuit, when not disposing central processing unit on the above-mentioned cpu socket, above-mentioned signal specific is a high level, and makes above-mentioned switch controlling device conducting.
Above-mentioned motherboard also comprises a logic control device, its input end couples first signal end and the secondary signal end that corresponds respectively to the SLOTOCC# output terminal of two central processing units on above-mentioned two cpu sockets respectively, and output terminal then is coupled to above-mentioned switch controlling device; When above-mentioned two cpu sockets disposed central processing unit, above-mentioned first, second signal was low level, makes the above-mentioned signal specific of above-mentioned logic control device output be positioned at above-mentioned first level, and above-mentioned switch controlling device is opened circuit; When above-mentioned arbitrary cpu socket did not dispose central processing unit, the above-mentioned signal specific of above-mentioned logic control device output was positioned at above-mentioned second level, and makes above-mentioned switch controlling device conducting.
Above-mentioned end device is a resistor chain.
Above-mentioned end device comprises a plurality of resistance, and an end of each above-mentioned resistance all is coupled to above-mentioned switch controlling device, and an other end then is coupled to each signal end on the above-mentioned control bus respectively.
The control bus signal end of above-mentioned two cpu sockets partly is a state in parallel.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by two preferred embodiments, and be described with reference to the accompanying drawings as follows:
Fig. 1 represents the circuit block diagram of the first embodiment of the present invention;
Fig. 2 represents the circuit block diagram of the second embodiment of the present invention.
First embodiment:
Fig. 1 represents the circuit block-diagram of the first embodiment of the present invention.As shown in Figure 1, of the present invention pair of central processing unit motherboard comprises: two cpu sockets 1,2 that are used for disposing central processing unit, and relevant peripheral unit (not shown).
This central processing unit motherboard also comprises: an end device 3, one end are coupled on the control bus of above-mentioned two cpu sockets corresponding to central processing unit; With a switch controlling device 4, be disposed between the other end of a terminal voltage source 5 and above-mentioned end device 3.Again, the control bus of above-mentioned two cpu sockets part is in parallel.
Wherein, in the present embodiment, above-mentioned end device can be made of a plurality of resistor R, and an end of each above-mentioned resistance R all is coupled to above-mentioned switch controlling device 4, and an other end then is coupled to each signal end on the above-mentioned control bus respectively.In addition, above-mentioned end device also can be a resistor chain.Above-mentioned switch controlling device 4 is a nmos pass transistor in this embodiment.Above-mentioned terminal voltage source is 1.5V.
(for example only dispose central processing unit # 1 on cpu socket 1) when above-mentioned cpu socket only disposes a central processing unit, the conducting by the driving of a signal specific of above-mentioned switch controlling device 4 makes above-mentioned end device 3 its effectiveness of performance.
Wherein, with the SLOTOCC# output end signal of cpu socket 2, as above-mentioned signal specific corresponding to central processing unit #2.When disposing central processing unit # 2 on the above-mentioned cpu socket 2, above-mentioned signal specific (being SLOTOCC#) is a low level, and above-mentioned switch controlling device 4 (nmos pass transistor) is opened circuit, and does not so promptly influence the work of normal two central processing units.When not disposing central processing unit # 2 on the above-mentioned cpu socket 2, above-mentioned signal specific is a high level, and makes above-mentioned switch controlling device conducting, and above-mentioned end device 3 can play a role, and guarantees that single central processing unit normally moves.
Embodiment two:
Fig. 2 represents the circuit block diagram of the second embodiment of the present invention.Second embodiment has increased a logic control device 6 than first embodiment; Other device identical with first embodiment is with identical symbolic representation.
Above-mentioned logic control device 6, be one or (OR) gate circuit in this embodiment, its input end couples first signal end (SLOTOCC#1) and the secondary signal end (SLOTOCC#2) of the SLOTOCC# signal output part that corresponds respectively to two central processing unit # 1 and central processing unit # 2 on above-mentioned two cpu sockets 1,2 respectively; Give above-mentioned switch controlling device 4 (also being a nmos pass transistor in this embodiment) and export a signal specific.
When above-mentioned two cpu sockets 1,2 dispose central processing unit, above-mentioned first, second signal (SLOTOCC#1, SLOTOCC#2) is low level " 0 ", so the above-mentioned signal specific that above-mentioned OR circuit is exported is positioned at low level " 0 ", make nmos pass transistor open circuit, like this then do not influence the action of normal two central processing units.
When above-mentioned cpu socket 2 did not dispose central processing unit # 2, the SLOTOCC# 2 signal was positioned at high level " 1 ", and the SLOTOCC#1 signal then is positioned at low level " 0 "; Therefore, the above-mentioned signal specific that above-mentioned OR circuit is exported is positioned at high level " 1 ", makes above-mentioned nmos pass transistor conducting, and above-mentioned end device 3 can play a role, and guarantees that single central processing unit normally moves.
In like manner, when above-mentioned cpu socket 1 did not dispose central processing unit # 1, the SLOTOCC#1 signal was positioned at high level " 1 ", and the SLOTOCC#2 signal then is positioned at low level " 0 "; Therefore, the above-mentioned signal specific that above-mentioned OR circuit is exported is positioned at high level " 1 ", makes above-mentioned nmos pass transistor conducting, and above-mentioned end device 3 can play a role, and guarantees that single central processing unit normally moves.
More than describe the present invention by two preferred embodiments; right its is not in order to limit the present invention; any professional and technical personnel, improvement of being done and replacement without departing from the spirit and scope of the present invention all should be regarded as belonging to protection scope of the present invention.
Claims (7)
1. two central processing unit motherboard comprises: device slot in two centre that are used to dispose central processing unit, and relevant peripheral unit;
It is characterized in that also comprising:
One end device, one end are coupled on the control bus of above-mentioned two cpu sockets corresponding to central processing unit;
One switch controlling device is disposed between the other end of a supply unit and above-mentioned end device; Wherein, when above-mentioned cpu socket only disposed a central processing unit, above-mentioned switch controlling device will conducting.
2. motherboard as claimed in claim 1, it is characterized in that above-mentioned switch controlling device receives a signal specific, when disposing central processing unit on above-mentioned two cpu sockets, above-mentioned signal specific is positioned at one first level, and above-mentioned switch controlling device is opened circuit; When not disposing central processing unit on above-mentioned any cpu socket, above-mentioned signal specific is positioned at second level, and makes above-mentioned switch controlling device conducting.
3. motherboard as claimed in claim 2, it is characterized in that, from the optional one of above-mentioned two cpu sockets, with its corresponding to the signal of the SLOTOCC# output terminal of central processing unit as above-mentioned signal specific, when disposing central processing unit on the above-mentioned cpu socket, above-mentioned signal specific is a low level, and above-mentioned switch controlling device is opened circuit, when not disposing central processing unit on the above-mentioned cpu socket, above-mentioned signal specific is a high level, and makes above-mentioned switch controlling device conducting.
4. motherboard as claimed in claim 2, it is characterized in that, also comprise a logic control device, its input end couples first signal end and the secondary signal end that corresponds respectively to the SLOTOCC# output terminal of two central processing units on above-mentioned two cpu sockets respectively, and output terminal then is coupled to above-mentioned switch controlling device; When above-mentioned two cpu sockets disposed central processing unit, above-mentioned first, second signal was low level, makes the above-mentioned signal specific of above-mentioned logic control device output be positioned at above-mentioned first level, and above-mentioned switch controlling device is opened circuit; When above-mentioned arbitrary cpu socket did not dispose central processing unit, the above-mentioned signal specific of above-mentioned logic control device output was positioned at above-mentioned second level, and makes above-mentioned switch controlling device conducting.
5. motherboard as claimed in claim 1 is characterized in that, above-mentioned end device is a resistor chain.
6. motherboard as claimed in claim 1 is characterized in that above-mentioned end device comprises a plurality of resistance, and an end of each above-mentioned resistance all is coupled to above-mentioned switch controlling device, and an other end then is coupled to each signal end on the above-mentioned control bus respectively.
7. motherboard as claimed in claim 1 is characterized in that, the control bus signal end of above-mentioned two cpu sockets partly is a state in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991110579A CN1157642C (en) | 1999-07-29 | 1999-07-29 | Dual-CPU motherboard with use of single CPU without terminal card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991110579A CN1157642C (en) | 1999-07-29 | 1999-07-29 | Dual-CPU motherboard with use of single CPU without terminal card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1282895A true CN1282895A (en) | 2001-02-07 |
| CN1157642C CN1157642C (en) | 2004-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991110579A Expired - Fee Related CN1157642C (en) | 1999-07-29 | 1999-07-29 | Dual-CPU motherboard with use of single CPU without terminal card |
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| Country | Link |
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| CN (1) | CN1157642C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7917775B2 (en) | 2006-10-18 | 2011-03-29 | Asustek Computer Inc. | Power supply system |
-
1999
- 1999-07-29 CN CNB991110579A patent/CN1157642C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7917775B2 (en) | 2006-10-18 | 2011-03-29 | Asustek Computer Inc. | Power supply system |
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| Publication number | Publication date |
|---|---|
| CN1157642C (en) | 2004-07-14 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040714 Termination date: 20130729 |