CN1280729C - Data access method and device - Google Patents

Abstract

The present invention provides a data access method which is used for accessing data bit streams containing a plurality of figure elements in a memory. The data access method is characterized in that the difference between the writing time serial number and the reading time serial number of data of the same sequence in each figure element is calculated so as to determine the periods of the first quantity that the reading start time of the figure element delays writing start time; the data of all the figure elements is sequentially written into the memory; after all the figure elements begin to write the periods of the first quantity, the data of all the figure elements begins to be read, and thus, the effect of greatly raising the efficiency of data access by using one single memory is achieved.

Description

Data access method and device

Technical field

The present invention relates to a kind of data access method and device, relate in particular to the data access method and the device of picture decoder of a kind of time of effective minimizing data access.

Background technology

In computing machine or communication system now, the multi-medium data of information such as set sound, static animation, literal and dynamic image has become a kind of main data layout.Yet general multi-medium data amount is very huge, thereby medium or communication channel bandwidth are become a very white elephant.So in order to reduce the storage space or the channel width of multimedia storage or transmission usefulness, data compression is in that the stage is played the part of very important role now.

Yet no matter how media data compresses storage in which way, thereafter, and mostly need be before playing compressed multimedia data with previous compress mode inverse conversion to carry out data decompression.As Fig. 1, be the process flow diagram of common dynamic image decoding.At first execution in step 11, with variable-length decoding (variableLength decoder, VLD) mode is tentatively deciphered the video bit stream (video bit stream) that has compressed, and the parameter and the coefficient elder generation row decoding of image come out; Thereafter step 12, in the video bit stream is inverse discrete cosine transform coding (the Inverse discrete cosinetransform of unit with deciphering with 8*8, abbreviation IDCT) coefficient carries out data sorting to revert to the data ordering that does not scan before the compression again through inverse scan (inverse scan is called for short IS); Then, in step 13, will multiply by one group of particular factor through inverse quantization (inverse quantization is called for short IQ) through the IDCT of inverse scan coefficient; In step 14 carry out IDCT thereafter; In step 15, view data is carried out dynamic compensation (motion compensation is called for short MC) so that image smoothing at last.

There is multiple mode in the inverse scan that occurs in step 12.In the general pattern specification, be example with MPEG2, the sequencing table of IS has two kinds of scan modes, respectively as the zigzag scanning (zigzag scan) of Fig. 2 and intermittent scanning (alterna tion scan) as Fig. 3.

Understanding the example of passing the imperial examinations at the provincial level hereinafter for the process that makes scanning and the easier quilt of purpose describes.As Fig. 4, be without the example in the zigzag scanning write store behind the DCT coding, in when coding, the DCT of 8*8 encodes out and has a characteristic to be that big and more upper left than lower right numeral (HFS) the usually numeral of upper left numeral (low frequency part) is most of to be non-0 value.Like this, with the numeral among the Fig. 4 that lines by line scan among Fig. 2, then numeric sorting becomes [61,-3,4,-1,-4,2,0,2,-2,0,0,0,0,0,2,0,0,0,1,0,0,0,0,0,0,-1,0,0,-1,0,0,0,0,-1,0,0,0,0,0,0,0,-1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], most of non-0 value is all close forward, and the major part 0 of lower left is all arranged backward, so that continuous 0 can make the RLE coding can obtain better data compression effect so together.And the digital inverse scan that is sorted when decoding becomes Fig. 2, and the numeral that is about to be sorted begins to write to the lower right corner in the zigzag scanning mode by the upper left corner, and then row one row sequential read is fetched data again, can revert to original not data sequence of scanning.

Like this, need storer to carry out access data and to write/read address-generation unit in the picture decoder to sort again.Usually exist dual mode to finish the function of data access.

First kind provides two storeies (two memory bank), with aforementioned example, each storer can be stored 8*8 block (block) data, according to the address that writes that writes/read address-generation unit output the pattern element data in the video bit stream are write a wherein storer earlier at the beginning at inverse scan, then when next pattern element data continues to write another storer in the video bit stream, then make the address of reading that writes/read address-generation unit output begin to carry out the storer that data read had before write, utilize two storeies to come expedited data to rearrange like this, caused the rising of picture decoder cost and the increase of volume but take more memory block.

The second way is only to utilize an independent storer, according to aforementioned example, this storer can be stored the pattern element data of 8*8 block, as Fig. 5, in this mode write for the first time in W (0) basis write/read address-generation unit with the complete write store of the first picture group case element data in the video bit stream in after, then write/read address-generation unit produce again read that address enable enough carries out the first picture group case element data read R (0), then after these pattern element data R (0) read fully, that could carry out the second picture group case element data again writes W (1).In second kind of usual way, can utilize an independent storer to carry out the data rearrangement, to reach the memory footprint that reduces in the picture decoder and the effect of manufacturing cost, but, significantly increased the time of data rearrangement owing to only there is an independent storer to make fetch program and write-in program need alternately carry out and can't as first kind of usual way, carry out simultaneously.And, when writing data,, and just be 0 originally in some storer because the design of various storeies is different, so only need write non-0 value, making that each pattern element writes data volume N may be less than 64.Writing data volume as previously mentioned may be less than the number of blocks (as 64) of storer, makes in write step and the next read step may life period idlely, and the efficient that data rearrange is then lower.

Therefore, realizing reading and write data if can utilize an independent storer can walk abreast simultaneously, reduce memory footprint, manufacturing cost and take volume except reaching, can also reach and significantly shorten data rearrangement required time and improve data rearrangement efficient.

Summary of the invention

Therefore, an object of the present invention is to provide a kind of data access method and device, with utilize an independent storer, reach dwindle read and write-in program between the effect of standby time.

Another object of the present invention provides a kind of low data access method and device with the low cost of manufacture effect of memory footprint that reach.

A further object of the present invention provides a kind of reaching and improves method and the device that data that data rearrange the efficient effect rearrange.

Thereby, the invention provides a kind of data access method, be used for access and comprise that the data bit stream of a plurality of pattern elements is to storer, described each pattern element has multi-group data and described storer has a plurality of blocks for data corresponding in described each pattern element of access, and described each data write in the described storer corresponding block or are defined as one-period by corresponding block time for reading, and give write time sequence number of described each data in described each pattern element according to the order assignment that writes described storer, and read order assignment according to described each pattern element from described storer and give time for reading sequence number corresponding to said write time sequence number of described each data, described method comprises:

A) the write time sequence number of calculating described each data of same order in described each pattern element and time for reading sequence number difference mutually is with the cycle of first quantity that reads delay said write start time start time that determines this pattern element; And

B) data of described each pattern element are write in the described storer in regular turn, and all after dates of first quantity that begins to write at described each pattern element, promptly begin to read described each pattern element data.

The present invention also provides a kind of data access arrangement, be used for the data bit stream that access memory comprises a plurality of pattern elements, described each pattern element has multi-group data, and described storer has a plurality of blocks for data corresponding in described each pattern element of access, described each data write in the described storer corresponding block and corresponding block time for reading are defined as one-period, and distribute to described each one write time of data sequence number in described each pattern element according to writing described memory order, and read order assignment according to described each data from described storer and give a time for reading sequence number corresponding to said write time sequence number, this device comprises: pattern writes/reads start time generation circuit, be used for receiving in regular turn the write time sequence number and the time for reading sequence number of the same alphabetic data of described pattern unit, and according to the difference mutually between the time for reading sequence number of described same alphabetic data and write time sequence number, the start time of reading of described each pattern element of decision postpones the first quantity cycle that writes the start time of described each pattern element, and described pattern writes/reads the start time and produces circuit cycles ground and produce one and write a commencing signal and a read start signal; Write address-generation unit, be used for writing/read the start time and produce circuit and receive the said write commencing signal and export corresponding a plurality of of described each data in regular turn and write the address so that the data of described video bit stream write described storer from described pattern; And read address-generation unit, be used for from described pattern write/read the start time produce circuit receive export a plurality of described each data behind the said write commencing signal in regular turn respectively read the address to read the data of described video bit stream from described storer.

More knownly only utilize an independent storer need wait for that pattern element data write fully just and can read, and after having read fully, just can carry out writing of next pattern element, present embodiment can significantly shorten data time really, even data access efficiency can reach two times of access efficiency of the independent storer of known application, and the more known mode of utilizing two storeies, present embodiment only need utilize an independent storer can reach the efficient of identical data access (promptly rearranging), make the reduction of the required memory span of picture decoder like this, and then can reach the effect that the memory usage volume descends and cost reduces.

Description of drawings

Further feature of the present invention and advantage, in below with reference to accompanying drawing most preferred embodiment being elaborated, it is clearer to become, in the accompanying drawings:

Fig. 1 is a kind of image decompressor process flow diagram commonly used;

Fig. 2 is the synoptic diagram of a kind of zigzag scanning (zigzag scan);

Fig. 3 is the synoptic diagram of a kind of intermittent scanning (alternation scan);

Fig. 4 is an example schematic of the zigzag scanning of Fig. 2;

Fig. 5 is the sequential chart of data access in storer of the example of Fig. 4;

Fig. 6 is the circuit diagram of most preferred embodiment of the present invention;

Fig. 7 is the process flow diagram of the most preferred embodiment among Fig. 6;

8 figure are example schematic of zigzag scanning;

Fig. 9 is that the example among Fig. 7 subtracts each other chart according to the sequence number of embodiment among Fig. 6; And

Figure 10 is the sequential chart of the example among Fig. 8.

[contrast of assembly label]

2 counters

3 patterns write/read start time generation circuit

30 subtracters

31 sign detection unit

32 comparers

33 read register

35 converters

36 comparers

37 write register

37 write/the read start signal generator

4 totalizers

5 scan conversion windows

6 counters

Embodiment

The present invention is a kind of data access method and device, with independent storer access data under optimum efficiency, to shorten the required time of data access.In the present embodiment, data bit stream is a video bit stream, video bit stream comprises a plurality of pattern elements, each pattern element is made of multi-group data, and give described each one write time of data sequence number b in described each pattern element according to the write store order assignment, and read order according to described each data from described storer and distribute to the time for reading sequence number a of described each data one in regular turn corresponding to said write time sequence number, described data access arrangement combining image code translator different writes and reads order with described writing data into memory or read to utilize in storer, data in each pattern element are rearranged, to reach the purpose of inverse scan (IS).Though it should be noted that in the present embodiment, this data access method system is applied in the picture decoder, yet also can be applicable to the data access of others and to be not limited to present embodiment illustrated.

As Fig. 6, the data access arrangement of present embodiment comprises: counter 2, pattern write/read start time generation circuit 3, totalizer 4, scan conversion window 5 and counter 6.

Described counter 2 is used for beginning in regular turn accumulating values and being input to pattern as write time sequence number b and writing/read the start time and produce circuit 3 from 0, and the group that equals the data that each pattern element has when the number of times of counter 2 accumulating values then resets to 0 when counting and adds up again.But because the data bulk in each pattern element equates and the write time sequence number b of the same alphabetic data of different pattern element can be identical with time for reading sequence number a, make that only need compare a pattern element sequence at the data in the same video bit stream in the present embodiment gets final product, get final product so counter 2 only need be counted an included data set number of a pattern element at a video bit stream.For instance, when if each pattern element has 16 (4*4) group data, then counter 2 exports 0 in regular turn, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 organize the write time sequence number b of data in regular turn as each, write time sequence number b1 as first group of data is 0, second group of data write time, sequence number b2 was 1, the 3rd group of data write time sequence number b3 is 2, write time sequence number b16 to the 16 group of data is 15 by that analogy, then reset to 0 again, so that determine the write time sequence number b of data in each pattern element of next video bit stream.

In general, the storer (not shown) is the matrix block that has with the data bulk equal number of each pattern element, each block can be respectively for making data storage corresponding in each pattern element in wherein, and data described in each pattern element are according to the order that adds up according to write time sequence number b write store in regular turn, and insert in the corresponding block of storer with the scan mode of intermittent scanning etc. as zigzag scanning in described data based original picture coding, and the described data that read the pattern element that deposits in the storer are by the reading of row order (raster-scan) in proper order, so the time for reading sequence number a of each alphabetic data depends on write time sequence number b when reading.In order to be easier to understand, now lift an example explanation, as Fig. 8, for example each pattern element comprises 16 groups of data, and storer 7-4*4 block, in this example, described data are inserted corresponding block in the storer 7 according to the zigzag scanning mode, then in regular turn described data are read when then reading by row, can finish inverse conversion, promptly, the time for reading sequence number a1 of first group of reading of data is 0, the time for reading sequence number a2 of second group of reading of data is 1, the time for reading sequence number a3 of the 3rd group of reading of data is 5, the time for reading sequence number a4 of the 4th group of reading of data is 6, by that analogy, ensuing time for reading sequence number a is 2 in regular turn, 4,7,12,3,8,11,13,9,10,14,15.

Because data must write earlier again and read, even therefore to before the write-in program of a pattern element is not finished, promptly begin the fetch program or do not finish in the fetch program of this pattern element before promptly begin the write-in program of next pattern element, just can read after also must corresponding block data with existing writes in storer or the data in corresponding block could write the data of next pattern element after being read again, it is one-period and the time that writes data also to be one-period that the time of data is read in definition here, the fetch program that therefore must calculate each pattern element could begin to read (promptly by all after dates of first quantity after write-in program begins, described pattern element has write and has equaled could begin reading of data line by line after the first sets of numbers data), and the fetch program that calculates described pattern element all after dates of beginning second quantity could begin to carry out the write-in program (that is, described pattern element read the data that just can carry out next pattern element when equaling second quantity data write) of next pattern element in the video bit stream again.So, in this enforcement, utilize the time for reading sequence number a of each data and write time sequence number b subtracted each other and decide first quantity and second quantity, because with the time for reading sequence number a of each data and after the write time, sequence number b subtracted each other, gained is when subtraction value, that then represents these data reads order too early, the time for reading that means these data surpasses the amount of cycles of answering the write time, and as two sequence number a, when b is kept to the negative value subtraction value mutually, then represent described in next pattern element order data write sequence too early, the write time that means described data surpasses the amount of cycles of time for reading of the same order of last pattern element.

Therefore, the pattern of present embodiment writes/reads start time generation circuit 3 and is used for receiving in regular turn write time sequence number b and the time for reading sequence number a that respectively organizes data, and the beginning time for reading that decides each pattern element according to differing between the time for reading sequence number a of same alphabetic data and write time sequence number b and the beginning write time of next pattern element, avoid not writing situation about promptly reading and take place and read and write the effect that can walk abreast to reach.Each time for reading sequence number a that organizes data decides according to scan pattern (scan pattern) element.The pattern of present embodiment writes/reads the start time and produces circuit 3 and comprise: subtracter (substractor) 30, sign detection unit (sign check unit) 31, comparer (comparator) 32, read register (R-register) 33, converter (converter) 35, comparer 36, write register (W-register) 37 and write/read start signal generator (W/R start signal generator) 34.

Described subtracter 30 receives the time for reading sequence number a that respectively organizes data and the write time sequence number b of a pattern element in regular turn, and the time for reading sequence number a that will write and read the data (first data that for example write with the first group of data that reads) of same order deducts write time sequence number b (a-b).In the present embodiment, discern the time for reading sequence number a of each data for convenience and after the write time, sequence number b subtracted each other on the occasion of or negative value, when subtraction value is timing, then increasing by one in subtraction value is 0 sign bit, and when subtraction value when negative, then increasing by one in subtraction value is 1 sign bit, like this can for subsequent components understand distinguish out subtraction value be on the occasion of or negative value.Those skilled in the art will appreciate that in this definition for sign bit only be for convenience of description, also can set subtraction value certainly is timing, then increase to 1 sign bit, and subtraction value is when negative, then increases to the variation of sign bit of 0 and so on, is not limited to the explanation of present embodiment.

Described sign detection unit 31 receives time for reading sequence number a and the write time sequence number b subtraction value of respectively organizing data from subtracter 30, and the numerical value that utilizes sign bit in the subtraction value respectively organize data comes judged result for just (being that a＞b and sign bit are 0) or bear (a＜b and sign bit are 1), when the time for reading sequence number of judging each data greater than the write time sequence number (during a＞b), then result of calculation is delivered to comparer 32, when the time for reading sequence number small letter angle of incidence sequence number of judging each data (during a＜b), is then delivered to result of calculation converter 35.Though present embodiment utilize 0,1 represent positive and negative, yet that those skilled in the art also can utilize 2 complementations to represent is positive and negative, converter 35 is also got 2 complement code and is changed.

When comparer 32 is received from the time for reading sequence number a of same alphabetic data of sign detection unit 31 and write time sequence number b subtraction value, the big subtraction value of can read from register 33 before the having deposited subtraction value of secondary data is therewith made comparisons, if this subtraction value is during greater than previous big subtraction value, then this subtraction value is delivered to and read register 33 and deposit and replace previous big subtraction value, and when this subtraction value during less than previous maximum result, then read register 33 and continue the previous big subtraction value of storage, continue like this all data of operation in pattern element of relatively depositing all relatively intacter till (for example when pattern element has 16 groups of data, then relatively in 16 groups of data part time for reading sequence number a to deduct write time sequence number b be positive subtraction value), and time for reading sequence number in these data can be stored in greater than the maximal phase depreciation in the write time sequence number and read in the register 33 as first subtraction value.Like this, the collocation that can utilize comparer 32 and this to read register 33 is used, and the time for reading sequence number a and the write time sequence number b that obtain described data subtract each other maximal value.

Reading register 33 is used for storing through the newer subtraction value that enters of comparer 32 and reads the bigger subtraction value of register 33 with before being stored in, and the big subtraction value that can when comparer 32 will compare, provide comparer 32 to read to deposit in the register 33, and after each data of a pattern element of video bit stream are relatively intacter, deliver to as first subtraction value and write/read start signal generator 38 being stored in the big phase difference that reads in the register at last.

Check out subtraction value when sign detection unit 31 and when negative, then subtraction value delivered to converter 35 that converter 35 is delivered to comparer 36 after can removing negative sign in the subtraction value (be sign bit be 1 change into 0) again.

Comparer 36 had read previous big subtraction value comparing with the subtraction value that receives from converter 35 from writing register 37, and in this subtraction value during greater than previous big subtraction value, this subtraction value is delivered to write in the register 37 storage as subtraction value greatly.

Writing register 37 is used to store through the bigger relatively subtraction value of comparer 36 after relatively, and the big phase difference that in good time transmits storage is made comparisons for comparer 36 and the subtraction value that newly enters data, continue like this all data of operation in pattern element of relatively depositing all relatively intacter till (for example when pattern element has 16 groups of data, then relatively in 16 groups of data part time for reading sequence number a deduct write time sequence number b and be negative subtraction value), and write time sequence number b in these data can be stored in greater than the maximal phase depreciation among the time for reading sequence number a and write in the register 33 as second subtraction value.Like this, can utilize converter 35, comparer 36 to use with the collocation that writes register 37, the write time sequence number b and the time for reading sequence number a that obtain described data subtract each other maximal value (i.e. second subtraction value).

Write/read start signal generator 38 is according to deciding first quantity (being the amount of cycles that falls behind fetch program of each pattern element write-in program) and second quantity (being the amount of cycles of fetch program of the last pattern element of write-in program backwardness of next pattern element) from reading register 33 with writing first subtraction value that register 37 receives and second subtraction value respectively, and produce at interval according to first quantity and second quantity and to write commencing signal and read start signal.

At first describe with first quantity, because if only when making first quantity equal the maximal phase depreciation, then having the situation that writes and read with same alphabetic data in one-period takes place, thereby the error that causes data not write promptly to read, for example when equaling write time sequence number b at the time for reading sequence number a of the data that read and write with the one-period planted agent, the situation that data do not write and read will take place, cause the entanglement of data, so write in the present embodiment/first subtraction value that read start signal generator 38 can determine first quantity to equal to read register 33 adds up 1.By that analogy, second quantity second subtraction value that equals to write register 37 adds up 1.

Like this, when write/first and second quantity of read start signal generator 38 decision after, produce one first in advance and write commencing signal to totalizer 4, triggering totalizer 4 then begins to add up from 0, the numerical value that then totalizer 4 is added up output periodically in regular turn is (as 0,1,2,3,4, ..) to scan conversion window 5, the scan pattern that pattern element is arranged in this scan conversion window 5, like this when scan conversion window 5 receives the write time sequence number b of the data that totalizer 4 delivers to, then the control scan pattern determines the address that writes of these data, so that the data of first pattern element can be according to writing the address in regular turn in the write store.For instance, as Fig. 8, suppose that pattern element has 16 groups of data and storer 7 has 16 blocks, and the setting previous coding is the zigzag scanning mode, corresponding address at the described block of described setting storer 7 is added to 15 from 0 from left to right and from top to bottom, and according to zigzag scanning, it is in 0 the block that first group of data of first pattern element of video bit stream (its write time sequence number b is 0) can deposit the address in, it is in 1 the block that second group of data (its write time sequence number b is 1) can deposit the address in, it is in 5 the block that the 3rd group of data (its write time sequence number b is 2) can deposit the address in, by that analogy, can to deposit the address in be in 15 the block to last group data (its write time sequence number b is 15) of last described pattern element.And, write/read start signal generator 38 is at the first all after dates that write at interval first quantity of commencing signal output, export first read start signal thereupon, flip-flop number 6 is exported count results as reading the address since 0 by cycle counting and periodicity, the fetch program of such first pattern element is all after dates of interval write-in program first quantity again, begin reading of data and send by the cycle, and write/read start signal generator 38 again first at interval read start signal second quantity week after date, export second then and write commencing signal, so that the data of second pattern element begin in the write store in the described video bit stream, write/read start signal generator 38 second writes at interval commencing signal first quantity week after date again, export second read start signal then, to carry out the data read of second pattern element, by that analogy, till the pattern element in video bit stream rearranges and finishes.

For the easier quilt of the present invention is understood, cooperate a Fig. 7 and an example to describe hereinafter.

Each pattern element in this example in the video bit stream has 16 groups of data, the write time sequence number b of the described data in each pattern element is 0 in regular turn, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, and these data are accessed in the storer of a 4*4 matrix block in regular turn, and pattern element scans in the zigzag scanning mode, therefore as Fig. 8, these data are that representative is inserted in the described storer 7 corresponding blocks according to the zigzag scanning mode with write time sequence number b, and when reading by the row reading of data, make as shown in Figure 9, the time for reading sequence number a of 16 groups of data is 0 in regular turn, 1,5,6,2,4,7,12,3,8,11,13,9,10,14,15.

At first, as Fig. 7, beginning execution in step 81, calculate and write in the pattern element and the time for reading sequence number a of the group of the i in fetch program data and the subtraction value (being a-b) between write time sequence number b, i is the positive integer that adds up, cooperate Fig. 9, the time for reading sequence number of utilizing subtracter 30 to calculate first group of data deducts the subtraction value (0-0=0) of write time sequence number.

Then step 82 judge described first group of data time for reading sequence number a whether greater than write time sequence number b, promptly whether the phase difference in the step 81 is the positive integer (using sign detection unit 31 to check the sign bit of subtraction value in the present embodiment) greater than 0.If time for reading sequence number a greater than write time sequence number b, then skips to step 83, to form first quantity.Anti-if time for reading sequence number a greater than write time sequence number b, then skips to step 83 ', to form second quantity.

In step 83, utilize phase difference that comparer 32 will organize data and before be stored in the big difference mutually that reads register 33 and make comparisons.When the phase difference of these group data during greater than previous big phase difference, then carry out step 84 and will organize the phase difference of data and be stored in and read in the register 33 as new big phase difference, next organizes the comparison of data otherwise skip to step 85 continuation.Here owing to be first group of data, reset to 0 so read register 33 interior previous phase differences.

In addition, in step 83 ' in utilize converter 35 to eliminate the negative sign (being the digit symbol position) of phase differences in advance, utilize phase difference that comparer 32 will organize data to write making comparisons of register 37 with before being stored in then than difference greatly mutually.When the phase difference of these group data during, then carry out step 84 greater than previous big phase difference ' the phase difference that will organize data is stored in and writes in the register 37 as new big phase difference, next organizes the comparison of data otherwise skip to step 85 continuation.Here owing to be first group of data, also reset to 0 so write register 37 interior previous phase differences.

Then, carry out step 85 add up i (being i+1) and relatively add up after the data set number that whether comprises of i greater than pattern element, if when being not more than, the time for reading sequence number a of the i group data after then rebound step 82 is proceeded to add up compares with the difference mutually between write time sequence number b, promptly carry out second group in regular turn according to abovementioned steps, the 3rd group ... the time for reading sequence number a of the 16 group of data compares with the difference mutually of write time sequence number b, and utilize step 83,84 form peaked first quantity, and utilize step 83 ', 84 ' forms second quantity of minimum value.When the data set that comprises greater than pattern element of the i after relatively adding up was counted n (promptly 16) then, then end loop skipped to step 86.

In step 86, write/read start signal generator 38 produces in regular turn according to first quantity and second quantity and writes commencing signal and read start signal.As shown in Figure 9, first quantity equals 5 and second quantity and also equals 5, write like this/6 the periodic cycle ground outputs in every interval are write commencing signal with read start signal generator 38 and the read start signal branch is clipped to totalizer 4 sum counters 6 till the described pattern element access of video bit stream is intact.

And then in step 87, totalizer 4 is because of writing the address that writes that commencing signal is triggered and makes scan conversion window 5 produce data accordingly in regular turn, and counter 6 because of read start signal begin to count output from 0 add up in regular turn read the address.At last in step 88, the data of video bit stream are deposited in regular turn in the storer 7 and according to reading the address and take out in regular turn according to writing the address.

As mentioned above, as Figure 10, the fetch program R (0) of first pattern element of the video bit stream of this example promptly began to carry out in write-in program W (0) back 6 cycles of beginning, and the write-in program W (1) of second pattern element promptly begins to carry out at 6 all after dates of the fetch program of first pattern element R (0) beginning, by that analogy, 6 cycles are performed at interval for fetch program and write-in program.Like this, with can carry out simultaneously in one-period in the same pattern element different value write data with the time for reading sequence number, as the 7th to ten two cycles among Figure 10, even can be carry out two data write operation and read operations in the different pattern element with one-period, as 17 cycles of the 13 cycle to the among Figure 10.Therefore, present embodiment can reach the effect that data access efficiency (promptly rearranging) efficient significantly promotes really.

Here, write/read start signal 38 in regular turn at interval first and second quantity loop cycle ground output write commencing signal and read start signal, the data that can carry out different sequence numbers in same cycle simultaneously write and read and be unlikely and cause the data entanglement, more knownly only utilize an independent storer need wait for that pattern element data write fully just and can read, and after having read fully, just can carry out writing of next pattern element, present embodiment can significantly shorten data time really, even data access efficiency can reach two times of access efficiency of the independent storer of known application, and the more known mode of utilizing two storeies, present embodiment only need utilize an independent storer can reach the efficient of identical data access (promptly rearranging), make the reduction of the required memory span of picture decoder like this, and then can reach the effect that the memory usage volume descends and cost reduces.In addition, because present embodiment can utilize pattern to write/read the start time after the input of each video bit stream and produce first quantity that circuit 3 calculates pattern element in this video bit stream and export the appropriate intervals time that writes between commencing signal and read start signal with decision with second quantity, therefore no matter be which kind of scan mode to carry out inverse scan with can utilize pattern to write/read the data access that start time generation circuit 3 decides the best, to reach the wide effect of applicability.

Above-described is most preferred embodiment of the present invention, can not limit scope of the invention process with this, and simple equivalent that promptly claim and description are done according to the present invention changes and modifies, and all belongs within the scope that patent of the present invention contains.

Claims (14)

1. data access method, be used for the data bit stream that access memory comprises a plurality of pattern elements, described each pattern element has multi-group data, and described storer has a plurality of blocks for data corresponding in described each pattern element of access, described each data write in the described storer corresponding block and corresponding block time for reading are defined as one-period, and distribute to described each one write time of data sequence number in described each pattern element according to writing described memory order, and comply with described each data and give the time for reading sequence number corresponding to said write time sequence number from the order assignment that described storer reads, this method comprises:

A) the write time sequence number of calculating described each data of same order in described each pattern element and time for reading sequence number difference mutually postpones cycle of first quantity of said write start time with the start time of reading that determines described pattern element; And

B) data of described each pattern element are write in the described storer in regular turn, and all after dates of first quantity that begins to write at described each pattern element, promptly begin to read the data of described each pattern element.

2. also determine the cycle that the start time postpones second quantity that reads the start time of described pattern element that writes of next pattern element data access method as claimed in claim 1, wherein, steps A) according to described phase difference.

3. data access method as claimed in claim 2, also comprise step C) begin all after dates of second quantity of reading of data at described storer, order is close to described each data in the next pattern element of described pattern element according to being stored in corresponding to the write time sequence number in the described storer in the corresponding block in described data bit stream, and step D) repeating step B) with step C) until described video bit stream all till described storage access.

4. first quantity data access method as claimed in claim 1, wherein, steps A) deducts the greatest measure decision in the difference of write time sequence number according to the time for reading sequence number of described each data of same order.

5. the greatest measure that the time for reading sequence number that first quantity data access method as claimed in claim 4, wherein, steps A) equals described each data of same order deducts in the difference of write time sequence number adds 1 numerical value.

6. second quantity data access method as claimed in claim 2, wherein, steps A) deducts the greatest measure decision in the difference of time for reading sequence number according to the write time sequence number of described each data of same order.

7. the greatest measure that the write time sequence number that second quantity data access method as claimed in claim 6, wherein, steps A) equals described each data deducts in the difference of time for reading sequence number adds 1 numerical value.

8. data access arrangement, be used for the data bit stream that access memory comprises a plurality of pattern elements, described each pattern element has multi-group data, and described storer has a plurality of blocks for data corresponding in described each pattern element of access, described each data write in the described storer corresponding block and corresponding block time for reading are defined as one-period, and distribute to described each one write time of data sequence number in described each pattern element according to writing described memory order, and read order assignment according to described each data from described storer and give a time for reading sequence number corresponding to said write time sequence number, this device comprises:

Pattern writes/reads start time generation circuit, be used for receiving in regular turn the write time sequence number and the time for reading sequence number of the same alphabetic data of described pattern element, and postpone the first quantity cycle that writes the start time of described each pattern element according to the difference mutually between the time for reading sequence number of described same alphabetic data and write time sequence number, the start time of reading of described each pattern element of decision, and described pattern writes/reads the start time and produces circuit cycles ground and produce one and write a commencing signal and a read start signal;

Write address-generation unit, be used for writing/read the start time and produce circuit and receive the said write commencing signal and export corresponding a plurality of of described each data in regular turn and write the address so that the data of described video bit stream write described storer from described pattern; And

Read address-generation unit, be used for from described pattern write/read the start time produce circuit receive export a plurality of described each data behind the said write commencing signal in regular turn respectively read the address to read the data of described video bit stream from described storer.

9. data access arrangement as claimed in claim 8, wherein, described pattern writes/reads start time generation circuit and comprises:

Subtracter is used for receiving in regular turn the write time sequence number and the time for reading sequence number of described each data of the same order of described pattern element, and the subtraction value that in regular turn the time for reading sequence number of same alphabetic data is deducted time for reading sequence number gained is sent;

The sign detection unit is used in regular turn receiving subtraction value from described subtracter, and judge described subtraction value on the occasion of or negative value send then;

First comparing unit, be used in regular turn receiving from described sign detection unit through be judged as on the occasion of subtraction value, and relatively select the maximal phase depreciation as first subtraction value; And

Write/the read start signal generator, be used for when when described first comparing unit receives first subtraction value, determine first quantity according to described first subtraction value, and beginning produce circularly write commencing signal and with interval time of said write commencing signal be the read start signal in the first quantity cycle so that described pattern element is accessed in the described storer in regular turn till described each pattern element all has been accessed in described storer.

10. data access arrangement as claimed in claim 9, wherein, described first comparing unit comprises comparer and reads register, described comparer be received as from described sign detection unit on the occasion of subtraction value with read the previous big subtraction value that register reads and made comparisons from described, and the subtraction value of described sign detection unit is stored in after relatively big the described register that reads with as subtraction value greatly.

11. data access arrangement as claimed in claim 9, also comprise second comparing unit, be used for receiving from described sign detection unit in regular turn through being judged as the subtraction value of negative value, and convert on the occasion of outputing to said write/read start signal generator after as second subtraction value relatively to select the maximal phase depreciation, so that said write/read start signal generator determined for the second quantity cycle according to described second subtraction value, said write/read start signal generator makes the next one write the commencing signal output time when circulation output said write commencing signal and described read start signal to postpone the described second quantity cycle of read start signal then.

12. data access arrangement as claimed in claim 11, wherein, described second comparing unit comprises converter, comparer and writes register, the subtraction value that described converter will be received as negative value from described sign detection unit converts on the occasion of outputing to described comparer, and described comparer is made comparisons the subtraction value of described converter and the subtraction value of described converter is stored in after relatively big the said write register with as subtraction value greatly with the previous big subtraction value that reads from the said write register.

13. data access arrangement as claimed in claim 9, wherein, said write/read start signal generator adds one to produce described first quantity with first subtraction value of described first comparing unit.

14. data access arrangement as claimed in claim 11, wherein, said write/read start signal generator adds one to produce described second quantity with second subtraction value of described second comparing unit.

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