CN1275331C - Semiconductor device with reduced line-to-line capacitance and cross talk noise - Google Patents

Semiconductor device with reduced line-to-line capacitance and cross talk noise Download PDF

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Publication number
CN1275331C
CN1275331C CNB018189377A CN01818937A CN1275331C CN 1275331 C CN1275331 C CN 1275331C CN B018189377 A CNB018189377 A CN B018189377A CN 01818937 A CN01818937 A CN 01818937A CN 1275331 C CN1275331 C CN 1275331C
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grid
base material
line
source electrode
drain
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CN1475034A (en
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M·赫兹曼
K·威克索瑞克
F·N·豪斯
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor device (200) is disclosed, having an insulating material disposed between the gate electrode (204) and the drain and source lines, wherein the dielectric constant of the insulating amterial is 3.5 or less. Accodingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor (200) with decreased cross talk noise.

Description

Through reducing the semiconductor device of line capacitance and crosstalk noise
Technical field
The present invention relates to VLSI (very lagre scale integrated circuit (VLSIC) semiconductor device), particularly relate to (line-to-line) electric capacity and cross-talk (cross talk) noise between the line in the semiconductor device of super-high density circuit.
Background technology
The manufacture process of integrated circuit (IC) relates to the manufacturing of many semiconductor device, the transistor of insulated gate field-effect on for example single base material.Be integration density and the improved device performance with raising, for instance, for signal processing time and power loss, the parts of semiconductor device (feature) size stably reduces.The part dimension that reduces has various advantages, for example high packaging density and between transistorized transfer period since the time of (signal of telecommunication) lifting that the channel length that shortens causes shorter.Yet when further reducing as if part dimension, this type of advantage may be subjected to offseting as higher interconnection resistance and the shortcomings such as coupling capacitance between adjacent lines.Moreover the resistance of raising and/or capacitive coupling also can make along the electric signal speed of this connector conduction slows down.This generally can be described as interconnect delay (interconnect delay).
By and large, at part dimension, for example, grid length, be in the device of 0.18 μ m magnitude, interconnect delay begins to dominate integral device to postpone, so 0.18 μ m and littler device component will cause the device performance that fails, therefore will limit, for example, the clock frequency of CPU (central processing unit).In the modern super-high density circuit, not only interconnect delay is an important problem, and the formation of local interconnect, promptly in order to the drain electrode of connection field-effect transistor and the cross tie part of source region also is.In the design standard of modern integrated circuits, for example, in super-high density CMOS (complementary metal oxide semiconductors (CMOS)) circuit, require to have between grid and the local interconnect small distance between 10 to 250nm.When if slight misalignment takes place when forming the perforate of indivedual local interconnect, this type of distance even shorter again.
See for clear, the typical prior art flow process be described, and with reference to figure 1a and 1b with related subproblem in the formation of the cross tie part that is described in detail in modern integrated circuits.Those skilled in the art is easy to understand, illustrates that the figure of prior art processing is a skeleton diagram, and the tangible transition (district) in the true device may not be represented on transition (district) that shows with tangible line and border.And the accurate manufacture process of explanation index of typically existing technological process and do not point out to be used for the canonical parameter value of these processes is because single procedure of processing can be specifically related to requirement to satisfy by corresponding improvement.
The summary generalized section of the field-effect transistor device when Fig. 1 a shows concrete fabrication stage.In semiconductor substrate 1, define transistor area with the shallow insulation layer (trans-isolations) 2 of striding.Grid 4 forms on base material 1 and is isolated by gate insulator 3.Near gate insulator 3, form light doping section 5.Those skilled in the art will understand that this grid 4 can be formed by DUV (deep UV) mask technique, then, be implanted by ion and will form light doping section 5.
Fig. 1 b roughly shows the generalized section of the field-effect transistor of more advanced fabrication stage.Sidewall spacer 7 forms and extends along this transistorized width, and this direction is defined as direction perpendicular to the graphic plane of Fig. 1 b, makes the sidewall of contiguous this grid 4.On the other hand, the lateral dimension of this grid 4 is often referred to long limit.For example, the width of this grid 4, that is, the distance between the sidewall spacer 7 shown in Fig. 1 b is often referred to this transistorized grid length.In addition, form drain electrode and source region 6.The formation of this sidewall spacer 7 can be by silicon dioxide or silicon nitride or silicon oxynitride layer deposition and the execution of anisotropic etching subsequently.The dielectric constant k of this type of material between 3.9 to 6, decides on the type of used depositing operation usually.Form after this sidewall spacer 7, form the high doped source electrode by ion implantation and rapid thermal annealing well-known to those having ordinary skill in the art.
Fig. 1 c shows the summary generalized section of the transistor device of another advanced fabrication stage.The interbed of dielectric material 8 forms on this structure and comprises and partly expose the drain electrode and the perforate 9 on source electrode surface at least respectively.The typical process flow that forms this perforate 9 and interbed 8 is commonly referred to as local interlinkage (LI) process sequence, comprises following steps usually.At first, utilize chemical vapor deposition (CVD) with TEOS (tetraethoxy silicate) deposition of dielectric materials interbed (ILD) 8.Then, the surface of this ILD 8 complanation by chemico-mechanical polishing (CMP).Afterwards, form the perforate 9 that is through hole (vias) or line (lines) form by standard masks and etching technique.Substantially, can see slight misalignment during this perforate 9 forms, so this perforate 9 to the distance of this grid 4 all can't accurately reach consistent usually by Fig. 1 c.
Fig. 1 d roughly among the displayed map 1c perforate 9 fill up metal, tungsten for example, transistor device be connected to being electrically connected of this drain electrode and source region 6 so that provide.Then, carrying out another CMP technology flattens the metal in this ILD8 and this perforate 9.Those skilled in the art will understand can be before metal fills up perforate 9 the barrier layer (not shown) of deposition of thin.
Distance between the metal in modern super-high density semiconductor circuit in grid 4 and the perforate 9 between 20 to 250nm.This distance even also can be littler, the misalignment of any magnitude that is taken place during forming according to perforate 9 is decided.Distance between the parasitic capacitance that forms between this metal and this grid and this metal and this grid is inversely proportional to, and therefore, the time constant of switching transistor will shorten and increase along with distance between this metal and this grid.And the crosstalk noise between drain electrode and the source region also will be along with distance shortens and increases.As a result, in the super-high density semiconductor circuit, stably shorten transistor length, promptly, grid length, the benefit that is obtained have at least part to be offseted by the distance that shortens between source electrode and drain line and the grid, therefore cause the parasitic capacitance and the crosstalk noise of increase.
Look back the above, need to have between drain electrode and source region and the grid improvement field-effect transistor of low electric capacity to improve the device performance of super-high density semiconductor circuit.
Invention discloses
According to one embodiment of the invention, one field-effect transistor is set in the integrated circuit on being formed on base material, this field-effect transistor includes along the grid of the opposing sidewalls of this transistor width direction extension, this grid forms on base material and is separated by gate insulator and base material, the drain line that forms to small part in the drain region, this drain line is electrically connected to this drain region, the source electrode line that forms to small part in the source region, this source electrode line is electrically connected to this source electrode, this drain line and this source electrode line electric insulation and by being separated by sidewall spacer with this grid, this sidewall spacer comprises that dielectric constant is equal to or less than 0.35 material.
According to one embodiment of the invention, one field-effect transistor is set in the integrated circuit on being formed on base material, this field-effect transistor includes along the grid of the opposing sidewalls of this transistor width direction extension, this grid forms on base material and is separated by gate insulator and base material, the drain line that forms to small part in the drain region, this drain line is electrically connected to this source electrode, this drain line to small part forms on the drain region, the source electrode that forms to small part in the source region, this source electrode line is electrically connected to this source electrode, this drain line and this source electrode line are electric insulation and are separated by sidewall spacer with this grid, the wherein ratio of the distance between drain line and this grid and the dielectric constant of this sidewall spacer, and the distance between this source electrode line and this grid all is equal to or less than 0.35nm with the ratio of the dielectric constant of this sidewall spacer -1
According to yet another embodiment of the invention, the method of one manufacturing field-effect transistor is provided, comprise the steps: to provide one surperficial base material is arranged, in this base material, form the active region, on this base material, form grid, this grid forms electric insulation by gate insulator and base material, formation is adjacent to the dielectric sidewall spacer of this grid and extends along this grid according to this transistorized Width, this sidewall is equal to or less than 3.5 material by dielectric constant and forms, in being adjacent to the active region of this grid, form drain electrode and source electrode, depositing insulating layer on this base material, respectively, form perforate in drain electrode and source region to small part, fill up this perforate to form drain line and source electrode line with conductive material, wherein this sidewall spacer helps to isolate on electric insulation between this grid and this drain line and this source electrode line and the space.
Because the electric capacity between this drain region or this source region and this grid depend on this sidewall spacer dielectric constant " k " and and this drain line or this source electrode line and this grid between be partitioned into inverse ratio, can obtain by the sidewall spacer that low-k materials forms to compensate effectively by this electric capacity that reduces described distance and increase in the super-high density semiconductor circuit.Opposite with the device that comprises the sidewall spacer that forms by silica, silicon nitride or the silicon oxynitride of dielectric constant between 3.9 to 6 in the prior art, the invention provides by the field-effect transistor of dielectric constant between 3.5 sidewall spacers of making to the material below 1.3.Therefore, the present invention can make transistor device subtract forr a short time, thereby avoids by between grid that improves and the source electrode and/or the electric capacity between grid and the drain electrode and crosstalk noise and cause the decline of device performance.
The accompanying drawing simple declaration
By following detailed description contrast accompanying drawing, can make other advantage of the present invention more apparent, wherein:
Fig. 1 a roughly shows the profile of the field-effect transistor of a concrete fabrication stage;
Fig. 1 b roughly shows the profile of field-effect transistor device in the advanced fabrication stage, and this figure illustrates the sidewall spacer that forms according to typical existing technology;
Fig. 1 c roughly shows the deposition of dielectric materials interbed and form the profile of perforate field-effect transistor afterwards in this dielectric material interbed;
Fig. 1 d roughly is presented at the profile of the field-effect transistor of the fabrication stage that forms drain electrode and source electrode line in the perforate of interbed illustrated among Fig. 1 c;
Fig. 2 a roughly shows the profile according to the field-effect transistor of one concrete fabrication stage of the present invention; And
Fig. 2 b roughly the field-effect transistor of displayed map 2a at another advanced fabrication stage midship section figure.
Although the present invention is illustrated with reference to the specific embodiments of explanation in following detailed description and accompanying drawing, but understanding following detailed description and accompanying drawing can't make the present invention be limited to the specific embodiments that is disclosed, described specific embodiments is each embodiment of illustration the present invention only, and scope of the present invention is defined by claim.
Execution mode
To make other advantage and purpose of the present invention more apparent by following detailed description and claim.And, although noting the present invention's contrast as the described specific embodiments of following detailed description is illustrated, but understanding following detailed description can't make the present invention be limited to that this specific specific embodiments discloses, described specific embodiments is each embodiment of illustration the present invention only, and scope of the present invention is defined by claim.
Fig. 2 a roughly shows the profile according to the field-effect transistor 200 of a specific fabrication stage of the present invention.Among Fig. 2 a, shallow trench isolation layer 202 is formed in the base material 201, and this base material 201 can be a suitable semiconductor substrate, for example silicon or insulating properties base material, and glass for example, and define the active region of this transistor 200 by this base material 201.In the active region of this transistor 200, form drain electrode and the source region 206 of containing lightly doped region 205.Grid 204 is positioned on the active region of this transistor 200 and via gate insulator 203 and this transistor 200 isolates.Sidewall spacer 207 forms and extends along the Width of this transistor 200 along the respective side walls of this grid 204.
The illustrated technological process that is used to form the parts of this field-effect transistor 200 can comprise following step as Fig. 2 a.After the standard grid forms, for example illustrated with reference to Fig. 1 a to 1d, to implant by ion and to form after the lightly doped region 205, this sidewall spacer 207 is equal to or less than 3.5 material by dielectric constant and deposits and form.The material that is applicable to sidewall spacer 207 comprises oxygen silicon fluoride (F-SiO 2K=2.6 to 3.5), hydrogen silicon silsequioxane (hydrogensilsesquioxane, HSQ), fluorinated polyimide, Parylene, poly-naphthalene, polytetrafluoroethylene (p-TFE), methyl silicon silsequioxane (methylsilsesquioxane, MSQ), perfluor cyclobutane, nano-stephanoporate silicon dioxide (nano porous silica) and blend together silicon silsequioxane (hybrid silsesquioxane).HSQ and fluorinated oxide have 3.0 and 3.5 k value respectively, yet organic polymer such as Parylene have the k value below 3.0.The k value greater than 2.0 nano-stephanoporate silicon dioxide film, porous matter polymer and P-TFE arranged.This type of low-k materials can by, for example, plasma fortified CVD or high-density plasma CVD deposition.Because the type of depositing operation all can influence the k value that is deposited layer usually, so the low k value of each of certain material all can be by using different deposition processs or being obtained by the parameter value that changes this deposition process, this knows from process as first pre-spacer material such as silica.
Fig. 2 b is the field-effect transistor 200 of advanced fabrication stage among the displayed map 2a roughly.Above grid 204 and this sidewall spacer 207, form insulating barrier 208, drain electrode and source electrode line 210 are adjacent to this insulating barrier.This drain electrode and source electrode line 210 can form the form of guide hole, circuit or the two combination, need to decide on design.As above-mentioned pointed, this drain electrode and source electrode line 210 also can be described as local interconnect.
With reference to Fig. 1 a to 1d, insulating barrier 208 is formed on this structure, and is flattened then as above-mentioned, and forms the opening 209 that part exposes drain electrode and source area 206.Afterwards, but the barrier layer (not shown) of deposition of thin, and for example cobalt silicide or titanium silicide layer are to cover the surface of perforate 209.Then, with metal, for example tungsten is filled in this perforate 209, makes the structural planization of gained again with CMP.Distance between grid 204 and drain electrode or the source electrode line 210 also is called distance ' ' d ' ', on being used to drain and the perforate 209 of source electrode line 210 alignment accuracy during forming is decided.Because what the transistor length size was stable reduces, so the distance 211 in the modern integrated circuits is usually between 10 to 250nm, when certain degree misalignment takes place even littler.
Electric capacity between grid 204 and drain electrode and the source electrode line 210 is proportional to k/d, wherein the dielectric constant of " k " material between source electrode and drain line 210 and grid 204.Notice that the k/d ratio must multiply by electric field constant ε 0(8.8542 * 10 -12As/Vm) could obtain absolute value.Therefore, the distance ' ' d ' ' that shortens according to the present invention is used the deterioration that can not cause this transistor device performance as the littler distance ' ' d ' ' of prior art thus by lower " k " value compensation.For the type of the material type of low-k materials and/or depositing operation can be through selecting with " k " value of regulating sidewall spacer 207 so that the ratio of " k " of source electrode line value and distance ' ' d ' ', and the ratio of " k " value of drain line and distance ' ' d ' ' all is equal to or less than 0.35nm -1, or when using absolute value, be approximately equal to or less than 3.099 * 10 -3As/Vm 2This expression the present invention suggestion, for example, minimum range " d " be equal to or less than 3.5 dielectric material for 10nm needs " k " value, and distance ' ' d ' ' is that 8nm needs " k " value is 2.8 material, or the like.Therefore, according to the present invention, to the assigned voltage of the grid, drain electrode and the source electrode that put on this field-effect transistor, can select " k " value of this sidewall spacer material to make and be equal to or less than 3.099 * 10 for the electric capacity between minimum range " d ", grid and the drain electrode of depending on design standard and technology accuracy and the source electrode line 210 -3As/Vm 2
And, be to be used to drain and the metal of source electrode line 210 although the present invention has illustrated tungsten, yet, note any suitable material, as copper, aluminium etc., also can use.Moreover the present invention is equal to or less than in the transistor device of 0.2 μ m particularly useful at grid length, because this type of transistor device has 250nm or littler line and gate distance usually.
Although the present invention is with reference to semiconductor substrate, as silicon, the field-effect transistor of last formation and being illustrated will notice that the present invention also can be applicable to any field-effect transistor that forms on any suitable base material.For example, the form that this field-effect transistor can SOI (covering silicon on the oxide) device forms, and maybe can be formed at the insulating properties base material or as on other semiconductor substrates such as III-V or II-VI semiconductor.
Above-mentioned specific embodiments is only for explanation, and the present invention is can those skilled in the art known and have benefited from difference taught herein but the method correct and the realization of equivalence.For example, above-mentioned procedure of processing can be carried out according to different order.Moreover, except following claim illustrated, construction or design shown in this article is restriction not.Therefore clearly, more than the specific embodiments of Jie Shiing can change or revise, and all these type of variations all are contained in scope of the present invention and the spirit.Therefore, the scope such as the presenter of claim institute of the protection of this paper institute desire.

Claims (10)

1. a field-effect transistor device (200), it is arranged in the integrated circuit of manufacturing on the base material, and it comprises:
One grid (204), it contains the opposing sidewalls of extending along the Width of described transistor (200), and described grid (204) forms in base material (201) top and is isolated by gate insulator (203) and base material (201);
One drain line, it has at least part to form above the drain region, and described drain line is electrically connected to described drain region; And
The one source pole line, it forms at least partially in the top, source region, described source electrode line is electrically connected to described source region, described drain line and source electrode line are by isolating on a sidewall spacer (207) and described grid (204) electric insulation and the space, described sidewall spacer (207) is equal to or less than 3.5 material by dielectric constant to be formed, and described material is selected from by the oxygen silicon fluoride, hydrogen silicon silsequioxane, fluorinated polyimide, Parylene, poly-naphthalene, polytetrafluoroethylene, methyl silicon half an oxygen alkane, the perfluor cyclobutane, nano-stephanoporate silicon dioxide and blend together the group that silicon sesquialter alkylene oxide is formed.
2. field-effect transistor device as claimed in claim 1, wherein, the length of described grid is less than 0.2 μ m.
3. field-effect transistor device as claimed in claim 1, wherein, described drain line and described source electrode line comprise a kind of in tungsten, aluminium and the copper.
4. field-effect transistor device as claimed in claim 1, wherein, described base material (201) is a semiconductor substrate.
5. field-effect transistor device as claimed in claim 1, wherein, electric field constant ε 0And the product of the ratio of distance is equal to or less than 3.099 * 10 between the dielectric constant of described sidewall spacer (207) and described drain line and the described grid -3As/Vm 2, and described electric field constant ε 0And the product of the ratio of distance is equal to or less than 3.099 * 10 between the dielectric constant of described sidewall spacer (207) and described source electrode line and the described grid -3As/Vm 2
6. method of making field-effect transistor, it comprises the steps:
Preparation has the base material (201) on surface;
In described base material (201), form an active region;
Go up formation grid (204) at described base material (201), described grid (204) forms electric insulation by gate insulator (203) and described base material (201);
Formation is adjacent to the dielectric sidewall spacer (207) of described grid (204) and extends along described grid according to described transistorized Width, described sidewall spacer (207) is equal to or less than 3.5 material by dielectric constant to be formed, and described material is selected from by oxygen silicon fluoride, hydrogen silicon sesquialter alkylene oxide, fluorinated polyimide, Parylene, poly-naphthalene, polytetrafluoroethylene, methyl silicon sesquialter alkylene oxide, perfluor cyclobutane, nano-stephanoporate silicon dioxide and blendes together the group that silicon sesquialter alkylene oxide is formed;
In being adjacent to the active region of described grid, form drain electrode and source electrode;
Go up depositing insulating layer (208) at described base material (201);
Form perforate in described drain electrode and source region to small part respectively; And
Fill in described perforate to form drain line and source electrode line with conductive material, wherein, described sidewall spacer (207) helps to isolate on electricity isolation between described grid and described drain line and described source electrode line and the space.
7. profit requires 6 described methods, and wherein, the length of described grid (204) is less than 0.2 μ m.
8. method as claimed in claim 6, wherein, described drain line and described source electrode line comprise a kind of in tungsten, aluminium and the copper.
9. method as claimed in claim 6, wherein, described base material (201) is a semiconductor substrate.
10. method as claimed in claim 6, wherein, described base material is the insulating properties base material.
CNB018189377A 2000-11-16 2001-10-04 Semiconductor device with reduced line-to-line capacitance and cross talk noise Expired - Fee Related CN1275331C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10056868A DE10056868A1 (en) 2000-11-16 2000-11-16 Semiconductor device with reduced line capacitance and reduced crosstalk noise
DE10056868.8 2000-11-16
US09/812,372 2001-03-20
US09/812,372 US6555892B2 (en) 2000-11-16 2001-03-20 Semiconductor device with reduced line-to-line capacitance and cross talk noise

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Publication Number Publication Date
CN1475034A CN1475034A (en) 2004-02-11
CN1275331C true CN1275331C (en) 2006-09-13

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US5882983A (en) * 1997-12-19 1999-03-16 Advanced Micro Devices, Inc. Trench isolation structure partially bound between a pair of low K dielectric structures
US6107667A (en) * 1998-09-10 2000-08-22 Advanced Micro Devices, Inc. MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions
US6271132B1 (en) * 1999-05-03 2001-08-07 Advanced Micro Devices, Inc. Self-aligned source and drain extensions fabricated in a damascene contact and gate process
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CN1475034A (en) 2004-02-11

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