CN1272703C - Processor and method for aligning block by automatic command pattern conversion - Google Patents
Processor and method for aligning block by automatic command pattern conversion Download PDFInfo
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- CN1272703C CN1272703C CN 03133082 CN03133082A CN1272703C CN 1272703 C CN1272703 C CN 1272703C CN 03133082 CN03133082 CN 03133082 CN 03133082 A CN03133082 A CN 03133082A CN 1272703 C CN1272703 C CN 1272703C
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Abstract
The present invention relates to a processor and a method for aligning blocks by the conversion of an automatic instruction mode. An instruction operated by the processor comes from an instruction boundary with L bit element length, and the L bit element instruction boundary can contain an M bit element instruction or a plurality of N bit element instructions. When the taken L bit element block is an M bit element instruction, and the previous L bit element block is an N bit element instruction, if the N bit element instruction has a corresponding M bit element instruction, the N bit element instruction is converted into a corresponding M bit element instruction, and if the N bit element instruction does not have the corresponding M bit element instruction, at least one NOP instruction of the N bit element is inserted behind the N bit element instruction.
Description
Technical field
The invention relates to the technical field of processor, refer to especially a kind of in multimode instruction with automatic command mode switch the align processor and the method for word group.
Background technology
General multimode instruction processing unit has the instruction mode of 32 bits and 16 bits, and can carry out in these two kinds of mode switch, store required space to save procedure code, in U.S. USP 5,758, in No. 115 patent announcements, be with programmable counter (Program Counter, PC) the T bit in is positioned at 32 bits or 16 bit instruction modes to determine this preparation implement, and the value of utilizing branch (Branch) instruction to come T bit in the changeover program counter, its instruction mode switches as shown in Figure 1, when carrying out branch (Branch) instruction 220, the initial address Badd (1) that branch to (Branch to) 16 bits instruction stores also carries out the instruction of 16 bits, be somebody's turn to do the+1st, be positioned at 16 bit instruction modes to indicate this processor in order to switch this T bit, when carrying out branch (Branch) instruction 240, the address Badd (2) that branch to (Branch to) 32 bits instruction stores also carries out the instruction of 32 bits, should+0 be in order to this T bit is changed into ' 0 ', to indicate this processor to be positioned at 32 bit instruction modes, take this kind changing method that the processor of ARM and MIPS series is arranged, yet take the 32 bits instruction of this kind changing method and the instruction of 16 bits need be stored in different blocks respectively, instruction of 32 bits and the instruction of 16 bits can't be mingled with leaves same block in, therefore the procedure code storage area can't obtain optimization, not only can't obtain optimization in the procedure code storage area so plant changing method, when switching again simultaneously, also increase required storage area.
Can't be mingled with the problem that is stored in same block at instruction of 32 bits and the instruction of 16 bits, in U.S. USP 6,209, in the 079B1 patent announcement, be with (the MostSignificant Bit of most significant digit unit in the order code, MSB) decide this preparation implement to be positioned at 32 bits or 16 bit instruction modes, 32 bits instruct and the instruction of 16 bits can't be mingled with the problem that is stored in same block to solve, as shown in Figure 2, if if in the MSB ' 1 ' on 32 bit borders, then this 32 bit is represented the instruction of one 32 bits, if if in the MSB ' 0 ' on 32 bit borders, then this 32 bit is represented two 16 bit instructions, if if the MSB ' 0 ' of 16 bits instruction B, then be expressed as two 16 bits instructions of carrying out in proper order, if if the MSB ' 1 ' of 16 bits instruction B, 16 bits that then are expressed as two parallel execution refer to the present, take this kind changing method that the processor of M32R series is arranged, take the instruction of 32 bits and the instruction of 16 bits of this kind changing method to need not to be stored in respectively different blocks, can reach the purpose that improves procedure code density (Code Density), yet when taking this kind changing method, need handled when carrying out branch (branch) or jumping (jump) instruction, in order to avoid jump to the latter part of one 32 bits instruction, because the latter part of this 32 bit instruction is not an executable instruction, can produce the mistake that to expect, therefore the address that jumps need be limited in block boundary (word boundary) or 32 bit borders (32-bit boundary), returning address (return address) and also need be limited in block boundary (wordboundary) or 32 bit borders (32-bit boundary) for the instruction of branch-link (branch-and-link) and jump-link (jump-and-link), this kind restriction can increase the inconvenience on using, therefore, the design of known multimode instruction processing unit still has many disappearances and gives improved necessity.
Summary of the invention
The object of the present invention is to provide a kind of with automatic command mode switch the align processor and the method for word group, to avoid known technology the jump address to be limited in block boundary or 32 caused challenges of non-boundary because of need, simultaneously, improve the execution speed of processor.
According to a characteristic of the present invention, propose a kind of with the align processor of word group of automatic command mode switch, its performed instruction is from the instruction boundaries of L bit length, can hold a M bit instruction or the instruction of a plurality of N bit in this L bit instruction boundaries, wherein L, M, N are positive integer, L 〉=M＞N, at least one N bit instruction is to there being M bit instruction, and this processor comprises:
One instruction inputting device, it comprises a width is the L bit word group of the storage area of L bit for a plurality of representatives instructions of storage;
One instruction capture device is in order to capture a L bit word group of this order code input media; And
One instruction mode conversion equipment, the L bit word group that is captured when this instruction capture device is that M bit instruction and last L bit word group are when only being N bit instruction, if this N bit instruction has corresponding M bit instruction, it then is corresponding M bit instruction with this N bit instruction transformation, if this N bit instruction does not have corresponding M bit instruction, the NOP that then inserts at least one N bit instructs after this N bit instruction.
Described processor wherein also comprises:
One instruction decoding device is decoded in order to the instruction that this instruction mode conversion equipment is exported; And
One instruction executing device instructs after carrying out the decoding that this instruction decoding device exports.
Described processor, wherein, L is 32, and M is 32, and N is 16.
According to another characteristic of the present invention, propose a kind of with the align method of word group of automatic command mode switch, the performed instruction of this processor is from the instruction boundaries with L bit length, can hold a M bit instruction or the instruction of a plurality of N bit in this L bit instruction boundaries, wherein L, M, N are positive integer, L 〉=M＞N, at least one N bit instruction is to there being M bit instruction, and the method comprising the steps of:
(A) the L bit word group that provides a plurality of representatives to instruct;
(B) acquisition one L bit word group, wherein, when the L bit word group that is captured is that M bit instruction and last L bit word group are when only being N bit instruction, if this N bit instruction has corresponding M bit instruction, it then is corresponding M bit instruction with this N bit instruction transformation, if this N bit instruction does not have corresponding M bit instruction, the NOP that then inserts at least one N bit instructs after this N bit instruction;
(C) the L bit word group that is captured is decoded; And
(D) carry out this decoded N bit instruction or instruction of M bit.
Described method is characterized in that, wherein, L is 32, and M is 32, and N is 16.
Converse routine of the present invention instructs the method for word group of aliging, the instruction of this program has the instruction boundaries of L bit length, can hold a M bit instruction or the instruction of a plurality of N bit in this L bit instruction boundaries, L wherein, M, N is a positive integer, L 〉=M＞N, at least one N bit instruction is to there being M bit instruction, this method is acquisition one a L bit word group, wherein, when the L bit word group that is captured is M bit instruction, and when last L bit word group only is N bit instruction, if this N bit instruction has corresponding M bit instruction, it then is corresponding M bit instruction with this N bit instruction transformation, if this N bit instruction does not have corresponding M bit instruction, the NOP that then inserts at least one N bit instructs after this N bit instruction.
Description of drawings
Fig. 1: be the synoptic diagram of known instruction mode switching.
Fig. 2: be the order structure synoptic diagram of another known instruction mode switching.
Fig. 3: for of the present invention with the align Organization Chart of processor of word group of automatic command mode switch.
Fig. 4: for of the present invention with the align process flow diagram of method of word group of automatic command mode switch.
Fig. 5: for foundation the present invention with an align example of word group of automatic command mode switch.
Fig. 6: be a foundation exemplary applications of the present invention.
Embodiment
For further understanding structure of the present invention, feature and purpose thereof, also elaborate in conjunction with the accompanying drawings with preferred embodiment.
Relevant of the present invention in multimode instruction with automatic command mode switch the align processor and the method for word group, please be earlier with reference to processor architecture figure shown in Figure 3, it includes an instruction inputting device 310, an instruction capture device 320, an instruction mode conversion equipment 330, an instruction decoding device 340 and an instruction executing device 350.Aforementioned multimode instruction processing unit has M bit instruction set and N bit instruction set (M, N is a positive integer, M＞N), wherein, in N bit instruction set, have at least N bit instruction in M bit instruction set, to have a corresponding M bit instruction, have the storage area of the instruction boundaries of L bit length (L is a positive integer and aforementioned instruction inputting device 310 provides one, L 〉=M), for storing the instruction that to carry out, word group (Word) in this L bit instruction boundaries can be a M bit instruction or the instruction of a plurality of N bit, and in present embodiment, the L value is 32, the M value is 32, and the N value is 16.
Aforementioned instruction capture device 320 is in order to capture a L bit word group of this instruction inputting device, this instruction mode conversion equipment 330 is in order to the content of the L bit word group that captured according to this instruction capture device, judges whether that the pattern of the instruction that will be comprised is changed.This instruction decoding device 340 is decoded in order to the instruction that this instruction mode conversion equipment 330 is exported, and this instruction executing device 350 instructs after in order to the decoding of carrying out this instruction decoding device 340 and being exported.
Fig. 4 further shows of the present invention with the align control flow of processor of word group of automatic command mode switch, at first, these instruction inputting device 310 inputs have the L bit word group (step S401) of a plurality of representative instructions, this instruction capture device 320 acquisitions one L bit word group (step S402), in step S403, this instruction mode conversion equipment 330 judges whether that the L bit word group (being assumed to be n L bit word group) that is captured is M bit instruction, and L bit word group (n-1 L bit word group) only is N bit instruction on it, as denying, need not carry out instruction transformation, in this way, represent that then this n-1 L bit word group may cause word group alignment problem, and must be changed, therefore, step S404 judges further whether the N bit instruction of this n-1 L bit word group has corresponding M bit instruction in M bit instruction set, if have, it then is corresponding M bit instruction (step S405) with the N bit instruction transformation in this L bit word group, so can avoid the problem of word group alignment, continue acquisition instruction (step S402) again.
In M bit instruction set, there is not corresponding M bit instruction if in step S404, judge the N bit instruction of this n-1 L bit word group, then in the NOP instruction (step S405) of at least one N bit of back insertion of this N bit instruction, to mend the instruction boundaries of full L bit, to exempt the problem of word group alignment, in this embodiment, therefore L=M=32 and N=16, only need to insert the NOP instruction of a N bit.
Fig. 5 shows of the present invention with automatic command mode switch the align processor of word group and the example of method, as shown in the figure, in pending instruction, instruction (7) is that one 16 bits instruct (8) be that one 32 bits instruct, this will cause word group alignment problem, therefore, if the instruction (7) of this 16 bit has the instruction (7 ') of corresponding 32 bits, then the present invention is converted to the instruction (7) of this 16 bit the instruction (7 ') of its corresponding 32 bits.Instruction (17) is that one 16 bits instruct (18) be that one 32 bits instruct, if the instruction (17) of this 16 bit does not have the instruction (17) of corresponding 32 bits, then the present invention in the instruction (17) of this 16 bit afterwards, instruction (18) inserts the NOP instruction of one 16 bits before, and solves word group alignment problem.
From the above, in the present invention, because the instruction (7) of 16 bits has been converted to the instruction (7 ') of its corresponding 32 bits, so this processor executes can execute instruction immediately after the instruction (7 ') of this 32 bit (8), and need not after carrying out 16 a bit NOP instruction that does not act on, could execute instruction (8), this can increase this processor execution speed, can overcome the instruction of known technology 32 bits instructions and 16 bits and can't be mingled with the problem that leaves same block in.
Fig. 6 shows an exemplary applications of the technology of the present invention, a program 610 with a plurality of 32 bit word groups wherein, and it can comprise a plurality of 16 bits and the instruction of 32 bits.This program 610 can be earlier via instruction mode conversion equipment 330 of the present invention or technology, be about to have in this program 610 instruction (7) that can cause word group alignment problem as shown in Figure 5 earlier and instruction (8) is changed and be program 620, this program 620 is stored in the reservoir 630 again.This kind transfer process also can be used a software to carry out off-line (off-line) and handle.
And general processor 640 is when this program 620 of execution, it will be by taking off program fetch 620 in this reservoir 630, because this program 620 has not had word group alignment problem, this processor 640 can avoid carrying out the hardware circuit that carries out related words group alignment problem, this not only can lower the complexity of processor 640 designs, simultaneously, also can quicken its execution speed.
It should be noted that above-mentioned many embodiment only give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (5)
1, a kind of with the align processor of word group of automatic command mode switch, its performed instruction is from the instruction boundaries of L bit length, can hold a M bit instruction or the instruction of a plurality of N bit in this L bit instruction boundaries, wherein L, M, N are positive integer, L 〉=M＞N, at least one N bit instruction is to there being M bit instruction, and this processor comprises:
One instruction inputting device, it comprises a width is the L bit word group of the storage area of L bit for a plurality of representatives instructions of storage;
One instruction capture device is in order to capture a L bit word group of this instruction inputting device; And
One instruction mode conversion equipment, the L bit word group that is captured when this instruction capture device is that M bit instruction and last L bit word group are when only being N bit instruction, if this N bit instruction has corresponding M bit instruction, it then is corresponding M bit instruction with this N bit instruction transformation, if this N bit instruction does not have corresponding M bit instruction, the NOP that then inserts at least one N bit instructs after this N bit instruction.
2, processor as claimed in claim 1 is characterized in that, wherein also comprises:
One instruction decoding device is decoded in order to the instruction that this instruction mode conversion equipment is exported; And
One instruction executing device instructs after carrying out the decoding that this instruction decoding device exports.
3, processor as claimed in claim 1 is characterized in that, wherein, L is 32, and M is 32, and N is 16.
4, a kind of with the align method of word group of automatic command mode switch, the performed instruction of this processor is from the instruction boundaries with L bit length, can hold a M bit instruction or the instruction of a plurality of N bit in this L bit instruction boundaries, wherein L, M, N are positive integer, L 〉=M＞N, at least one N bit instruction is to there being M bit instruction, and the method comprising the steps of:
(A) the L bit word group that provides a plurality of representatives to instruct;
(B) acquisition one L bit word group, wherein, when the L bit word group that is captured is that M bit instruction and last L bit word group are when only being N bit instruction, if this N bit instruction has corresponding M bit instruction, it then is corresponding M bit instruction with this N bit instruction transformation, if this N bit instruction does not have corresponding M bit instruction, the NOP that then inserts at least one N bit instructs after this N bit instruction;
(C) the L bit word group that is captured is decoded; And
(D) carry out this decoded N bit instruction or instruction of M bit.
5, method as claimed in claim 4 is characterized in that, wherein, L is 32, and M is 32, and N is 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03133082 CN1272703C (en) | 2003-07-23 | 2003-07-23 | Processor and method for aligning block by automatic command pattern conversion |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03133082 CN1272703C (en) | 2003-07-23 | 2003-07-23 | Processor and method for aligning block by automatic command pattern conversion |
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| Publication Number | Publication Date |
|---|---|
| CN1570852A CN1570852A (en) | 2005-01-26 |
| CN1272703C true CN1272703C (en) | 2006-08-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 03133082 Expired - Fee Related CN1272703C (en) | 2003-07-23 | 2003-07-23 | Processor and method for aligning block by automatic command pattern conversion |
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| CN (1) | CN1272703C (en) |
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