CN1270713A

CN1270713A - Master-salve delay locked loop for accurate delay of non-periodic signals

Info

Publication number: CN1270713A
Application number: CN98809096A
Authority: CN
Inventors: S·R·莫尼
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1997-07-14
Filing date: 1998-07-07
Publication date: 2000-10-18
Anticipated expiration: 2018-07-07
Also published as: AU8382798A; CN1169294C; EP1025644A1; WO1999004494A1; EP1025644A4; KR20010021784A; KR100347445B1; US5905391A; TW408550B

Abstract

The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal and a data signal responsive to the clocking signal. A receiving component receives the strobe signal and data signal. The receiving component includes delay circuitry to delay the strobe signal so as to position edges of the strobe signal with respect to data cells of the data signal. The delay circuitry includes a loaded delay elements and DC level restoration circuitry to control the load of the loaded delay element. The delay elements may be a series of inverters loaded with RC loads. The DC level restoration circuitry may be pulse generation circuitry.

Description

The principal and subordinate's delay lock loop that accurately postpones nonperiodic signal

The background of invention

TECHNICAL FIELD OF THE INVENTION:

The present invention relates to comprise delay circuit with between the deferred telegram parts aperiodic gating signal interface system, particularly such interface system, in this system, delay circuit comprises that DC level recovers, to prevent and to shake relevant figure.

Background technology:

Data are everlasting and are transmitted between two electric parts.For example, data transmit between microprocessor and memory.Under the situation that is called public clock example, the signal that comes self-clock is offered transmission and receiving-member.In a clock cycle, transmit data and locking data receiving-member from transmit block.Therefore, limit the speed that data transmit by the journey time of data by conductor between parts.In certain of clock frequency more than the grade, because the electrical length of interconnection becomes greater than the clock cycle, so can not adopt public clock method again.

In order to overcome this problem, developed such technology, wherein,, timing information is sent with data for locking data on the link receiver side.This is called source synchronizing signal.According to a kind of technology, timing information sends on same conductor as data.According to second kind of technology, on the conductor that separates, send timing information.

According to a method of second kind of technology, only when sending on the link of data between parts, just trigger different timing signals or gating signal.Data are locked in the receiver side of link.Circuit becomes the data transaction of locking the clock zone of receiving-member.Gating signal and data depart from, with respect to data cell centering (center) gating signal.The a series of resistor-capacitors that have not gate in delay circuit, have been used.If finish accurate delay by aperiodic gating signal.Utilize aperiodic, only mean that gating signal just triggers (still, gating signal is periodic) in of short duration scope when being connected with data converter.Therefore, timing information only can obtain off and on.Have, the node of delay circuit has the bandwidth greater than the input data frequency again.If this condition is not satisfied, the node voltage in the delay circuit may become relevant datagraphic so.For the clock figure, the voltage of node does not reach rail voltage, and for one and zero of long string, this voltage produces and the relevant figure of timing signal shake.

Therefore, for interface system, need avoid figure relevant with shake in postponing timing signal aperiodic.

Disclosure of an invention

The present invention includes electric unit interface system.This system comprises the clock circuit that clock signal is provided.Transmit block provides gating signal and the data-signal corresponding with clock signal.Receiving-member receives gating signal and data-signal.Receiving-member comprises delay circuit, and this circuit delay gating signal is so that determine the position at gating signal edge with respect to the data cell of data-signal.Delay circuit comprises the DC level restoration of the delay element load of loaded delay elements and control loaded.In some embodiments of the invention, gating signal is the signal of aperiodic.

Brief description of drawings

Below, will more completely understand the present invention according to the following description of reference embodiment of the invention accompanying drawing, still, the invention is not restricted to described specific embodiment, specific embodiment only is used for explaining and understanding.

Fig. 1 is the schematic block diagram of the electric unit interface system of one embodiment of the invention.

Fig. 2 is the schematic block diagram of the delay circuit that adopts in system shown in Figure 1.

Fig. 3 is the curve chart of the gating signal of the data-signal, gating signal and the delay that produce in system shown in Figure 1.

Fig. 4 is the schematic block diagram of the delay circuit that adopts in delay circuit shown in Figure 2.

Fig. 5 is voltage signal in delay circuit shown in Figure 4 and the curve chart that does not have the voltage signal under the DC level recovery situation.

Fig. 6 is the pulse generator that adopts in delay circuit shown in Figure 6.

DETAILED DESCRIPTION OF THE PREFERRED

With reference to Fig. 1, electric unit interface system 10 comprises two electric parts 14 and 16.Interface system 10 is specially adapted to from parts 14 to parts 16 data high-speed and transmits.Parts 14 and parts 16 can be one of various parts that comprise by microprocessor, memory, logical circuit and controller, but are not limited to these parts.Parts 14 can be microprocessor, and parts 16 can be the memory (for example, L2 cache) that is separated by high-speed bus (for example, back side bus like the relevant back side bus type of the Pentium  Pro processor that makes with Intel Corp.).

Parts

14 and 16 can be parts that comprises the personal computer of desktop computer, server or portable computer.Only show the part-structure of

parts

14 and 16.

In parts 14, according to the clock signal on the conductor 28 50, data-signal 18 offers conductor 26 from conductor 20 through latch 22.Latch 22 can comprise d type flip flop.Clock signal 50 also offers an input of AND door 30.Another input of AND door 30 is connected with conductor 34, applies gating signal on this conductor selectively.The output of AND door 30 is offered the clock input of latch 38.When the gating initiating signal was identified, latch 38 offered conductor 40 to gating signal 54 according to clock signal 50.Latch 38 can comprise bistable trigger.According to another embodiment, the D input of control trigger.

Transmit the gating initiating signal of confirming relatively on the conductor 34 with data, otherwise be not identified from electric parts 14 to electric parts 16.For example, the transmission of four of data-signal 18 parts can be finished in four clock cycle of clock signal 50.Because of the transmission of final data part, the gating initiating signal is not assert that gating signal 54 is no longer valid.After this, gating signal 54 is acyclic (although it is periodic with respect to finite time).

Clock signal 50 is come self-clock source 44.The clock signal 50 ' of coming self-clock source 44 is offered conductor 60.On the conductor 28 and 60 of delay clock signals 50 and 50 ', can there be stray delay (being expressed as stray delay 64 and 66).Clock signal 50 and 50 ' distributes by nonideal mode, so that does not have accurately duplicating of original clock.In theory, clock signal 50 and 50 ' equates.Can regard clock signal 50 and 50 ' as single clock signal.

The data-signal 18 that latch 82 receives from conductor 26.If there is not delay circuit 76,, do not have the settling time of data bit in the latch 82 so if gating signal 54 and data-signal 18 arrive simultaneously.See figures.1.and.2, in order to address this problem, gating signal 54 is postponed by the delay circuit in the receiving-member 16 76, so that the triggering edge of gating signal 54 places the beginning of data cell and the center between the end ideally.Thus, the settling time and retention time or the nargin that have equivalent.On the other hand, gating signal 54 can postpone by the difference amount, and is different with generation on the retention time in foundation.Trigger the edge and can only be the rising edge, only be drop edge or rising edge and drop edge.

With reference to Fig. 1, transducer 86 is the clock zone that converts receiving-member 16 from the data-signal 18 of latch 82 to.Two clocks or domain are arranged in interface system 10.First domain is the territory of clock 44.The second clock territory is the territory of gating signal 54.Because various delays comprise the delay of the journey time of gating signal 54 on the conductor 40, so the domain of gating signal 54 is different with the territory of clock signal 50 '.Therefore, the phase-independent of the phase place of gating signal 54 and clock signal 50 and 50 '.Clock signal 50 and 50 ' is very approaching, is enough to they are handled as a clock zone.Transducer 86 makes data-signal 18 and clock signal 50 ' synchronously.Transducer 86 provides enough stand-by period, with any phase deviation between control gating signal 54 and the clock signal 50 '.

The delay that is produced by delay circuit 76 preferably reaches two criterions.The first, delay should be accurate, so that the triggering edge of the gating signal 54 that postpones is in the center of data cell.The second, postponing should be inresponsive to the variation of supply voltage.In addition, even gating signal 54 all triggers if having time in institute, delay circuit 76 preferably also produces the delay of expectation, rather than only produces delay when data transmit.

Obviously,

parts

14 and 16 receive the clock signal 50 and 50 ' in self-clock source 44.Therefore, gating signal 54 only has the frequency identical or relevant with clock signal 50 ' under the situation of phase deviation.Delay circuit 76 uses the frequency information from clock signal 50 ' to produce delay.

The frequency of clock signal 50 ' by 1: 2 frequency dividing circuit 72 divided by 2 so that on the conductor 74 cycle of clock signal be the clock signal twice in 50 ' cycle.The long cycle makes delay circuit 76 more be easy to generate suitable delay.The clock signal that produces offers delay circuit 76 by conductor 74.

With reference to Fig. 2, principal and subordinate's delay circuit 76 receive on the conductors 40 gating signal 54 and from the clock signal of conductor 74.Delay circuit 76 comprises the delay lock loop of being furnished with voltage-controlled delay circuit 108 and delay circuit 112 and the phase detectors 104 that the feedback signal that postpones on the phase place of the clock signal on the conductor 74 and the conductor 106 is compared.The output of phase detectors 104 is offered p NMOS N-channel MOS N (pMOS) transistor 120 that comprises resistance 122 and play the capacitor effect.In order to make delay circuit 76 simple, filter 118 is simple first order pole RC circuit, plays low pass filter, with filtering noise.Because delay circuit 108,112 and 114 is the delay circuits in the delay circuit, so can call sub-delay circuit to delay circuit 108,112 and 114.

Voltage control on the conductor 136 (V-control) signal offers delay circuit 108 and 112 by conductor 142, and offers voltage-controlled delay circuit 144 by conductor 132.Delay circuit 108,112 and 144 is mutually the same.V-control signal adjustment delay circuit 108 and 112 delays until delay circuit 108 and 112 equal the phase place of a clock signal on the conductor 74.When the delay by delay circuit 108 and 112 equals phase place of clock signal, so loop locked and will keep the locking.Delay in the loop that comprises delay circuit 108 and 112 all produces delay from beginning to the end of data cell.The delay of delay circuit 144 produces half delay, this postpone the beginning of data cell and between finishing midway delay gating signal 54 effectively or trigger edge (rise or descend) centering.

Fig. 3 provides a sequential chart, the universal relation between the gating signal 54 on expression data-signal 18, the conductor 40 and the gating signal 54 of the delay on the conductor 78.Data-signal 18 comprises various data cells, wherein special recognition data unit A, B, C and D.Data cell has beginning edge (B) and end edge (E) (certainly, actual signal does not have this sharp-pointed edge).Data or bit period (being also referred to as cell width) are between two neighboring edges (for example, from time t0 to time t2).Data cell A is a logical value 1, and data cell B is a logical value 0.Two data unit C and D are logical value 1.Data-signal 18 adopts non-return-to-zero (NRZ) scheme.Therefore, not conversion between data cell C and data cell D.On the meaning not according to any particular order, data-signal 18 is not periodic at logical zero and logical one.But continuous data cell generally has identical data width.Therefore, data cell has been considered to the cycle.

Gating signal 54 is postponed like this, so that during the gating signal 54 that postpones gets between the beginning of data cell and end edge.For example, data cell A begins when time t0 and finishes when time t2.The centre of time t1 between time t0 and time t2.The rising edge of the gating signal 54 that postpones occurs when time t1.This makes the foundation (S) of the data in latch 82 or the parts 16 and keeps (H) that the equal time is arranged.The drop edge of the gating signal 54 that postpones occurs when time t3, and this time is in the beginning of data cell B with the centre between finishing, and therefore foundation and the maintenance to the data in latch 82 or other places provides the equal time.When time t4 and t6, carry out beginning and the end of data cell C.When time t6 and t8, carry out beginning and the end of data cell D.The rising edge of the gating signal 54 that postpones when time t5 is centered in the center of data cell C, and the drop edge of the gating signal 54 that postpones when time t7 is centered in the center of data cell D.Therefore, for data cell C and D, equal foundation and retention time are arranged.

In Fig. 3, the cycle of gating signal 54 is twices (cycle of gating signal 54 is to time t8 from time t4) of the cell width (or cycle) of the data cell of data-signal 18.As mentioned above, when transmitting data rather than other situation, gating signal 54 is to have periodically in the of short duration time limit.In another embodiment of the present invention, bit width can be identical with the cycle of gating signal 54.In this case, have only one to trigger the edge, for example the rising edge of gating signal or forward position are by centering.Situation shown in Figure 3 is specially adapted to the server of fair speed, and the cell width situation identical with the gating signal cycle is specially adapted to slower, not expensive desktop computer.Postpone in the loop minute multiplexer to be can be used for having two data-signal frequency capability in single assembly.But the delay of multiplexer is often uncontrolled, and the susceptibility of Vcc is increased.

With reference to Fig. 4, the gating signal 54 on the conductor 40 by the not gate in the delay circuit 144 150 oppositely.Not gate 152A (this not gate is the example of delay element) receives and is reverse from the reverse signal on the conductor 154A of not gate 150.In check resistance-capacitance (RC) circuit 166A offers not

gate

150 and 152A to the RC load by conductor 162A.The speed of not

gate

150 and 152A switch is relevant with the RC load capacity.In check RC circuit 166A comprises the pMOS transistor 178A that produces electric capacity, and n NMOS N-channel MOS N (nMOS) the transistor 170A that has a resistance.By the V-control signal controlling resistance amount on the conductor 132.As described in more detail below, pulse generator 172A carries out the DC level recovery to the voltage VRC (A) on the conductor 176A.

Not gate 152B receives and is reverse from the signal on the conductor 154B of not gate 152A.Not gate 152C receives and is reverse from the signal on the conductor 154C of not gate 152B.Not gate 152D receives from the signal on the conductor 154D of not gate 152C.Not gate 190 is oppositely from the signal on the conductor 194 of not gate 152D.In check RC circuit 166B provides RC load by conductor 162B to not gate 150A and 152B.In check RC circuit 166C provides RC load by conductor 162C to not gate 152B and 152C.In check RC circuit 166D provides RC load by conductor 162D to not gate 152C and 152D.In

check RC circuit

166B, 166C and 166D and circuit 166A are basic identical.

For the gating signal 54 by delay circuit 144, the quantity of not gate is determined ductile scope (being upper and lower bound).Certainly, the quantity of not gate can be greater or less than quantity shown in Figure 4.V-control signal on the conductor 132 is set special actual delay in this scope.

In Fig. 4, voltage VRC (A) is the voltage on the node of conductor 174A and 176A.Pulse generator 172A in check RC circuit 166A is the DC level restoration that the node of

conductor

174A and 176A is provided the DC level restoring signal.The DC level restoring signal can influence voltage VRC (A), and therefore influences the speed of not gate 152A switch.On the conductor 176B (not shown) in check RC circuit 166B voltage VRC (B) is arranged, this voltage is corresponding to the voltage on the conductor 176A among the in check RC circuit 166A.Equally, the pulse generator 172B (not shown) in check RC circuit 166B is the DC level restoration that the node of conductor 174B and 176B (not shown) is provided the DC level restoring signal.The DC level restoring signal can influence voltage VRC (B), and therefore influences the speed of not gate 152B switch.Because the change on the not gate is followed in the variation in the load, so, make circuit very insensitive to the variation among the Vcc according to not gate specified loads correctly.Adopt the problem of delay circuit 76 to be in high-speed applications (for example, back side bus is used), under low control voltage, the node of

conductor

174A and 176A has very little bandwidth especially.As mentioned above, when capacitance voltage was relevant with figure, this can be attached to the figure relevant with shake on the input stage.DC level recovers to have solved this problem.

The purpose of pulse generator 172A, 172B etc. is to avoid and shakes relevant figure.The figure relevant with shake shows this state, and in this state, the period voltage level of signal depends on the initial state of signal and/or the length of signal.Under the situation that does not have pulse generator 172A, 172B etc., the value of VRC (A), VRC (B) etc. can depend on that the length in 54 triggered times of gating signal and/or gating signal 54 are high transition or low transition when handling beginning.With reference to Fig. 5, represent by signal 180,182,184 and 186 in the effect of the last pulse generator 172A of VRC (A) with in the effect of the last pulse generator 172B (not shown) of VRC (B).Signal 180 is illustrated in the voltage VRC (A) that can occur under the situation that does not have pulse generator 172A.Label 192 (dotting) expression rail voltage.Signal 182 is illustrated in the voltage VRC (A) under the pulse generator 172A working condition.Signal 184 is illustrated in the voltage VRC (B) that can occur under the situation that does not have pulse generator 172B (not shown).Signal 186 is illustrated in the voltage VRC (B) under the pulse generator 172B working condition.In Fig. 5, suppose the rising edge of signal corresponding to gating signal 54 on the conductor 40.

For example, for the top edge of the gating signal 54 of following next bit cell lower limb, the ceiling voltage of signal 180 can be V1.On the contrary, if gating signal 54 keeps high level for a long time, the ceiling voltage of signal 180 will be near rail voltage VR so.Therefore, the delay meeting basis signal that the rise time of not gate reaches by delay circuit 144 keeps the time span of high level different, but does not expect to occur this phenomenon.But, utilizing the work of pulse generator 172A, the ceiling voltage of signal 182 is approximately VR, keeps the time span of high level irrelevant with gating signal 54.Signal 182 has and irrelevant rising and fall time of the duration of gating signal 54.Utilize DC level to recover, when each end cycle, voltage VRC (A), VRC (B) etc. is resumed to the quiescent value identical with respect to each cycle by delay circuit.

Under the situation of signal 184, when handling beginning, the gating signal on the conductor 154A is approximately rail voltage.But after this, ceiling voltage is smaller than rail voltage.As an example, the triple point of not gate 152B is at the Vcc place.Drop edge during time t1 is from dead level, and the drop edge during time t2 is from low voltage level.Not gate 152B in the drop edge of time t2 than connecting quickly in the drop edge of time t1.This is and the example of shaking relevant figure.In signal 186, DC level appeared in each cycle, so that had and the irrelevant same delay of signal graph.

The details of the embodiment of Fig. 6 indicating impulse generator 172A.In general, the lower limb of VCR (A) is no problem.Problem is edge on top often.Voltage signal on the conductor 160A offers the drain electrode of not gate 204A and nMOS transistor 224A.The reverse signal of not gate 204A output is offered the input of not gate 206A and the input of NOR door 210A.The output of not gate 206A is also offered the input of NOR door 210A.Owing to postpone by not gate 206A,, this pulse offered the grid of nMOS transistor 220A so NOR door 210A produces of short duration pulse at its output.Reference voltage 222A is offered the grid of transistor 224A, so that this transistor ON always.The grid of nMOS transistor 230A connects its drain electrode on the node of conductor 174A.At work, it is high level that pulse generator 172A generation pulse makes transistor 220A, in case the input of not gate 204A is surpassed Vcc, just recovers the voltage level (threshold voltage) of Vcc-Vt.Transistor 224A keeps this voltage as little retainer circuit by this level.Transistor 230A provides little bias current to transistor 224A () long channel device for example,＜1 microampere (μ A) is recovering not extract VRC (A) on the level so that sub-threshold value is revealed (subthresholdleakage).This produce to Vcc level relative insensitivity with postpone irrelevant figure.Be noted that loop filter and Vcc rather than be coupled with Vss.Therefore, the variation on the Vcc can appear on the not gate 150A, also appears on the transistor 170A, strengthens the Vcc noise suppressed of delay circuit 144.The regulation transistor specifications is so that make the sensitiveness minimum of Vcc.

Additional information and embodiment

For the those skilled in the art that obtain the open interests of the present invention, the many variations on the various circuit are tangible.For example, illustrated here various logic circuitry can replace with other logical circuit with identical function.General utility functions of the present invention can be finished by diverse circuit.For example, do not need principal and subordinate's delay lock loop.

Place illustrating or illustrate single conductor can replace with the conductor of parallel connection.Place at diagram or explanation parallel conductor can replace with single conductor.

Do not require mutually the same delay circuit 108,112 and 144.In addition, do not require mutually the same in

check RC circuit

166A, 166B, 166C and 166D.

Although delay circuit shown in Figure 4 144 comprises six not gates, can use the not gate of more or less quantity.In addition, can use even number or odd number not gate.Not gate 190 can be used for two purposes.At first, the edge of not gate 190 arrangement gating signals 54.The second, provide the even number not gate, so that suitably adjust the phase place of the rising edge of the gating signal 54 that postpones.But also may not request this two effects.At first, the edge of gating signal 54 is just enough under the situation that does not have not gate 190.The second, the not gate quantity according in the delay circuit 144 can have the even number not gate under the situation that does not have not gate 190.Have, circuit and timing can be such as the even number not gate that expected result is provided again.

Do not need 1: 2 frequency dividing circuit 72, but this circuit can be set, so that provide the bigger clock cycle delay circuit 76.

Phase detectors 104 can be provided with the relay system phase detection, utilize this system, no matter how far clock signal on the conductor 74 and the feedback signal on the conductor 106 depart from, all supply with the plus or minus phasing of control line 136 same amounts.Phase detectors 104 can be realized by simple latch.Phase detectors 104 can be the duplicate of latch 82.Utilize the duplicate of latch 82, phase detectors 104 have identical foundation and retention performance on latch 82, to make settling time of reason latch 82 the gating signal displacement on the conductor 78.If arranged the settling time of non-zero on latch 82, so preferably utilize to make this settling time regularly from the data cell off-centring.Filter 118 is used to reduce the variation of controlling voltage when loop is in locking.Theoretically, filter poles preferably is in alap frequency for loop.Generally should limit the effective coverage.Generally also should limit requirement locking time.In certain embodiments, the fluctuation that allows is set at＜30mv, and therefore sets senior filter.The second, lock quickly in order to make loop, behind the anti-form (deassertion) that resets, can use high frequency filter.Set the limit of this filter, make minimum locking time of loop.Because fluctuation increases with filter poles, so should consider the limit of two filters, promptly because first limit shifts to an earlier date, and descend to the locking time of first filter, and increase the locking time of second loop, calculates minimum locking time.

As shown in Figure 1, parts 14 are sent to parts 16 to data.Certainly, parts 16 also can be sent to parts 14 to data.The delay circuit identical with delay circuit in the parts 16 can be included in the parts 14.

The above preferred embodiment that has been combined on the different conductors system specialization that transmits timing information and data.But the present invention also can be used for interface system, in this interface system, transmits the timing information as data on identical conductor.

Utilization well known to a person skilled in the art various materials and method, can realize various structure of the present invention.Intermediate structure (for example, buffer) or signal between two structures of being showed can be arranged.Some conductor do not resemble showed be continuous, but separated by intermediate structure.The border of square frame is used for illustrative purposes among the figure.Actual device can not comprise the border of such qualification.The relative size of institute's display member is not represented actual relative size.

On the meaning of work, use term " connection " and relational language, might not be limited to direct connection.For example, delay circuit 144 is connected (although connecting indirectly) by RC circuit 118 with phase detectors 104 with conductor 132.Term " response " and relational language refer to that a signal or incident are subjected to the influence of another signal or incident to a certain extent, but not necessarily fully or directly influence.

If specification illustrates parts with " can ", " should " or " best ", refer to not require certain components so.

Obtain one skilled in the art will recognize that of disclosure interests, without departing from the present invention, can carry out many changes with accompanying drawing according to the above description.Therefore, appended claims comprises any amendment that limits the scope of the invention.

Claims

1. electric unit interface system comprises:

Clock circuit provides clock signal;

Transmit block provides gating signal and data-signal in response to clock signal; With

Receiving-member, receive gating signal and data-signal, this receiving-member comprises delaying strobe signal so that place the delay circuit at the edge of gating signal with respect to the data cell of data-signal, this delay circuit has loaded delay elements and DC level restoration, with the load of the delay element of control loaded.

2. system as claimed in claim 1 wherein is placed on the edge of gating signal the center of data cell, so that provide identical foundation and the retention time to the data unit.

3. system as claimed in claim 1, wherein delay circuit comprises principal and subordinate's delay lock loop, this principal and subordinate's delay lock loop comprises that two boss's delay circuits introducing same delay respectively and one are from sub-delay circuit.

4. system as claimed in claim 1, wherein delay circuit receive clock signal, and delay circuit comprises delay lock loop, this delay lock loop comprises that the sub-delay circuit of modulation equals the voltage signal of a phase place of clock signal until the delay of sub-delay circuit.

5. system as claimed in claim 1, the derivative of delay circuit receive clock signal wherein, and this delay circuit comprises delay lock loop, and this locking ring comprises that the sub-delay circuit of modulation equals the voltage control signal of a phase place of clock signal derivative until the delay of sub-delay circuit.

6. system as claimed in claim 1, wherein the frequency of clock signal is by divided by 2, and is delayed circuit and receives.

7. system as claimed in claim 1, wherein DC level restoration comprises pulse generator.

8. system as claimed in claim 1, wherein DC level restoration comprises pulse generator, this pulse generator provides the DC level restoring signal in response to the supply voltage of system.

9. system as claimed in claim 1, wherein delay circuit comprises phase detectors and simple R C low pass filter, this RC low pass filter carries out filtering to the output of phase detectors, produces the voltage control signal of the sub-delay circuit of control.

10. system as claimed in claim 1, wherein the position at the Continuity signal edge at data cell center is insensitive to power source change.

11. system as claimed in claim 1 wherein also comprises the circuit of control data cell width.

12. system as claimed in claim 1 comprises that also being in server mode according to system still is in the circuit that desk-top pattern is come the control data cell width.

13. system as claimed in claim 1, wherein gating signal is gating signal aperiodic, and this signal only is triggered in response to the transmission of data-signal.

14. system as claimed in claim 1, wherein delay element is a not gate.

15. system as claimed in claim 1, wherein delay element is contained on the RC circuit.

16. system as claimed in claim 1, wherein the edge only comprises the rising edge.

17. the interface system of electric parts comprises:

Clock circuit provides clock signal;

Transmit block, provide corresponding with clock signal aperiodic gating signal and data-signal; With

Receiving-member, receive gating signal and data-signal, this receiving-member comprises delay circuit, this delay circuit delays gating signal is so that place the edge of gating signal with respect to the data cell of data-signal, this delay circuit has loaded delay elements and DC level restoration, with the load of the delay element of control loaded.

18. as the system of claim 17, wherein the edge of gating signal places the center of data cell, so that provide equal foundation and the retention time to the data unit.

19. as the system of claim 17, wherein delay circuit is in response to clock signal.

20. as the system of claim 17, wherein DC level restoration comprises pulse generator.

21. as the system of claim 17, wherein DC level restoration comprises pulse generator, this pulse generator provides the DC level restoring signal in response to the supply voltage of system.

22. an electric unit interface system comprises:

Clock circuit provides clock signal;

Receiving-member, receive gating signal and data-signal, this receiving-member comprises delay circuit, this delay circuit delays gating signal is so that place the edge of gating signal with respect to the data cell of data-signal, the useful controlled RC circuit loaded delay elements of this delay circuit, controlled RC circuit comprises DC level restoration, with the load of the delay element of control loaded.

23. as the system of claim 22, wherein the edge of gating signal places the center of data cell, so that provide equal foundation and the retention time to the data unit.

24. as the system of claim 22, wherein delay circuit is in response to clock signal.

25. as the system of claim 22, wherein DC level restoration comprises pulse generator.

26. as the system of claim 22, wherein DC level restoration comprises pulse generator, this pulse generator provides the DC level restoring signal in response to the supply voltage of system.