CN1265431C - Relaxed, low-defect SGOI for strained Si CMOS applications - Google Patents

Relaxed, low-defect SGOI for strained Si CMOS applications Download PDF

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CN1265431C
CN1265431C CNB2003101163084A CN200310116308A CN1265431C CN 1265431 C CN1265431 C CN 1265431C CN B2003101163084 A CNB2003101163084 A CN B2003101163084A CN 200310116308 A CN200310116308 A CN 200310116308A CN 1265431 C CN1265431 C CN 1265431C
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layer
relaxation
sige
basically
pattern
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CN1503327A (en
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保罗·D.·阿格尼罗
斯蒂芬·W.·比代尔
罗伯特·H.·丹纳德
安佐尼·G.·多迈尼古奇
凯思·E.·弗盖尔
蒂文德拉·K.·萨达纳
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Description

SiGe and manufacture method thereof on relaxation, the low defective insulator
Technical field
The present invention relates to make a kind of method of semiconductor substrate materials, more particularly, relate to make a kind of relaxation basically, SiGe (SiGe-on-insulator, SGOI) method of backing material on the low defective insulator.The present invention also relates to have a kind of SGOI backing material of above-mentioned character and the structure that comprises SGOI backing material of the present invention at least.
Background technology
In semi-conductor industry, complementary metal oxide semiconductors (CMOS) (CMOS) is used, with strain, based on the heterostructure of Si to obtain high carrier mobility structure, done huge effort.Traditionally, in order to improve the performance of NFET and PFET, the implementation method in the prior art is developing strain layer on thick (from about 1 to about 5 microns magnitude) relaxation SiGe resilient coating.
Though the heterostructure of prior art has been reported high channel electron mobility; But several noticeable shortcomings that are attached thereto are arranged with thick SiGe resilient coating.At first, thick SiGe resilient coating usually is difficult for and is existing, combines based on the CMOS technology of Si.The second, defect concentration comprises line dislocation (TD) and misfit dislocation, is from about 10 6To about 10 8Defective/cm 2, this VLSI for reality (integrated very on a large scale) should be used for saying, is still too high.The 3rd, the character of prior art structure is got rid of the selective growth of SiGe resilient coating, to use strain Si and not have strain Si and the circuit of each device of SiGe material is difficult to, in some cases, is bordering on and can not be integrated comes out.
In order on the Si substrate, to form (relaxed) SiGe material of relaxation, the method of prior art grow usually layer of even or gradual change, or the SiGe layer of ladder, it (also is such thickness that its thickness surpasses metastable critical thickness, surpassing this thickness dislocation will form to discharge stress) and make misfit dislocation and relevant line dislocation, in the SiGe layer, form.Thereby used various buffer structures to reduce TD density with the length that attempt is increased in misfit dislocation district in the structure.
When strain SiGe layer metastable under the typical prior art was annealed under sufficiently high temperature, misfit dislocation will form and grow, thereby removed the whole strains in the film.Elastic strain when in other words, film begins is disengaged because of the plastic strain of lattice.To the metastable strain SiGe of growing on the SOI substrate under the prior art, experiment shows, under overwhelming majority's annealing/oxidizing condition, the formation of misfit dislocation for greater than 700 ℃ temperature, occurs in the commitment of annealing process.Many in these defectives are during the high annealing of structure or be consumed or buried in oblivion, yet between the heat of oxidation, the configuration of surface of original mismatch array is still keeping.
In addition, the method for making the SGOI backing material with thermal diffusion in the prior art can not fully make SiGe alloy-layer relaxation.But final SiGe lattice is just expanded the part of equilibrium valve, because between the heat of oxidation, the value for any one given little attempt relaxation of SiGe film all has contiguous volume on its each limit, the power of a resistance of they effects relaxation.For example, observe, when forming the SGOI backing material with the hot mixed method of prior art, under certain condition, the relaxation of last SiGe alloy, for a specific SOI origination wafer and an initial SiGe alloy-layer, can be saturated on certain value between 40 to 70%.
This saturated meaning reaches a kind of equilibrium condition between strain relief mechanism and elastic energy, this balance in the part relaxation, is keeping in the SGOI material of part compressive strain.For side direction (also promptly the being parallel to substrate surface) size that makes a compressive strain layer perfect elasticity relaxation (not having defective to form) film must increase in some way.Up to now, prior art do not provide any method to increase the SiGe alloy firm lateral dimensions so that relaxation force greater than the power of resistance relaxation.
In view of making the problems referred to above that a kind of fundamental relaxation SGOI backing material method has in the prior art, exist new and a kind of lasting needs that improve one's methods, with for a SOI substrate, can form the single crystalline Si Ge resilient coating of relaxation basically.Term " relaxation basically " or " height relaxation " are meant so a kind of SGOI substrate, and wherein final SiGe alloy is by relaxation about 50% to about 100%.Other 100% relaxation shows that this SiGe layer has (non-strain) diamond cubic lattice, and its lattice constant is by the ratio decision of Ge, and it all equates in three host lattice directions.
Summary of the invention
It is a kind of thin to an object of the present invention is to provide manufacturing, the method for high-quality SGOI backing material.
It is a kind of thin that another object of the present invention provides manufacturing, the method for high-quality SGOI backing material, and this backing material has the relaxation (50% or higher) of associated suitable high level.
It is a kind of thin that another purpose of the present invention provides manufacturing, the method for high-quality SGOI backing material, and this backing material does not have substantially or do not have associated blemish.
It is a kind of thin that a further object of the present invention provides manufacturing, the method for high-quality SGOI backing material, and this backing material has associated defect concentrations in crystals significantly still less.
It is a kind of thin that another purpose of the present invention provides manufacturing, the method for high-quality SGOI backing material, and this method has used and the treatment step of complementary metal oxide semiconductors (CMOS) (CMOS) treatment step compatibility.
Another object of the present invention provide make a kind of thin, high-quality, the SGOI backing material of relaxation basically, when forming strain Si layer, it can also be a substrate as the template of a lattice mismatch.
Another purpose of the present invention provides strain Si/ fundamental relaxation SGOI structure, and it has high carrier mobility, and this is useful in high-performance CMOS is used.
Purpose of these and other and advantage, obtain with so a kind of method in the present invention, wherein with a step that forms pattern, on Ge diffusion impervious layer top, form the structure of the island of the island that comprises single crystalline Si and strain SiGe alloy or part relaxation SiGe layer.Make Si and SiGe layer form island-shaped pattern and changed the local power that acts on each island edge by this way, make relaxation force greater than the power of revolting relaxation.The shortage restoring force just makes final SiGe film want further relaxation compared with continuous film on the patterned layer edge having.
This Ge diffusion impervious layer can be as a kind of viscosity medium, and lateral movement can take place on the film island thereon, but this only just generation in enough hour of the linear-scale on the island.How for a short time, be only " enough little ", this point depends on the thickness of relaxation film, acts on lateral stress total on the interface and Mechanical Properties of Materials.Viscid-elastic property that the residing temperature of lateral expansion is decided by to be buried the Ge barrier layer can take place in the SiGe island.Specifically also promptly, stop that the barrier layer of Ge diffusion shows the temperature of viscosity (it flows).The enough ion injection methods of this energy are introduced impurity and are controlled in the Ge barrier layer.For example, boron is injected the Ge barrier layer and can be used for reducing the temperature that deformation relaxation takes place on the island.
The notion of pattern island enhancing relaxation also can extend to direct SiGe alloy-layer high temperature, original place (in situ) on the Si island and optionally grow, and the Si island then is to pass through the formation of formation method of patterning on original continuous thin silicon on insulator layer.So this relaxation SiGe island, original place can be as the ground Si growth of the selective property of lattice template, this will cause the elongation strain in the Si layer.A kind of selective epitaxial Si growing method also can be used in strained silicon on relaxation SiGe island.
The present invention is used for relaxation, low defective SGOI backing material the basically method of a kind of formation, may further comprise the steps:
On one first single crystal Si layer surface, form one deck Si xGe 1-xLayer, x=0 or wherein less than a number of 1, and there is an interface on described first single crystal Si layer and the following barrier layer that can resist the Ge diffusion;
Make described Si xGe 1-xLayer and described first single crystal Si layer form pattern so that a figuratum structure to be provided; And
Heat described figuratum structure in certain temperature, this temperature allows the relaxation in the internal strain of figuratum layer, and later Ge is at whole figuratum first single crystal Si layer and figuratum Si xGe 1-xInterior diffusion in the layer, thus one deck formed basically by the single crystalline Si Ge layer of relaxation at the top on a part of barrier layer.
In another method of the present invention, used following step:
On one first single crystal Si layer surface, form one deck Si xGe 1-xLayer, x=0 or wherein less than a number of 1, and there is an interface on described first single crystal Si layer and the following barrier layer that can resist the Ge diffusion;
Heat for the first time described each layer under certain temperature, this temperature allows Ge at whole first single crystal Si layer and Si xGe 1-xInterior diffusion in the layer is to form on the top on barrier layer or single crystalline Si Ge layer part relaxation or abundant strain;
On single crystalline Si Ge layer, form pattern; And
Heat for the second time single crystalline Si Ge layer under certain temperature, this temperature allows the further relaxation of single crystalline Si Ge layer, to form one deck single crystalline Si Ge layer of relaxation basically on the top on a part of barrier layer.
Of the present inventionly be used for forming relaxation basically, another method of low defective SGOI backing material may further comprise the steps:
Make one first single crystal Si layer form the pattern of an in advance definite geometry; And one deck epitaxy Si Ge layer of on described geometry, optionally growing, its growth temperature allows described SiGe layer original place relaxation, thereby forms one deck SiGe zone of relaxation basically.
In the described in front method of the present invention, the geometry of formation patterned layer is square or rectangle normally.Form pattern and be used for changing the effect that acts on local power on each edge, bar island by this way, so that relaxation force is greater than the power of resistance relaxation.The shortage that forms restoring force on the patterned layer edge make last SiGe film compared with thin be that relaxation gets more under the continuous situation.Except the enhancing relaxation of SiGe layer, because the island is allowed to flexibly relaxation (by the lateral expansion on oxide layer) rather than plastically (by introducing the defective that discharges strain), last defect concentration has been reduced.
Notice that the single crystalline Si Ge layer of the relaxation basically that is formed by above-mentioned any one embodiment of the present invention comprises Si xGe 1-xThe uniform mixing of the layer and first single crystal Si layer.In addition, the single crystalline Si Ge layer of the fundamental relaxation defect concentrations in crystals that minimum blemish arranged and reduced.
Follow above-mentioned treatment step, can be on the top of relaxation single crystalline Si Ge layer basically epitaxial growth one ply strain Si layer optionally, with form strain Si/ basically relaxation SiGe this can be used in the heterostructure of multiple high-performance CMOS in using.
In some application of the present invention, first single crystal Si layer and barrier layer are the parts of silicon-on-insulator (SOI) structure.In other was used, the barrier layer was to form on the top of semiconductor substrate surface, formed first monocrystalline silicon layer afterwards on the barrier layer, and a kind of backing material in back is a kind of non-SOI substrate.
In another application of the invention, first single crystal Si layer is an extremely thin layer, the about 50nm of its thickness or littler.The use of thin initial single crystalline layer forms last SGOI thickness and the required amount of oxidation of Ge concentration is useful reducing, and under the situation that the oxidation that exposes sidewall to the open air on figure island must reduce, this is useful.
This method has also been studied with the Ge barrier layer (also being that the barrier layer is continuous) that does not form pattern or has been formed the barrier layer (also promptly, separately and the zone or the island of isolating, their are enclosed with semi-conducting material) of pattern.
In another application of the invention, before this structure of heating, at Si xGe 1-xThe alloy-layer top is gone up and is formed one deck Si cap layer.This embodiment of the present invention provides thermodynamically stable (on the meaning that prevents the defective generation), approaches, basically SiGe (SGOI) backing material on the insulator of relaxation.Note, when in conjunction with high-quality, when the SiGe material adopts " approach " this term on the insulator of fundamental relaxation, show the about 2000nm of thickness of the uniform SiGe layer by this inventive method formation or littler, and its thickness is more desirable about 10 to about 200nm.
Another aspect of the present invention relates to SiGe (SGOI) backing material on the insulator that forms with said method.Specifically, backing material of the present invention comprises a slice and contains the Si substrate, is containing the insulating regions that opposing Ge diffusion is arranged on the silicon substrate top; With one deck on insulating regions top SiGe layer of relaxation basically, have an appointment 2000nm or littler thickness of the SiGe layer of relaxation basically wherein, about 50% or the bigger relaxation value that records, there are not or do not have blemish and about 5 * 10 basically 6/ cm 2Or littler defect concentrations in crystals.
Another aspect of the present invention relates to a kind of heterostructure, which comprises at least above-mentioned backing material.Specifically, this heterostructure of the present invention comprises a slice and contains silicon substrate, is containing the insulating regions that a low anti-Ge diffusion is arranged on the top of silicon substrate; And on top, exhausted level zone, one deck SiGe layer of relaxation is basically being arranged, and have an appointment 2000nm or littler thickness of the SiGe layer of relaxation basically wherein, about 50% or the bigger relaxation value that records, there are not or do not have blemish and about 5 * 10 basically 6/ cm 2Or littler defect concentrations in crystals; Si layer with a ply strain that on the top of the SiGe layer of relaxation basically, forms.
Other aspects of the present invention are except relating to the template as other lattices imbalance structures, and this template comprises SiGe backing material on the insulator of the present invention at least, also relates to superlattice structure.
Description of drawings
Figure 1A-1F provides the present invention to be used for making height relaxation, the diagram (sectional view) of the basic handling step of first embodiment of low defective SGOI backing material.
Fig. 2 A-2B is the diagram (sectional view) that provides another embodiment of the invention, wherein forms one deck Si cap layer on SiGe alloy-layer top, and the SiGe alloy-layer does not form pattern (1A) or forms on the substrate of pattern (1B) at one.
Fig. 3 A-3F provides the present invention to be used for making height relaxation, the diagram (sectional view) of the basic handling step of second embodiment of the SGOI backing material of low defective.
Fig. 4 is a structure that can form with SGOI backing material of the present invention.
Fig. 5 A-5C provides the present invention to be used for making height relaxation, the diagram (sectional view) of the basic handling step of the 3rd embodiment of the SGOI material of low defective.
Embodiment
Now with reference to should with accompanying drawing be described in detail that to the invention provides manufacturing thinner, high-quality, the method for SiGe backing material on the insulator of height relaxation, and this backing material can be used as after the template of the epitaxy Si lattice mismatch of growing.Note in the accompanying drawings representing identical and/or corresponding elements with identical several the showing of participating in government and political affairs.
Earlier with reference to Figure 1A and Figure 1B, they provide two kinds dissimilar can be used in initial substrate materials of the present invention.Specifically, the initial substrate materials of drawing in Figure 1A-1B comprises and contains silicon semiconductor substrate 10, can resist the barrier layer 12 (back claims the barrier layer) that Ge spreads at the one deck that contains on the top, surface of silicon semiconductor substrate 10, and first single crystal Si layer 14 on the top on barrier layer, it has less than about 1 * 10 5Defective/cm 2Misfit dislocation and TD dislocation density.The difference of two kinds of initial configurations that drawn in the drawings is, in Figure 1A, the barrier layer exists on total continuously, and in Figure 1B, the barrier layer exists with discrete and regional island that separate, and they are by semi-conducting material, and also promptly layer 10 and 14 surrounds, thereby comprise a barrier layer that does not have pattern in the structure shown in Figure 1A, and the initial configuration among Figure 1B comprises a figuratum barrier layer.
No matter there is pattern on the barrier layer or does not have pattern, this initial configuration can be a kind of silicon-on-insulator (SOI) backing material, and wherein the zone 12 is that a quilt buries oxide areas (BOX), it first monocrystalline silicon layer 14 with contain Si Semiconductor substrate 10 electricity and keep apart.So-called " siliceous " is meant a kind of Semiconductor substrate that comprises silicon at least herein, indicative example includes, but are not limited to: Si, SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC etc., and preformed silicon-on-insulator (SOI) structure can be included in the quilt of the arbitrary number that exists in this structure and buries oxide layer (continuously, discontinuous, or continuous and discrete mixture).
This SOI substrate can be with the SIMOX of routine well-known to those skilled in the art (injecting separately with oxonium ion) method, and at the United States Patent (USP) that transfers people such as Sadaua jointly, the patent No. 09/861,593 is submitted to May 21 calendar year 2001; 09/861,594, submit to May 21 calendar year 2001; 09/861,590, submit to May 21 calendar year 2001; 09/861,596, submit to May 21 calendar year 2001; And 09/884,670, June 19 calendar year 2001 and United States Patent (USP) NO.5, the 930634 various SIMOX methods of being mentioned form, and the full content of each patent inserts for your guidance at this.Notice that the method for announcing can be used to be manufactured on the figuratum substrate shown in Figure 1B herein in 590 use.
Perhaps, the SOI backing material also can be made with other conventional methods, comprise, for example, thermal bonding and cutting method.
Except the SOI substrate, also can be a kind of non-SOI substrate at the substrate shown in Figure 1A and Figure 1B, it uses conventional deposition process and photoetching and corrosion (using) when making a figuratum substrate.Specifically, when using non-SOI substrate, initial configuration is used in and contains the surface of silicon top by conventional deposit or heat growth method deposit one deck Ge diffusion impervious layer, the photoetching process of available routine and corrosion if necessary makes the barrier layer form pattern, use conventional deposition process afterwards again, comprise, for example, chemical vapor deposition (CVD), plasma assisted CVD, sputter, evaporation, chemical solution deposit or epitaxy Si growth form one deck monocrystalline silicon layer with the top on the barrier layer.
Barrier layer 12 at initial configuration shown in Figure 1A and the 1B comprises any insulating material, and it has the resistivity of height to the diffusion of Ge.The example of this insulation and opposing Ge diffusion material includes, but not limited to the crystal of oxide or nitride or noncrystal.
The thickness of each layer of initial configuration depends on method used when making them.Yet say that typically single crystal Si layer 14 has from about thickness of 1 to about 2000nm, it is highly preferred that little about 10 to about 200nm thickness.Under the situation of barrier layer 12 (also promptly resisting the layer of Ge diffusion), this layer can have from about thickness of 1 to about 1000nm, it is highly preferred that from about thickness of 20 to about 200nm.Containing layer-of-substrate silicon, also is the thickness of layer 10, irrelevant with the present invention.Notice that above-mentioned thickness is exemplary, never places restrictions on scope of the present invention.
For simplicity, all the other steps of the present invention are only used the initial configuration shown in Figure 1A.Yet these remaining steps are equally useful to the initial configuration shown in Figure 1B.
Fig. 1 C draws and form one deck Si on the top of single crystal Si layer 14 xGe 1-xLayer 16 (wherein x be 0 or less than 1 number) after formed structure.Later on " Si xGe 1-x" layer is called one deck SiGe alloy-layer.This SiGe alloy-layer among the present invention can include the Ge (at this moment x is less than 1) up to 99.99 atomic percentages, and germanium Ge (x=0 at this moment), also promptly comprises the SiGe alloy of 100 atomic percentage Ge.In one embodiment of the invention, the content of Ge is preferably in about 0.1 between about 99.9 atomic percentages in the SiGe alloy-layer, the atomic percentage of Ge is then better between about 10 to about 35, in the figure, and the interface that reference number 13 refers between barrier layer 12 and monocrystalline silicon Si layer 14.
According to the present invention, on the top of single crystal Si layer 14, form the SiGe alloy and be with a kind of in the field epitaxy method of the known routine of technical staff, this method can (i) growth one deck thermodynamically stable (under a certain critical thickness) SiGe alloy, or the one deck of (ii) growing metastable and do not have defective, promptly do not have the SiGe alloy-layer of misfit dislocation and TD dislocation.Can satisfy condition (i) or the example of this growing method (ii) comprises, but be not limited to: its cavitation vapor deposition (UHVCVD) of low pressure chemical vapor deposition (LPCVD) superelevation, atmospheric pressure chemical vapor deposition (APCVD), molecule come extension (MBE) and plasma enhanced chemical vapor deposition (PECVD).
In this moment of the present invention, formed SiGe alloy-layer can have different-thickness, but typically, layer 16 can have from about thickness of 10 to about 500nm, and thickness is then more desirable to about 200nm from about 20.
In another embodiment of the invention, consult Fig. 2 A-2B, carrying out before the heating steps of the present invention, on the top of SiGe alloy-layer 16, form one deck and select cap layer 18 for use.The used in the present invention cap layer of selecting for use comprises any Si material, includes, but are not limited to: epitaxial silicon (epi-Si), and amorphous silicon (a:Si), monocrystalline or polycrystalline Si or their combination in any comprise composite bed.In a preferred embodiment, this cap layer comprises epi Si.Notice that layer 16 and 18 can not form yet in same reative cell in same reative cell.
When selecting cap layer 18 for use, it has from about thickness of 1 to about 100nm, and its thickness is then desirable about 1 to about 30nm.This selects for use the available any deposition process of knowing of epitaxial growth method noted earlier that comprises of cap layer to form.
In one embodiment of the invention, on the surface of single crystal Si layer, be preferably formed as SiGe alloy (Ge atomic percentage the be 15 and 20) layer of a layer thickness from about 1 to about 200nm, form the Si cap layer of thickness from about 1 to 100nm afterwards at the top of SiGe metal.
Then, this structure no matter whether it selects Si cap layer for use, makes dominant shape become the structure of pattern to obtain being drawn as among Fig. 1 D.Specifically, this structure no matter whether it selects Si cap layer for use, is used conventional photoetching process and corroding method to make and is had pattern.The step of this photoetching process is included on the surface of structure, promptly or in the SiGe metal or selecting for use on the top of Si cap layer cloth with photoresist (not drawing), again photoresist is exposed to the open air under the width of cloth of all patterns is penetrated, again with a kind of Resist development agent of routine in photoresist, to set up pattern.Attention has the photoresist of figure and has protected this part-structure, and other parts of bar structure expose to the open air out simultaneously.Then, when the photoresist with pattern was stayed the original place, the exposed portion of bar structure eroded to the top on barrier layer 12 and stops.In certain embodiments, the corrosion step exposed portion of having removed the SiGe alloy-layer and the single crystal Si layer below SiGe alloy exposed portion like this, and in other embodiments, select for use the Si cap at first to be corroded, and SiGe alloy-layer and the single crystal Si layer below it just is removed afterwards.
Corrosion step can realize to form with single corrosion step or with multiple corrosion step, for example, and in the structure shown in Fig. 1 D.No matter carry out single or multiple corrosion step, can use conventional dry etching method, as if reaction-ion etching, plasma etching, ion beam etching, laser ablation or their any combination are corroded.Except dry corrosion, the present invention considers that equally this corrosion step also can comprise uses moist chemical corrosion method, perhaps realizes with combination moist and the dryness corrosion.When with moist chemical corrosion, with a kind of compared with removing oxide or nitride, to removing the chemical mordant that Si has high selectivity, after corrosion, in process of the present invention at the moment, remove photoresist with the conventional resist process of sloughing with figure.
SiGe layer 16, Si layer 14 also has, and if present, cap layer 18 these figuratum layer that selectivity is used are called an island here.Notice that though the formation of only drawing a single island structure among the figure, the present invention also considers and form a plurality of this island structures on the surface on barrier layer 12.These islands are normally little dimensionally, and its lateral width is approximately 500 μ m or littler.Preferably, there is the lateral width from about 0.01 μ m to 100 μ m on these islands.It should be noted that the relaxation that must be enough to allow the SiGe film by the width on the formed island of the present invention, the power that this will be by guaranteeing relaxation in the zone, island is greater than the power of opposing relaxation.
In certain embodiments, can of the present invention this time be engraved in to form on the SiGe alloy-layer 16 patterned surfaces tops and select Si cap layer for use.This embodiment of the present invention is not drawn in the present invention particularly.
Then the figuratum structure heating that comprises above-mentioned island, also i.e. annealing, its temperature to allow strain the SiGe alloy-layer relaxation and make after Ge by first single crystal Si layer 14, SiGe alloy-layer 16, and, if present, select diffusion in the Si cap layer for use, thereby on the top, barrier layer, form relaxation basically, single crystalline Si Ge layer 20 (consulting Fig. 1 E).Relaxation annealing can separately be carried out with interior diffusion annealing, perhaps is combined into an annealing process.Heating can be carried out in a tube furnace or with rapid thermal annealing (RTA) equipment.Attention forms one deck oxygen layer 22 on the top of layer 20 in heating steps.This oxide layer typically but not always, not removed from structure with conventional moist caustic solution behind heating steps, wherein uses to resemble HF and compared with SiGe the height chemical mordant is arranged for removing oxide like this.This oxide layer also can be removed with the dryness caustic solution as the reactive ion etching.
Note when oxide layer is removed after, can on the top of layer 20, forming one deck second layer single crystal Si layer, and that above-mentioned treatment step of the present invention can repeat is any repeatedly to obtain a multilayer, by the SiGe backing material of relaxation.
The oxide layer that heating steps of the present invention forms later on has a transformable thickness, and its scope is from about 2 to about 2000nm, and is preferable from about 2 to 500nm.
Specifically, heating steps of the present invention is an annealing steps, and it carries out under from about 900 ° to 1350 ℃ in temperature, then is being preferable from temperature about 1200 ℃ to 1335 ℃.In addition, heating steps of the present invention can carry out in certain oxidizing atmosphere, and this can comprise at least a oxygen-containing gas, as if O 2, NO, N 2O, H 2O (water vapour), ozone, air and change similar oxygen-containing gas.This oxygen-containing gas can mix (as if O mutually 2Mix with NO), perhaps this gas can dilute with a kind of inert gas, as if He, Ar, N 2, Xe, Kr or Ne.
The time that heating steps carries out can be different, and typical scope is from about 10 to about 1800 minutes, and the time was preferable from about 60 by about 600 minutes.Heating steps can carry out under a single target temperature, perhaps can enough various fade rate and soaking time different gradual changes and the soak period formed.
This heating steps can carry out in oxidizing atmosphere, to obtain a surface oxide layer, promptly the layer 22, it plays the effect of diffusion impervious layer to the Ge atom.Therefore in case in body structure surface formation oxide layer, Ge just becomes and is trapped between barrier layer 12 and the oxide layer 22.Along with the thickness increase of surface oxide layer, Ge is at layer 14,16 and select for use the distribution in the layer 18 just to become more and more even, but it is prevented to invade oxide layer constantly and effectively.So when this (homogenized now) layer is thinned, the ratio of Ge will increase so relatively in heating steps.Among the present invention,, when in the oxygen-containing gas of a dilution, carrying out, obtain effectively heat mixing when heating steps arrives under about 1320 ° temperature at about 1200 °.
Here also consider to go to be based on the fusing point of SiGe alloy-layer this heating cycle with a specific heating cycle.In this case, temperature is adjusted to the fusing point that is lower than the SiGe alloy slightly.
Notice that if oxidation is carried out too soon, then Ge can not spread fast enough from oxide on surface/SiGe interface, and or carry (and losing) by oxide, perhaps become Tai Gao so that temperature of the interface humidity of Ge will reach the melting point of alloy.
Heating steps role of the present invention be (1) thus keep one to distribute uniformly to allow during annealing the Ge atom to spread faster; And (2) make (at the beginning) have strain the layer be subjected to a heat supply, reach equilibrium configuration to impel.After carrying out this heating steps, this structure comprises one uniformly, and the SiGe alloy-layer of fundamental relaxation is a layer 20 also, and it is clipped between barrier layer 12 and the surface oxide layer 22.
This heating steps also can carry out in a nonoxidizing atmosphere.In this case, this annealing just makes Ge homogenizing in first single crystalline Si and SiGe layer.Lateral dimensions on the island of pattern is very little, thereby under the situation that the oxidation of structure can consume owing to the lateral oxidation of sidewall, then this annealing steps is preferable.
According to the present invention, have an appointment 2000nm or littler thickness of the SiGe layer 20 of relaxation is then more desirable at about 10 to 200nm thickness basically.Notice that the SiGe layer of the relaxation basically of formation will approach compared with the SiGe resilient coating in the prior art in the present invention, and its defect concentration comprises misfit dislocation and line dislocation, is about 5 * 10 6Defective/cm 2Perhaps still less.
The composition of the final Ge of the SiGe layer of the relaxation basically of Xing Chenging is from about 0.1 to about 99.9 atomic percentages in the present invention, and the atomic percentage of Ge is then more desirable about 10 to about 35.Basically another feature of the SiGe layer 20 that eliminates stress is that it has one about 50% or the bigger lattice relaxation degree that measures, if the lattice relaxation degree that measures is from about 75 to 100% then more desirable.Notice that 100% slackness is the most desirable in the present invention.
As previously mentioned, surface oxide layer 22 can be removed in this stage of the present invention, so that SiGe backing material on the insulator to be provided, for example, shown in Fig. 1 F.
Above-mentioned discussion illustrated in Figure 1A-1F, is the representative of first embodiment of the present invention.With reference to Fig. 3 A-3F, discuss second embodiment in more detail below, it is included in and forms the heating steps that eliminates stress that pattern has a part before.
Fig. 3 A provides the used initial structure of second embodiment of a present invention (it contains Ge barrier layer 12 and is clipped in monocrystalline silicon layer 14 and contains between the silicon substrate 10).Attention is identical with the structure shown in Figure 1A in the structure shown in Fig. 3 A.Except utilizing this concrete initial configuration, also can use in the structure shown in Figure 1B.
Then, on the top of first single crystal Si layer 14, formed SiGe alloy-layer 16 with former described treatment step, to obtain the structure shown in Fig. 3 B.In this moment of method of the present invention, can on SiGe alloy-layer top, form and select Si cap layer 18 for use, after this, allow this structure,, stand one first heating steps no matter whether select Si cap layer for use, it carries out under a such temperature, and this temperature allows Ge by first single crystal Si layer and Si xGe 1-xThe interior diffusion of layer, thus be formed on the partly relaxation or the single crystalline Si Ge layer 19 of strain fully on the top, barrier layer 12.First heating steps of the present invention carries out under about 1335 ℃ temperature at about 900 ℃, carries out then more desirable under the temperature between about 1150 ° to about 1320 ℃.
In addition, first heating steps of the present invention is to carry out in a kind of oxidation oxygen atmosphere, and this atmosphere comprises a kind of oxygen-containing gas at least, as if O 2, NO, N 2O, H 2O (steam), ozone, air and other similar oxygen-containing gass.Oxygen-containing gas can mix (O for example mutually 2With the mixture of NO, perhaps this gas can dilute with certain inert gas, as if use He, Ar, N 2, Xe, Kr, or Ne.First heating steps can carry out the different time, and is typically from about 10 in about 1800 minutes scope, then more desirable in the scope of about 60 to 600 minutes clock times.This first heating steps can carry out under certain single target temperature, also different gradual changes and the even heat cycle that can form with various fade rate and soaking time.
Formed structure exists after first heating steps, for example, and shown in Fig. 3 C.Formation or part relaxation, perhaps the SiGe layer 19 of complete strain are pushed up in attention, first heating steps on 12 surfaces, barrier layer.Also note in addition,, on the top of the SiGe of part relaxation layer, begin to form the thin oxide layer of one deck in this moment of the present invention.Yet for the sake of clarity, the oxide layer that this layer is thin is omitted in the drawings.
Then, as former discussion, make SiGe layer 19 form patterns, to obtain the figuratum structure shown in Fig. 3 D.The SiGe island that forms is just like preceding described identical lateral width.After forming pattern, structure as shown in Fig. 3 D stands heating steps for the second time again, this step is carried out under such temperature, and this temperature allows the further relaxation of single crystalline Si Ge layer to be clipped on the top on a part of barrier layer and forms the single crystalline Si Ge layer 20 of relaxation basically, consults Fig. 3 E.Attention has layer of oxide layer 22 on the SiGe of relaxation layer top.The thickness of oxide layer 22 can extremely thin (Asia-nanometer) or is thicker, also depends on annealing oxygen atmosphere and temperature.
Second heating steps of the present invention carries out under about 1335 ° temperature at about 900 °, carries out under about 1320 ℃ temperature then more desirable at about 1150 °.In addition, second heating steps of the present invention can carry out in certain oxidizing atmosphere, and this oxidizing atmosphere comprises at least a oxygen-containing gas, as if O 2, NO, N 2O, H 2O (water vapour), ozone, air or other similar oxygen-containing gass.Oxygen-containing gas can mix (as if O mutually 2Mixture with NO) or this gas can dilute with a kind of inert gas, as if He, Ar, N 2, Xe, Kr, or Ne.Second heating steps also can carry out in a kind of nonoxidizing atmosphere to reduce the consumption and the distortion on pattern island.Second heating steps can carry out the different time, and is between about 1 to about 1800 minutes, then more desirable between about 10 to about 600 minutes usually.Second heating steps can carry out under a single target temperature, also can spare thermal cycle with the different gradual change that various fade rate and even hot time are formed.
Fig. 4 has provided resulting structure after forming Si layer 24 on the SiGe layer top of Fig. 1 F or Fig. 3 F.Specifically, Si layer 24 is to form with the known selective epitaxial precipitation method in present technique field.Epitaxy Si layer 24 can have different thickness, but typically, epi-Si layer 24 has from about thickness of 1 to about 100nm, and is then more desirable from about thickness of 1 to 30nm.
Fig. 5 A-5C provides third party's method of the present invention, in this third party's method, first single crystal Si layer 14 of a SOI wafer (comprising Ge barrier layer 12 and Semiconductor substrate 10 equally), photoetching process and corrosion by routine, be formed pattern, comprise a structure determining geometry earlier thereby form, for example, shown in Fig. 5 A.After forming pattern, growing epitaxial SiGe optionally under such temperature, this temperature is enough high causing SiGe layer original place relaxation, thus Fig. 5 B is consulted in the SiGe zone 20 of formation fundamental relaxation.
With a kind of selectively deposited method resemble CVD, and about 600 ℃ or higher of its deposition temperature, the original place relaxation has just taken place.Preferably the original place occur in from about 800 ° under about 1100 ℃ temperature.
Notice that the single crystal Si layer 14 of the geometry in SiGe zone 20 and formation pattern is basic identical.Fig. 5 C is given in structrural build up Si layer 24 shown in Fig. 5 B.
In some cases, can use foregoing treatment step, on the SiGe of relaxation layer 20 top, form additional SiGe, form epi-Si layer 24 afterwards again.Because layer 20 has big plane lattice parameter compared with extension-layer 24, thereby epitaxial loayer 24 will have a strain of stretching character.
Still be in the 3rd embodiment no matter above-mentioned the first, the second, can be before this structure of heating, with conventional ion method for implanting well-known to those skilled in the art boron or other similar foreign ion injection Ge barrier layers.In the present invention, this foreign ion is used to reduce the temperature that elastic relaxation can take place.Specifically, foreign ion is injected the Ge barrier layer can reduce nearly 300 ℃ of relaxation temperatures, in addition more.
Still be in the 3rd embodiment no matter, can both be located on or near the interface of imbedding oxide/top Si so that inject the peak of ion distribution by this way coming the hydrogen hydrogen ion to inject above-mentioned the first, the second.This can strengthen the relaxation of SiGe layer, and can be used in combination with formation method of patterning described herein.Hydrogen ion injects and can be used in the common transfer U.S. and use series number 10/196.On July 16th, 611,2002 application, in technology and the condition announced carry out, its full content is incorporated herein for participating in government and political affairs.Also can be, and use deuterium without hydrogen ion, helium, neon and other similar ions, as long as they can or form defective at the interface and allow mechanically decoupled (mechanical decoupling) near the first crystal Si/ barrier layer.Here also consider to use the mixture of above-mentioned ion.Preferred ion comprises hydrogen ion, and preferred condition comprises: ion concentration is less than 3E16 atom/cm 2With inject energy from about 1 to about 100keV.This ion can be in aforementioned three embodiments any one on, before or after forming pattern, inject.
As previously mentioned, the present invention not only thinks over the lattice mismatched structures that comprises SiGe on the insulator of the present invention (SGIO) backing material at least, also thinks over superlattice structure.Under the superlattice structure situation, this structure will comprise SiGe backing material on the insulator of fundamental relaxation of the present invention at least, and the Si that replaces and the SiGe layer that form on the top of the SiGe layer of the fundamental relaxation of backing material.
Under the situation of lattice mismatched structures, can on the top of the SiGe layer of the fundamental relaxation of SiGe (SGOI) backing material on the insulator of the present invention, form GaAs, Gap or other similar III/V compound semiconductors.
Following Example is provided to illustrate the present invention's some advantage compared with the hot mixed method of routine.
Example
Having 300 Si are arranged 0.8Ge 0.2The deposit epitaxial loayer has the heat under high temperature (from 1200 ° to 1320 ℃) of Si " cap " layer the such initial configuration of 350 SIMOX SOI of one deck 200 to mix again, and finding to be somebody's turn to do (continuously) film did not have relaxation.In other words, even Ge mixes at each interlayer, and oxidized process concentrates, and the SiGe film on oxide still keeps lattice parameter in the plane of block Si.Elastic strain energy in this one deck is also less than plastic relaxation.Also promptly, the formation of strain relief defective, required value, thereby relaxation process does not take place at all.
Thereby form pattern by some regional island that depicts film of removing original Si/SiGe/SOI film with identical initial configuration and before heating.The size on pattern island does not wait, its edge from a few tenths of micron to the hundreds of micron.Carry out same heating steps, figuratum structure is measured with X-ray diffraction (big beam sizes is asked average on many characteristic sizes), and measuring is 87% relaxation.With plane graph transmission electron microscope (PV-TEM) (with not Ah's analysis) further studies show that to each structure, the edge eliminates stress up to the island of 10 μ m complete (100%), and big structure division ground or relaxation asymmetricly, this depends on the size and dimension on island.
The SiGe island of causing in this way flexibly another key character of relaxation is not have defective fully, and this measures with PV-TEM.Be arranged in scanning and the upper limit of defective＜1 * 10 5Cm -2Do not find defective later at all.(x-ray analysis of 600 on 350 SIMOXSOI-17%SiGe) provides 99% relaxation, shows that the certain relaxation of thick film gets more to thick initial SiGe layer.
Though provide and described the present invention particularly with reference to its preferred embodiment, but for it will be appreciated by those skilled in the art that, can not depart under the spirit and scope of the present invention, can do aforesaid aspect form and the details and other change.Thereby the inventor requires the present invention not to be subjected to placing restrictions on of described herein and the concrete form that draws and details, and is positioned the scope of appended claims.

Claims (66)

1. one kind forms relaxation, low defective SGOI backing material basically method, comprises following steps:
On one first single crystal Si layer surface, form a Si xGe 1-xLayer, x=0 or wherein less than a number of 1, there is an interface on the barrier layer of described first single crystal Si layer and following opposing Ge diffusion;
Make described Si xGe 1-xLayer and described first single crystal Si layer form pattern so that a figuratum structure to be provided; And
Heat described figuratum structure at a certain temperature, heating-up temperature make to allow the deformation relaxation in figuratum layer, and permission subsequently at figuratum first single crystal Si layer and figuratum Si xGe 1-xThe interior diffusion of Ge in the layer, thus form one basically by the single crystalline Si Ge layer of relaxation at the top on a part of barrier layer.
2. the process of claim 1 wherein that described barrier layer is a barrier layer that forms pattern.
3. the process of claim 1 wherein that described barrier layer is a barrier layer that does not form pattern.
4. the process of claim 1 wherein that described barrier layer comprises the implanting impurity ion that is incorporated into this layer.
5. the process of claim 1 wherein described Si xGe 1-xLayer forms with a kind of epitaxial growth method, this method is from by the low pressure chemical vapor deposition, the atmospheric pressure chemical vapor deposition, the high vacuum chemical vapor deposition, molecular beam epitaxy, the plasma enhanced chemical vapor deposition is selected in the group of methods that ion assisted deposition or any other similar deposition technology are formed.
6. the method for claim 1, also be included in carry out heating steps before, at described Si xGe 1-xForm one deck Si cap layer on the top of layer.
7. the method for claim 6, wherein said silicon cap layer comprises epi-Si, a:Si, monocrystalline or polycrystalline Si or their combination in any and composite bed.
8. the process of claim 1 wherein that described formation pattern step comprises photoetching and corrosion.
9. the process of claim 1 wherein and during described heating steps, form the layer of surface oxide layer.
10. the method for claim 9 also comprises with a kind of moist chemical corrosion method or dryness corrosion and removes described surface oxide layer.
11. the process of claim 1 wherein that described heating is to carry out in comprising a kind of oxidizing atmosphere of at least a oxygen-containing gas.
12. the method for claim 11, wherein said at least a oxygen-containing gas comprises O 2, NO, N 2O, water vapour, ozone, air or their mixture.
13. the method for claim 11 also comprises a kind of inert gas, described inert gas is used for diluting described at least a oxygen-containing gas.
14. the process of claim 1 wherein that described heating is to carry out in a kind of nonoxidizing atmosphere that comprises any one inert gas or their mixture.
15. the process of claim 1 wherein that described heating is to carry out under about 1350 ℃ temperature from about 900 °.
16. the method for claim 15, wherein said heating are to carry out under about 1335 ℃ temperature from about 1200 °.
17. the method for claim 1, growth one additional SiGe layer is gone up on the SiGe layer top that also is included in described relaxation basically.
18. the method for claim 17 also is included in described additional SiGe layer top and goes up the Si layer that forms a ply strain.
19. the method for claim 1, the Si layer that forms a ply strain is gone up on the SiGe layer top that also is included in described relaxation basically.
20. thereby the process of claim 1 wherein that can form defective allows mechanically decoupled ion at the interface on described interface or near described, be injected into described Si before or after described formation pattern step xGe 1-xLayer.
21. the method for claim 20, wherein said injection ion packet is hydrogeneous, deuterium, helium, oxygen, neon or their mixture.
22. the method for claim 21, wherein injecting ion is hydrogen ion.
23. one kind forms relaxation, low defective SGOI backing material basically method, comprises following steps:
On one first single crystal Si layer surface, form a Si xGe 1-xLayer, x=0 or wherein less than a number of 1, there is an interface on the barrier layer of described first single crystal Si layer and following opposing Ge diffusion;
Allowing Ge at first single crystal Si layer and Si xGe 1-xHeat for the first time described each layer in layer under the temperature of diffusion, on the top on barrier layer, to form or single crystalline Si Ge layer part relaxation or complete strain;
On single crystalline Si Ge layer, form pattern; And
Under the temperature of the further relaxation that allows single crystalline Si Ge layer, heat single crystalline Si Ge layer for the second time, on the top on a part of barrier layer, to form the single crystalline Si Ge layer of relaxation basically.
24. the method for claim 23, wherein said barrier layer are barrier layers that forms pattern.
25. the method for claim 23, wherein said barrier layer are barrier layers that does not form pattern.
26. the method for claim 23, wherein said barrier layer comprises the implanting impurity ion that is incorporated into this layer.
27. the method for claim 26, wherein said foreign ion are used for reducing the temperature that the barrier layer allows elastic relaxation.
28. the method for claim 23, wherein said Si xGe 1-xLayer forms with a kind of epitaxial growth method, this method is from by the low pressure chemical vapor deposition, the atmospheric pressure chemical vapor deposition, the high vacuum chemical vapor deposition, molecular beam epitaxy, the plasma enhanced chemical vapor deposition is selected in the group of methods that ion assisted deposition or any other similar deposition technology are formed.
29. the method for claim 23, also be included in described first heating steps before, at described Si xGe 1-xForm one deck Si cap layer on the top of layer.
30. the method for claim 29, wherein said Si cap layer comprises epi-si, a:si, monocrystalline or polycrystalline Si or their combination in any or composite bed.
31. the method for claim 23, wherein said formation pattern step comprises photoetching and corrosion.
32. the method for claim 23 wherein forms the layer of surface oxide layer during described heating steps.
33. the method for claim 32 also comprises with a kind of moist chemical corrosion method or dryness corrosion and removes described surface oxide layer.
34. the method for claim 23, wherein said first heating and second heating all are to carry out in comprising a kind of oxidizing atmosphere of at least a oxygen-containing gas.
35. the method for claim 23, wherein said second annealing is what to carry out in a kind of nonoxidizing atmosphere that comprises inert gas or their mixture.
36. the method for claim 34, wherein said at least a oxygen-containing gas comprises O 2, NO, N 2O, water vapour, ozone, air or their mixture.
37. the method for claim 34 also comprises a kind of inert gas, described inert gas is used to dilute described at least a oxygen-containing gas.
38. the method for claim 23, wherein said first heating are to carry out under about 1335 ℃ temperature from about 900 °.
39. the method for claim 20, wherein said second heating is to carry out under about 1150 ° to 1320 ℃ temperature.
40. the method for claim 23, the additional SiGe layer of growth one deck is gone up on the SiGe layer top that also is included in described relaxation basically.
41. the method for claim 40 also is included in described additional SiGe layer top and goes up the Si layer that forms a ply strain.
42. the method for claim 23 also is included on the SiGe layer top of described relaxation basically, forms the Si layer of a ply strain.
43. the method for claim 23 wherein can form defective, thereby allows mechanically decoupled ion at the interface on described interface or near described, is injected into described Si before or after described formation pattern step xGe 1-xLayer.
44. the method for claim 43, wherein said injection ion is a hydrogen, deuterium, helium, oxygen, neon or their mixture.
45. the method for claim 44, wherein said injection ion is a hydrogen ion.
46. a backing material comprises:
One contains silicon substrate:
At the described insulating regions that has an opposing Ge to spread on the top of silicon substrate that contains; And
The one SiGe layer of relaxation is basically arranged on described insulating regions top, and the SiGe layer of wherein said relaxation basically have an appointment 2000nm or littler thickness have an appointment 50% or the bigger relaxation value that records and 5 * 10 6Or littler defect concentration.
47. the backing material of claim 46, wherein said insulating regions are to form pattern.
48. the backing material of claim 46, wherein said insulating regions are not form pattern.
49. the backing material of claim 46, wherein said insulating regions comprises crystallization or amorphous oxides, perhaps crystallization or amorphous nitride.
50. being formation quilts pattern or that do not form pattern, the backing material of claim 46, wherein said insulating regions bury oxide regions.
51. a heterostructure comprises:
One contains silicon substrate;
Containing the insulating regions that opposing Ge diffusion is arranged on the top of silicon substrate;
The one SiGe layer of relaxation is basically arranged on the top of insulating regions, and this have an appointment 2000nm or littler thickness of SiGe layer of relaxation basically wherein has an appointment 50% or the bigger relaxation value that records and 5 * 10 6Or littler defect concentration; And
The Si layer of a strain that on the top of the SiGe of described relaxation basically layer, forms.
52. the heterostructure of claim 51, wherein said insulating regions are to form pattern.
53. the heterostructure of claim 51, wherein said insulating regions are not form pattern.
54. the heterostructure of claim 51, wherein said insulating regions comprises crystallization or amorphous oxides, perhaps crystallization or amorphous nitride.
55. the heterostructure of claim 51, wherein said insulating regions are to form quilt pattern or that do not form pattern to bury zoneofoxidation.
56. the heterostructure of claim 51 wherein forms relaxation SiGe layer and strain Si layer alternately on the Si of described strain layer top.
57. the heterostructure of claim 51, the Si layer of wherein said strain uses the compound of a kind of lattice mismatch of selecting in the group of being made up of the III/V compound semiconductor to replace.
58. one kind forms relaxation, low defective SGOI backing material basically method, comprises following steps:
Make one first single crystal Si layer form the pattern of a geometry of being scheduled to; And
With respect to the described geometry epitaxy Si Ge layer of optionally growing, its growth temperature allows described SiGe layer original place relaxation, thereby forms the SiGe zone of relaxation basically.
59. the method for claim 58, wherein said first single crystal Si layer are parts of SOI substrate.
60. the method for claim 58, wherein said epitaxy Si Ge layer are to form under about 600 ℃ or higher deposition temperature.
61. the method for claim 58, wherein said epitaxy Si Ge layer are to form under about 1100 ℃ deposition temperature at about 800 ℃.
62. the method for claim 58, wherein said epitaxy Si Ge layer forms with CVD.
63. the method for claim 58, formation one deck Si layer is gone up on the top, SiGe zone that also is included in described relaxation basically.
64. the method for claim 58, thus its intermediate ion can form defective described first single crystal Si layer and below the barrier layer between on the interface that forms or mechanically decoupled near allowing at the interface.
65. the method for claim 64, wherein said injection ion packet is hydrogeneous, deuterium, helium, oxygen, neon or their mixture.
66. the method for claim 65, wherein said injection ion is a hydrogen ion.
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