CN1263037C - Method and apparatus to control temp of component - Google Patents
Method and apparatus to control temp of component Download PDFInfo
- Publication number
- CN1263037C CN1263037C CNB998136662A CN99813666A CN1263037C CN 1263037 C CN1263037 C CN 1263037C CN B998136662 A CNB998136662 A CN B998136662A CN 99813666 A CN99813666 A CN 99813666A CN 1263037 C CN1263037 C CN 1263037C
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- China
- Prior art keywords
- temperature
- control device
- electronic circuit
- equipment
- electronic unit
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Abstract
When a component, such as a memory device, exhibits an overtemperature condition (e.g., exceeds a first threshold value), the data transmission rate with respect to the component is reduced so as to lower its operating temperature. In one embodiment, this is achieved by changing the latency at which data packets are transmitted to and from the memory device in dependance on the temperature of the device. Controlling temperature in such a fashion allows for efficient use of the component over a large range of temperatures.
Description
Background of invention
The present invention relates to control the method for temperature and the equipment of parts.More specifically, the present invention relates to by reducing the whereabouts parts and/or controlling the method for temperature and the equipment of these parts from the data transfer rate of parts.
Electronic unit, such as storer (for example, static RAM (SRAM)), chipset (for example, Intel Company, Santa Clara, California, the 82430FX PCI of manufacturing group), graphics controller and processor processing device (for example, the Pentium II processor that Intel Company makes), all be the electronic circuit that generates heat at run duration.Maximum temperature when in many cases, the technical manual of these parts is indicated this parts true(-)running.If parts surpass this temperature, some problematic states then may appear.At first, the data-signal that transmitted of parts entail dangers to and or be stored in data-signal in the parts.This causes depending on the mistake in other parts of such data-signal.In addition, excessive heat can cause each circuit in the parts to be subjected to irreversible infringement.
The program step of undue temperature problem in the some kinds of control assemblies (such as above-mentioned electronic unit) has been proposed.In a system, when parts became too hot, it was turned off (that is, outage) and requires the user to turn-off department of computer science and unifies and connect (preferably after the computing machine cooling) once more.
For the problem that such system occurred be: the use of computing machine is because the outage of computer system and energising and be interrupted fully.Therefore need a kind of method and apparatus that allows the hot temperature in the control assembly and do not need to carry out such interruption in use.
Brief summary of the invention
According to embodiments of the invention, provide a kind of equipment of control assembly temperature.This equipment comprises control device, and it is suitable for being connected to these parts and is suitable for temperature according to parts being controlled at message transmission rate between control device and the parts.
The accompanying drawing summary
Fig. 1 is the total block scheme according to the system of embodiments of the invention structure.
Fig. 2 is the block scheme of example of the system of Fig. 1.
Fig. 3 a-b is the block scheme according to the DRAM memory module of embodiments of the invention structure.
Fig. 4 a-b is the process flow diagram according to the method for embodiments of the invention.
Describe in detail
With reference to Fig. 1, show total block scheme on the figure according to embodiments of the invention.A kind of control device is provided, and it sends data to parts 12 and/or receives data from parts.As used herein, data, order, control, address and other such signal should be thought to comprise widely in term " data ".Parts 12 produce heat at its run duration, this at least partially since reception cause from the data of control device 11.Parts 12 can produce temperature signal and send this signal to control device.For example, this temperature signal can be plussage of actual work temperature, predetermined threshold value or the like.According to the temperature signal from parts 12, control device 11 reduces the speed that data are sent to the speed of parts 12 and/or receive data from parts 12.
With reference to Fig. 2, be presented at the circuit of Fig. 1 under the computing system environments on the figure.In the embodiment of Fig. 2, computer system 20 comprises processor 21 (for example, the Pentium II processor that Intel Company makes), and the latter is connected to chipset 22 (for example, the 82430FX PCI group of Intel Company's manufacturing).In this example, chipset 22 comprises Memory Controller center (hub) 22a and I/O (I/O) controller center 22b.These controllers are called as " north bridge road " and " south bridge road " technically sometimes respectively.Memory Controller center 22a can pass through bus 23 (for example, the bus of moving according to peripheral component interconnect (PCI) technical manual (Rev.2.1, the special interest group of PCI, Hillsboro, Oregon, 1995)) and be connected to I/O controller center 22b.If want, graphics controller 24 can be connected to Memory Controller center 22a (for example, by advanced graphics port (A.G.P.) interface (seeing the A.G.P. Technical Interface Specification, correction 1.0,1996, Intel Company)).Memory Controller center 22a comprises memory status register 31, and the latter is connected to Memory Controller 32.Memory Controller is connected to one or more storage arrangements, such as dynamic RAM (DRAM) device 33a-c (for example, the DRAM device of Rambus, Rambus company, Mountain View, California).
Fig. 3 a-b shows the example of a DRAM device.On Fig. 3 a, storage arrangement 33a comprises circuit board 41 (such as printed circuit board (PCB) (PCB)), and a plurality of memory module 42a-d are installed on it.In the present embodiment, thermal sensor 43 is fixed on the circuit board 41 and (for example, passes through bolt).Thermal sensor 43 comprises output signal line (being described below).On Fig. 3 b, shown the side view of the storage arrangement 33a of Fig. 3 a.In this example, utilize heat sink 46a that compressible, heat conducting elastic body 45 is pressed on memory module (for example, memory module 42c-d) and the thermal sensor 43.Heat sink 46a-b is made by suitable heat conducting material, and is connected by pin (for example, pin 42c-d).When operation, thermal sensor 43 can detect the heat that is produced by the memory module that is connected to circuit board 41 by elastic body 45 and heat sink 46a-b.
In this example, the temperature of the memory module of thermal sensor 43 perception in memory module 33a.For example, thermal sensor 43 can comprise that the thermistor known (promptly, the analog device of the resistance that has the environment temperature of being proportional to and change) and analog digital converter, it is transformed into digital value (not specifically illustrating on Fig. 2) to the analog voltage on the thermistor latter.Then this digital value and threshold value (that is, the numerical value of the maximum operation temperature that representative is wanted) are compared, and on signal wire 44, produce the pulse signal that an expression threshold value has been exceeded.May wish that threshold value is set to be lower than the maximum operation temperature of setting forth in its technical manual.
In the embodiment of Fig. 2, be connected to general purpose I/O (GPIO) pin on IO controller center 22b from the signal wire 44 of sensor 43.Alternatively, the thermal sensor on additional memory module 33b-c can have the signal wire (unit 50-51) that is connected to this GPIO pin.In this case, signal wire 44,50 and 51 is used as and is added to or door 55 input.Therefore, when on one or more memory module 33a-c, over temperature condition occurring (for example, temperature surpasses first threshold value), (for example by its corresponding sensor, sensor 43) produce appropriate signals, and this signal by or door be sent to the GPIO pin of I/O controller center 22b.In this example, the overtemperature signal at 22b place, I/O controller center makes that producing an interruption is added to processor 21.The example of suitable interruption is included in the system management interrupt (SMI) that exists in the Pentium of all Intel and the Pentium II processor, interrupt (SCI) with system control and (see " the ACPI technical manual " of Intel Company etc., draft correction 1.0, Dec.22,1996).As replying, processor 21 is over temperature condition notice Memory Controller center 22a.In the example of Fig. 2, this is to finish to memory status register 31 by suitable numerical value being write (or login).
Memory Controller 32 control in the 22a of Memory Controller center from and/or to the transmission (for example, write and read) of the data of DRAM device 33a-c.In the present embodiment, data are sent out and receive according to packet oriented protocol.Each grouping transmits according to stand-by period (latency) value (for example, after grouping has been ready to, for this transmitted in packets is measured to DRAM device 33a-c and/or from the time delay of wherein this packet data transmission being come out).For example, at normal operation period, when DRAM device 33a-c did not present over temperature condition, latency value should be low, and is preferably zero.Memory Controller 32 is checked the content of memory status register 31 periodically.When register 31 was illustrated in over temperature condition among the DRAM device 33a-c, Memory Controller 32 increased latency value, so that slow down data transmission between Memory Controller center 22a and DRAM 33a-c.Whereabouts/from the working temperature that reduces can cause reducing these devices of the data traffic flow of DRAM 33a-c.Therefore, although over temperature condition occurs, DRAM 33a-c still continues operation (though being according to slower data throughput), rather than turn-offs fully.When message transmission rate is reduced, whereabouts/can thereupon be slowed down from the transmission of data other device (for example, graphics controller 24), that be added to DRAM 33a-c.
When the temperature on DRAM 33a-c is reduced to when being lower than the predetermined second threshold value, another signal (for example from sensor 43) be sent to I/O controller center 22b the GPIO pin (by or the door 55), represent that these devices are just operating in enough low temperature, thereby allow to improve message transmission rate for Memory Controller center 22a.When I/O controller center 22a receives such signal, will make second to interrupt being added to processor 21.As replying, processor 21 is placed into suitable numerical value in the memory status register 31 and (for example, the numerical value that is stored in the there is resetted).New numerical value in the register 31 makes Memory Controller 32 reduce latency value (for example, dropping to zero) and the message transmission rate of raising between Memory Controller center 22a and DRAM 33a.
In above-mentioned embodiments of the invention, DRAM device 33a-c remains running in suitable speed.Yet, might will be prevented from the interruption between I/O controller center 22b and the processor 21.For example, one group of code (being called as virus technically) of being carried out by processor 21 can make these interruptions not carry out.According to an alternative embodiment of the invention, can add and go up other unit, surpass the fixed temperature of maximum amount to prevent DRAM device 33a-c.I/O controller center can comprise a counter, and it begins counting when the GPIO pin receives signal.When counter 60 expires, determine whether IO controller center 22b produces interruption after the preset time interval.If it does not produce, then send suitable message to Memory Controller center 22a by bus 23 or the private bus between these parts 61 from I/O controller center 22b.As replying, Memory Controller center 22a is provided with suitable numerical value in memory status register 31, as expression in the above-described embodiment.When temperature is reduced to when being lower than second threshold value, the signal of the result on the GPIO pin can be used for producing immediately suitable message and give Memory Controller center 22a, or counter can be used for allowing IO controller center 22b to have producing the chance of interrupting.For above example, the message that is received by Memory Controller center 22a makes memory status register reset, and therefore improves whereabouts/from the data rate of DRAM device 33a-c.
Shown method on Fig. 4 a-4b according to embodiments of the invention.At square 101, system is initialised, and supposes that wherein all parts all operate under the acceptable temperature.Like this, whereabouts/from the message transmission rate of parts 12 (see figure 1)s is normal value (for example, rate) at full speed.At Decision Block 103, determine whether parts (for example, the parts 12 of Fig. 1, or the storer of Fig. 2 are such as DRAM storer 33a-c) present over temperature condition.If overtemperature do not occur, then Decision Block 103 is got back in condition control.Otherwise control enters piece 105 (Fig. 4 b), and counter can randomly be activated therein.(Fig. 4 a) produces an interruption (for example, the I/O controller center 22b by Fig. 2 produces) at square 107.At square 109, login over temperature condition (for example, suitable data being written in the memory status register 31 of Fig. 2).At Decision Block 110 (Fig. 4 b), whether monitor counter expires.If expire, then control enters Decision Block 111, to determine whether to produce interruption (for example, at square 107).If it's not true, then with direct mode login over temperature condition (for example, by the direct communication between the I/O of Fig. 2 controller center 22b and Memory Controller center 22a).
(Fig. 4 a) reduces message transmission rate, so that reduce the working temperature (Fig. 1) of parts 12 at square 113.At Decision Block 115, determine whether working temperature is reduced to and be lower than second threshold value.At Decision Block 117, determine before whether to have produced interruption the over temperature condition of square 107 (for example, in response to).If then control enters square 118 (Fig. 4 b).Produce new interruption therein, login not enough temperature conditions then and (for example, suitable data are written in the memory status register 31 of Fig. 2; Square 119).Do not interrupt if before produced, then control directly enters square 119, logins not enough temperature conditions with aforesaid direct mode.At square 121, improve data rate, so that improve performance.
In the example of Fig. 1-4, use first and second temperature threshold values.When parts surpassed first temperature threshold values, data rate was reduced to predetermined speed.When temperature is reduced to when being lower than second temperature threshold values, data rate is added to its original numerical value.It will be apparent to those skilled in the art that the method and apparatus shown in Fig. 1-4 can be modified, so that handle the threshold value of additional centre.For example, when temperature surpassed first (with the highest) threshold temperature value, message transmission rate was reduced to first (with minimum) numerical value.Surpass a middle threshold temperature (that is, a temperature between first and second threshold temperatures) if temperature is lower than first threshold value, then data rate can be set to be in original (full rate) numerical value and a middle numerical value of minimum numerical value.Therefore, this characteristic of the application of the invention, message transmission rate can be according to the working temperature of parts optimization better.
Though here specifically show and described embodiment, it will be appreciated that, modification of the present invention and become example and covered by above instruction, and be in the scope that does not deviate from spirit of the present invention and requirement in the qualification of appended claims.For example, though show each independent device on Fig. 1 and 2, many devices can be divided into independently parts, or are integrated into bigger parts.In addition, the present invention can be applicable to the parts except storage arrangement.Yet when using storage arrangement, the write operation that the message transmission rate between control device and storage arrangement can be by reducing each unit interval or the number of times (rather than number of times of these the two kinds of operations at one time) of read operation are reduced.
Claims (12)
1. equipment of controlling the temperature of electronic unit, this electronic unit is chosen from storer, chipset, graphics controller and processor, and this equipment comprises:
Control device, be suitable for being connected to this electronic unit, wherein said control device is suitable for temperature according to described electronic unit and is controlled at message transmission rate between described control device and the described electronic unit, wherein, described message transmission rate comprises and will be stored in the data transmission in the described electronic unit and/or be stored in data in the described electronic unit to the transmission of described control device.
2. the equipment of claim 1 is characterized in that, wherein when the temperature of described electronic unit surpassed first threshold value, described control device reduced described message transmission rate.
3. the equipment of claim 2 is characterized in that, the memory storage that wherein said electronic unit is made up of electronic circuit.
4. the equipment of claim 3 is characterized in that, wherein said control device is the Memory Controller center.
5. the equipment of claim 4, it is characterized in that, wherein said Memory Controller center comprises Memory Controller, described Memory Controller is suitable for sending packet to the described memory storage of being made up of electronic circuit with a latency value, when the temperature of the described memory storage of being made up of electronic circuit surpasses described first threshold value, increase described latency value.
6. the equipment of claim 5 is characterized in that, wherein is reduced to when being lower than second threshold value when the temperature of the described memory storage of being made up of electronic circuit, reduces described latency value.
7. the equipment of the temperature of the memory storage be made up of electronic circuit of a control comprises:
By the memory storage that electronic circuit is formed, it comprises:
At least one memory module;
Be connected to the temperature sensor of described memory module;
Circuit board, wherein said memory module and described temperature sensor are connected to described circuit board; With
Be connected to the heat conduction elastic body of described memory module and described temperature sensor, and
A control device that is connected to the described memory storage of forming by electronic circuit, described control device is suitable for being controlled at described control device and the described data transfer between storage devices speed of being made up of electronic circuit according to the temperature of the described memory storage of being made up of electronic circuit, wherein, described message transmission rate comprises and will be stored in the data transmission in the described memory storage of being made up of electronic circuit and/or be stored in data in the described memory storage of being made up of electronic circuit to the transmission of described control device.
8. the equipment of claim 7 is characterized in that, wherein when the temperature of the described memory storage of being made up of electronic circuit surpassed first threshold value, described control device reduced described message transmission rate.
9. the equipment of claim 8 is characterized in that, wherein said control device is the Memory Controller center.
10. the equipment of claim 9, it is characterized in that, wherein said Memory Controller center comprises Memory Controller, described Memory Controller is suitable for forwarding packets to the described memory storage of being made up of electronic circuit with a latency value, when the temperature of the described memory storage of being made up of electronic circuit surpasses first threshold value, increase described latency value.
11. the equipment of claim 10 is characterized in that, wherein is reduced to when being lower than second threshold value when the temperature of the described memory storage of being made up of electronic circuit, reduces described latency value.
12. the method for temperature of control electronic unit, this electronic unit is chosen from storer, chipset, graphics controller and processor, and this method comprises:
Be controlled at message transmission rate between control device and the described electronic unit according to the temperature of described electronic unit, wherein, described message transmission rate comprises and will be stored in the data transmission in the described electronic unit and/or be stored in data in the described electronic unit to the transmission of described control device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13621398A | 1998-08-18 | 1998-08-18 | |
| US09/136,213 | 1998-08-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1328687A CN1328687A (en) | 2001-12-26 |
| CN1263037C true CN1263037C (en) | 2006-07-05 |
Family
ID=22471860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB998136662A Expired - Fee Related CN1263037C (en) | 1998-08-18 | 1999-08-13 | Method and apparatus to control temp of component |
Country Status (6)
| Country | Link |
|---|---|
| CN (1) | CN1263037C (en) |
| AU (1) | AU5398199A (en) |
| DE (1) | DE19983470B4 (en) |
| GB (1) | GB2358944B (en) |
| HK (1) | HK1041975B (en) |
| WO (1) | WO2000011675A1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7269481B2 (en) | 2003-06-25 | 2007-09-11 | Intel Corporation | Method and apparatus for memory bandwidth thermal budgetting |
| US8122187B2 (en) | 2004-07-02 | 2012-02-21 | Qualcomm Incorporated | Refreshing dynamic volatile memory |
| US7454586B2 (en) * | 2005-03-30 | 2008-11-18 | Intel Corporation | Memory device commands |
| US9262326B2 (en) | 2006-08-14 | 2016-02-16 | Qualcomm Incorporated | Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem |
| CN102014201B (en) * | 2010-09-29 | 2014-04-30 | 中兴通讯股份有限公司 | Data card temperature control method and device |
| US10088880B2 (en) * | 2015-08-27 | 2018-10-02 | Intel Corporation | Thermal monitoring of memory resources |
| CN107678986B (en) * | 2017-09-28 | 2021-06-22 | 惠州Tcl移动通信有限公司 | USB3.0 transmission rate setting method, mobile terminal and storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3916263A (en) * | 1971-12-13 | 1975-10-28 | Honeywell Inf Systems | Memory driver circuit with thermal protection |
| US4881057A (en) * | 1987-09-28 | 1989-11-14 | Ranco Incorporated | Temperature sensing apparatus and method of making same |
| US5276843A (en) * | 1991-04-12 | 1994-01-04 | Micron Technology, Inc. | Dynamic RAM array for emulating a static RAM array |
| AU6988494A (en) * | 1993-05-28 | 1994-12-20 | Rambus Inc. | Method and apparatus for implementing refresh in a synchronous dram system |
| US5451892A (en) * | 1994-10-03 | 1995-09-19 | Advanced Micro Devices | Clock control technique and system for a microprocessor including a thermal sensor |
| JP4090088B2 (en) * | 1996-09-17 | 2008-05-28 | 富士通株式会社 | Semiconductor device system and semiconductor device |
| US5784328A (en) * | 1996-12-23 | 1998-07-21 | Lsi Logic Corporation | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
-
1999
- 1999-08-13 AU AU53981/99A patent/AU5398199A/en not_active Abandoned
- 1999-08-13 DE DE19983470T patent/DE19983470B4/en not_active Expired - Fee Related
- 1999-08-13 CN CNB998136662A patent/CN1263037C/en not_active Expired - Fee Related
- 1999-08-13 GB GB0103092A patent/GB2358944B/en not_active Expired - Fee Related
- 1999-08-13 WO PCT/US1999/018433 patent/WO2000011675A1/en active Application Filing
-
2002
- 2002-05-17 HK HK02103763.7A patent/HK1041975B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| HK1041975A1 (en) | 2002-07-26 |
| DE19983470B4 (en) | 2011-08-18 |
| GB0103092D0 (en) | 2001-03-28 |
| DE19983470T1 (en) | 2001-07-12 |
| GB2358944A (en) | 2001-08-08 |
| GB2358944B (en) | 2002-12-11 |
| CN1328687A (en) | 2001-12-26 |
| HK1041975B (en) | 2007-02-23 |
| WO2000011675A1 (en) | 2000-03-02 |
| AU5398199A (en) | 2000-03-14 |
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