CN1254184A - Dynamic random access memory capacitor manufacture method - Google Patents
Dynamic random access memory capacitor manufacture method Download PDFInfo
- Publication number
- CN1254184A CN1254184A CN 98124199 CN98124199A CN1254184A CN 1254184 A CN1254184 A CN 1254184A CN 98124199 CN98124199 CN 98124199 CN 98124199 A CN98124199 A CN 98124199A CN 1254184 A CN1254184 A CN 1254184A
- Authority
- CN
- China
- Prior art keywords
- layer
- storage node
- node contacts
- nitride
- contacts window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The production method of capacitor includes the following steps: including multiple material, sandwiching nitride layer between oxide layers, opening storage node contact window in multiple material of alternative oxide layer and nitride layer and stopping to contact pad, along side wall of the contact window removing partial nitride layer, and forming conformal first immediate doped polycrystalline silicon layer on top oxide layer and its contact window, forming a layer of photoresist layer in contact window, removing the first immediate doped polycrystalline silicon layer and removing the photoresist layer, forming conformal thin dielectric layer on top oxide layer and in its contact window, and on the thin dielectric layer forming second immediate doped polycrystalline silicon layer and filling up its contact window.
Description
The present invention relates to a kind of manufacture method of semiconductor memory, particularly relate to the manufacture method of fin-shaped groove structure (Fin-trench-structure) capacitor of a kind of dynamic random access memory (Dynamic Random Access Memory-DRAM).
The density that increases the DRAM integrated circuit is the trend of DRAM manufacturing now.Yet, when making the DRAM unit of higher density, in the DRAM unit, can reduce the usable floor area of making required capacitor relatively.In order to guarantee to keep under the reliable standard, can dwindle the area of capacitor, therefore under the situation that the capacitor area occupied reduces, it is important keeping the capacitance of each capacitor constant.Recently, the capacitor that proposes to have three-D space structure was once arranged, to increase the capacitance of memory cell, this kind capacitor comprises double stacked formula (Double-stacked) capacitor, fin structure (Fin-Structured) capacitor, crown shape capacitor, launches stack (Spread-stacked) capacitor and box-like (Box) structure capacitive device.
It is minimum that foundation can make manufacturing cost reduce to, and provide maximum manufacturing degree of containing so that production efficiency reaches maximum capacitor manufacture method, also is the problem that urgent need will solve.Below bit line in the manufacture craft of (Capacitor Under Bit Line-CUB), form storage node contacts at the capacitor of standard to link to each other with then pad (LandingPad).Have now and then fill up in the manufacturing time micron following technology of being everlasting, in order to dwindle the volume of memory cell, for example the Samsung of Korea S is exactly that the capacitor manufacturing of finishing in the DRAM unit is then filled up in use on a large scale.After forming memory node, carry out the deposition of silica-silicon-nitride and silicon oxide (Oxide-Nitride-Oxide-ONO), then form the top electrode of capacitor.In this prior art, need three photoresist masks to finish the manufacturing of DRAM capacitor, promptly be when forming storage node contacts window, memory node and capacitor top electrode, need to use three photoresist masks.Then, carry out the planarization manufacture craft of capacitor, then, form bit line contacting window and bit line.Because the ladder height drop of memory node is big, its difference in height is about 4000 dusts between 7000 dusts, and it is very difficult therefore will reaching good planarization effect.
The object of the present invention is to provide a kind of capacitor that is used in to be arranged in bit line below manufacture craft, the manufacture method of the fin-shaped groove structure capacitor of dynamic random access memory.Method of the present invention reduces the use of a photoresist mask than prior art, and can exempt when the problem that increases the long-pending capacitor planarization that is produced of capacitor surface, so it is minimum that the present invention can make manufacturing cost reduce to, and can provide the manufacturing tolerance of maximum so that production efficiency is brought up to maximum.
The object of the present invention is achieved like this, promptly provide a kind of in a substrate with the then pad that joins with source/drain regions, form the manufacture method of the fin-shaped groove structure capacitor of dynamic random access memory, this method comprises: formation comprises the alternating oxidation layer of a top oxide layer and a multiple thing of nitride layer, and wherein this each nitride layer is sandwiched between this each oxide layer; In the multiple thing of this oxide layer that replaces and nitride layer, form the storage node contacts window, this storage node contacts window stops at this and then fills up; Along the sidewall of this storage node contacts window, divest this nitride layer of part; Above this top oxide layer, form one first instant doped polysilicon layer, and conformal in the sidewall of this storage node contacts window, and with this then pad contact; Deposition one photoresist layer above this substrate; Divest this photoresist layer that is positioned at outside this storage node contacts window; Divest this first instant doped polysilicon layer of part that is positioned on this top oxide layer; Divest this photoresist layer; Above this top oxide layer, form a thin dielectric layer, and conformal this first instant doped polysilicon layer on the sidewall of this storage node contacts window; And above this thin dielectric layer with this storage node contacts window in, form one second instant doped polysilicon layer.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 to Fig. 3 and Fig. 5 to Fig. 8 are the flow process cutaway view of manufacture method of the fin-shaped groove structure capacitor of dynamic random access memory according to the preferred embodiment of the invention;
Fig. 4 A and Fig. 4 B are used to form the photoresist mask vertical view of storage node contacts window according in two preferred embodiments of the present invention.
Fig. 1 to Fig. 3 and Fig. 5 to Fig. 8 are the manufacture method flow process cutaway view of the fin-shaped groove structure capacitor of dynamic random access memory according to the preferred embodiment of the invention.The present invention's appended figure of will arranging in pairs or groups is described in detail as follows.The invention provides the manufacture method of capacitor of the dynamic random access memory of a fin-shaped groove structure, utilize manufacture method of the present invention can reduce the number of the photoresist mask of required use and the problem that can exempt the capacitor planarization.
Please refer to Fig. 1, semiconductor substrate 100 at first is provided.This semiconductor-based end, can comprise semiconductor wafer, and be formed with active and non-active member in this wafer, and multilayer is covered on this wafer.Therefore, substrate one title means form element in wafer, and forms multilayer cover above wafer.In this preferred embodiment, substrate 100 comprises drain region 102.In substrate 100, form the polysilicon that connects drain region 102 and then fill up 104. Wherein form substrate 100 and 104 the method for then filling up is known by haveing the knack of this operator, therefore do not need to do discussion more at this.
Then please refer to Fig. 2, carry out the alternating deposit step of oxide layer 106a, 106b, 106c and nitride layer 108.In this preferred embodiment, between bottom oxidization layer 106a and the intermediate oxide layer 106b, and between intermediate oxide layer 106b and the top oxide layer 106c, each is separated with one deck nitride layer 108 respectively.Wherein, the preferred thickness of each layer oxide layer is about 500 dusts to the 1500 Izod right sides, and the preferred thickness of each nitride layer 108 is about 1500 dusts between 2500 dusts.The formation method of oxide layer 106a, 106b and 106c comprises Low Pressure Chemical Vapor Deposition (Low PressureChemical Vapor Deposition-LPCVD) traditionally, and the formation method of nitride layer 108 for example is with LPCVD also for utilizing conventional method.
Continue please refer to Fig. 3, utilize traditional photoetching making technology and etching process to constitute and open storage node contacts window 110.In the preferred case, storage node contacts window 110 is positioned then to fill up 104 top, and for example, deposition covers one deck photoresist layer 112 on top oxide layer 106c, constitutes this photoresist layer 112, and forms storage node contacts window 110.Fig. 4 A and Fig. 4 B are the vertical view of photoresist mask.In the shown embodiment of Fig. 4 A, it is the storage contact hole that 0.35～0.5 μ m multiply by 0.2～0.4 μ m that photoresist mask is opened a size.And in the shown embodiment of Fig. 4 B, it is the storage contact hole that 0.2～0.4 μ m multiply by 0.2～0.4 μ m that photoresist mask is opened a size.Be generally and avoid alignment error (Misalignment), the preferred size of storage node contacts window 110 needs less than the size of then filling up 104.Then, carry out one or many anisotropic etching (Anisotropic Etching) step with etching oxide layer 106a, 106b, 106c, and nitride layer 108, reach bottom oxidization layer 106a always.Then, carry out slower oxide layer etching process, stop at the control etching process and then fill up on 104, thus, expose the sidewall 114 of oxide layer 106a, 106b, 106c and nitride layer 108.Afterwards, utilize traditional method that causes resist of delustering to divest photoresist layer 112.
Then, please refer to Fig. 5, with hot phosphoric acid solution, by sidewall 114 nitride etching layers 108.The preferred thickness of the nitride layer of removing along side surface direction 108 is about 500 to the 3000 Izod right sides.
Then please refer to Fig. 6, on top oxide layer 106c with storage node contacts window or groove 110 in, form first conformal instant (In-situ) doped polysilicon layer 116, this method that forms the first conformal instant doped polysilicon layer 116 comprises traditional chemical vapour deposition technique.As illustrating among Fig. 6, this first instant doped polysilicon layer 116 does not fill up storage node contacts window 110 fully, and its thickness end decided by the thickness of nitride layer 108, and its preferred thickness is about between 250 to 750 dusts.The first instant doped polysilicon layer 116 with then fill up 104 and be connected, and can be as the bottom electrode of capacitor.Though, in Fig. 6, only show two-layer fin structure 118,, can infer thus and learn, after the oxide layer and nitride layer of alternating deposit multilayer, also can obtain the fin structure of multilayer.
Follow again, please refer to Fig. 7, on the surface of the first instant doped polysilicon layer 116 and in the storage node contacts window 110, form spin-coating photoresist 120, and fill up storage node contacts window 110.Then carry out the etch-back manufacture craft, be removed up to the spin-coating photoresist 120 that is positioned at outside the storage node contacts window 110.Afterwards; carry out the etch-back manufacture craft; divesting the part first instant doped polysilicon layer 116 that is positioned on the top oxide layer 106c, and spin-coating photoresist 120 is arranged in the part first instant doped polysilicon layer 116 on the sidewall of storage node contacts window 110 in order to protection.Above-mentioned manufacture craft result such as Fig. 7.
Follow again, please refer to Fig. 8, divest the spin-coating photoresist 120 that is arranged in storage node contacts window 110.Subsequently, deposition of thin dielectric layer 122, the material of this thin dielectric layer 122 for example is silicon oxide/silicon nitride/silicon oxide or nitrogenize silicon/oxidative silicon.Then, deposition one deck second instant doped polysilicon layer 124 also fills up storage node contacts window 110, and the preferred thickness of this second instant doped polysilicon layer 124 is about between 500 to 1500 dusts.Afterwards, carry out traditional photoetching and etching process, constitute the second instant doped polysilicon layer 124, finish the manufacturing of capacitor to form an opening 125.
The opening 125 that forms in the second instant doped polysilicon layer 124 is the usefulness that is connected with the contact of then filling up 104 as bit line.Because after constituting the etching second instant doped polysilicon layer 124, the landform difference of height of the second instant doped polysilicon layer 124 500 to the 1500 Izod right sides of only having an appointment, therefore, banish the etch-back method of closing with boron-phosphorosilicate glass (BPSG) stream or boron-phosphorosilicate glass, can reach follow-up manufacturing bit line contacting window and the required flatness of bit line completely.Compared with prior art, in the prior art, when the height of memory node is about between 4000 to 7000 dusts, and the thickness of top electrode is about 500 to 1500 Izods when right, and its Terrain Elevation difference is about between 5000 to 8500 dusts.
Though disclosed the present invention in conjunction with an above preferred embodiment; yet it is not in order to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, thus protection scope of the present invention should be considered as enclosing claim defined is as the criterion.
Claims (11)
1. one kind has in the substrate of then filling up of joining with source/drain regions, forms the manufacture method of the fin-shaped groove structure capacitor of dynamic random access memory, it is characterized in that this method comprises:
Formation comprises the alternating oxidation layer of a top oxide layer and a multiple thing of nitride layer, and wherein this each nitride layer is sandwiched between this each oxide layer;
In the multiple thing of this oxide layer that replaces and nitride layer, form the storage node contacts window, this storage node contacts window stops at this and then fills up;
Along the sidewall of this storage node contacts window, divest this nitride layer of part;
Above this top oxide layer, form one first instant doped polysilicon layer, and conformal in the sidewall of this storage node contacts window, and with this then pad contact;
Deposition one photoresist layer above this substrate;
Divest this photoresist layer that is positioned at outside this storage node contacts window;
Divest this first instant doped polysilicon layer of part that is positioned on this top oxide layer;
Divest this photoresist layer;
Above this top oxide layer, form a thin dielectric layer, and conformal this first instant doped polysilicon layer on the sidewall of this storage node contacts window; And
Above this thin dielectric layer with this storage node contacts window in, form one second instant doped polysilicon layer.
2. the method for claim 1 is characterized in that, this each thickness of oxide layer is about between 500 to 1500 dusts.
3. the method for claim 1 is characterized in that, the thickness of this each nitride layer is about between 1500 to 2500 dusts.
4. the method for claim 1 is characterized in that, the size that divests this preceding storage node contacts window of this nitride layer of part is about 0.35 to 0.5 μ m and multiply by 0.2 to 0.4 μ m.
5. the method for claim 1 is characterized in that, the size of this storage node contacts window before divesting this nitride layer of part is about 0.2 to 0.4 μ m and multiply by 0.2 to 0.4 μ m.
6. the method for claim 1 is characterized in that, the thickness of this nitride layer of part that divests is about between 500 to 3000 dusts.
7. the method for claim 1 is characterized in that, the thickness of this first instant doped polysilicon layer is about between 250 to 750 dusts.
8. the method for claim 1 is characterized in that, the material of this thin dielectric layer comprises silicon oxide/silicon nitride/silicon oxide or silicon nitride.
9. the method for claim 1 is characterized in that, the multiple thing of this alternating oxidation layer and nitride layer comprises three layers or multilayer oxide layer and two-layer or nitride multilayer thing layer.
10. the method for claim 1 is characterized in that, along the sidewall of this storage node contacts window, the method that divests this nitride layer of part comprises the use hot phosphoric acid solution.
11. the method for claim 1; it is characterized in that; divesting when being positioned at this photoresist layer outside this storage node contacts window and divesting this first instant doped polysilicon layer of the part that is positioned on this top oxide layer, this photoresist layer that is arranged in this storage node contacts window is arranged in this first instant doped polysilicon layer on the sidewall of this storage node contacts window in order to protection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98124199A CN1106039C (en) | 1998-11-16 | 1998-11-16 | Dynamic random access memory capacitor manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN98124199A CN1106039C (en) | 1998-11-16 | 1998-11-16 | Dynamic random access memory capacitor manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1254184A true CN1254184A (en) | 2000-05-24 |
| CN1106039C CN1106039C (en) | 2003-04-16 |
Family
ID=5228525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98124199A Expired - Lifetime CN1106039C (en) | 1998-11-16 | 1998-11-16 | Dynamic random access memory capacitor manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1106039C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| CN105762118A (en) * | 2014-12-16 | 2016-07-13 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677222A (en) * | 1996-10-11 | 1997-10-14 | Vanguard International Semiconductor Corporation | Method for forming a DRAM capacitor |
| US5766994A (en) * | 1997-04-11 | 1998-06-16 | Vanguard International Semiconductor Corporation | Dynamic random access memory fabrication method having stacked capacitors with increased capacitance |
| US5770499A (en) * | 1997-05-29 | 1998-06-23 | Texas Instruments Incorporated | Planarized capacitor array structure for high density memory applications |
-
1998
- 1998-11-16 CN CN98124199A patent/CN1106039C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100339953C (en) * | 2003-02-24 | 2007-09-26 | 友达光电股份有限公司 | Method for forming contact hole |
| CN105762118A (en) * | 2014-12-16 | 2016-07-13 | 旺宏电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN110246827A (en) * | 2014-12-16 | 2019-09-17 | 旺宏电子股份有限公司 | Semiconductor element and its manufacturing method |
| CN110246827B (en) * | 2014-12-16 | 2021-10-15 | 旺宏电子股份有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1106039C (en) | 2003-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109256382B (en) | Dynamic random access memory and manufacturing method thereof | |
| US5342800A (en) | Method of making memory cell capacitor | |
| CN101207019B (en) | Metal-insulator-metal capacitor and method of forming the same | |
| US5543346A (en) | Method of fabricating a dynamic random access memory stacked capacitor | |
| US8957467B2 (en) | Method of fabricating a semiconductor device | |
| US5874757A (en) | Dual-packed capacitor DRAM cell structure | |
| US6100129A (en) | Method for making fin-trench structured DRAM capacitor | |
| KR970000718B1 (en) | Semiconductor memory device and manufacturing method thereof | |
| US5950084A (en) | Method of manufacturing dual-packed capacitor for DRAM cells | |
| US6303430B1 (en) | Method of manufacturing DRAM capacitor | |
| US6342419B1 (en) | DRAM capacitor and a method of fabricating the same | |
| US20080220575A1 (en) | Method of fabricating dynamic random access memory | |
| JPH1050962A (en) | Manufacture of semiconductor device | |
| WO2021233111A1 (en) | Memory forming method and memory | |
| US7064029B2 (en) | Semiconductor memory device and method of producing the same | |
| JP2001077325A (en) | Method for forming trench exceeding resolution of picture process inside insulation film | |
| EP0652592A2 (en) | Semiconductor memory device and manufacturing method thereof | |
| CN100358089C (en) | Side wall spacing piece structure of self aligning contact and its shaping method | |
| KR930005741B1 (en) | Dram cell having a tunnelled capacitor and method of fabricating therefor | |
| CN1106039C (en) | Dynamic random access memory capacitor manufacture method | |
| US6844233B2 (en) | Semiconductor memory device and fabrication method thereof using damascene gate and epitaxial growth | |
| US7074725B2 (en) | Method for forming a storage node of a capacitor | |
| US4897702A (en) | Semiconductor memory device and manufacturing method for the same | |
| KR100242470B1 (en) | Semiconductor memory device and its fabricating method | |
| US5329146A (en) | DRAM having trench type capacitor extending through field oxide |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20030416 |
|
| CX01 | Expiry of patent term |