CN1253792C

CN1253792C - Control circuit for testing high internal memory address and its control method

Info

Publication number: CN1253792C
Application number: CN 03142558
Authority: CN
Inventors: 朱修明
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2003-06-11
Filing date: 2003-06-11
Publication date: 2006-04-26
Anticipated expiration: 2023-06-11
Also published as: CN1460931A

Abstract

The present invention provides a control circuit for testing a high internal memory address and a control method thereof. A mapping circuit of a hardware is directly arranged in a north-bridge chip, and the switching of the mapping circuit is utilized to perform an internal memory test module under a large real mode so as to test internal memory address space which is more than 4GB.

Description

Test the control circuit and the control method of high memory address

Technical field

The invention relates to a kind of memory control circuit and control method, and particularly relevant for a kind of control circuit and control method thereof with the high memory address function of test.

Background technology

Because the fast development of computing machine science and technology, the operating speed fast lifting of personal computer relatively makes memory size also increase thereupon.And the control chip in the personal computer also must cooperate the increase of memory size and provide pin position, more address (Address Pin) to make that control chip can the bigger memory range of access.

In general, all utilize an internal memory test module (Memory Testing Tool) to carry out the test of internal memory control module on the personal computer.It is that the CPU (central processing unit) (CPU) of utilizing personal computer is carried out internal memory test module, but makes the data in all address spaces of CPU (central processing unit) access memory control module test.This internal memory test module is the standard that industry is assert, that is to say, control chip on the personal computer or internal memory control module all must utilize this internal memory test module to come by test, and also can be widely general industry of test result or manufacturer accept.

Please refer to Fig. 1, its illustrate is the test structure of known personal computer.CPU (central processing unit) 10 is connected to north bridge chips (North Bridge Chip) 20 via Front Side Bus (Front Side Bus) 12, north bridge chips is connected to internal memory control module 30 via a rambus 22, and north bridge chips 20 also is connected to South Bridge chip (South Bridge Chip) 40 via a specific format bus 24, and South Bridge chip 40 can be connected to a hard disk (Hard Disk) 50, and promptly stores internal memory test module in the hard disk 50.And the internal memory test module that utilizes CPU (central processing unit) 10 to carry out in the hard disk 50.CPU (central processing unit) 10 can be sent data to internal memory control module 30 and write the test that internal memory control module 30 is carried out in read command.And the data of read write command and write-read all are responsible for transmission by north bridge chips 20.

Under general traditional personal computer framework, internal memory test module only can (Operation System carries out the test of internal memory under big actual pattern OS) (Big Real Mode) at dos operating system.As everyone knows, illustrate as Fig. 2, CPU (central processing unit) 10 is carried out internal memory test module and only can be addressed to 4GB under the big actual pattern of personal computer, that is to say, the above address space of 4GB has no idea to carry out the access and the test of data.And the address space of 4GB is by 32 address wire (bit0～bit31) form.

Yet, with the operating system of a new generation, Windows 2000 operating systems for example, its addressing space can be greater than 4GB, and relevant testing hardware framework or test procedure lack very much.Therefore, the above internal memory control module of test 4GB can be pretty troublesome.

Summary of the invention

The objective of the invention is to propose a kind of control circuit and control method of testing high memory address, it directly provides the mapping circuit of hardware in north bridge chips, and utilize the switching of mapping circuit, reach and under big actual pattern, carry out internal memory test module and can carry out the test of the above memory address space of 4GB.

The present invention can realize by following measure:

The invention provides a kind of control circuit of testing high memory address, comprising: the internal memory control module, it can be divided into a plurality of memory blocks; CPU (central processing unit) can be carried out an internal memory test module, and sends a plurality of data write commands and a plurality of data read command in order to first memory block in the test memory control module; And, north bridge chips is connected between CPU (central processing unit) and the internal memory control module, in order to reception data write command and data read command, and optionally carry out the data write command in second memory block and by the second memory block response memory reading order.

The control circuit of the high memory address of described test, this north bridge chips comprises a mapping circuit in order to these data write commands and these data read commands are mapped to this second memory block, and this mapping circuit can change the level of the higher pin position, address in these data write commands and these data read commands.

The control circuit of the high memory address of described test, the address of this second memory block is higher than the address of this first memory block.

The control circuit of the high memory address of described test, this second memory block has identical size with this first memory block.

The control circuit of the high memory address of described test, the size of this first memory block and this second memory block is all 4GB.

The control circuit of the high memory address of described test also comprises:

One South Bridge chip, it is coupled to this north bridge chips; And

One hard disk is coupled to this South Bridge chip and stores this internal memory test module.

The present invention proposes a kind of method of testing high memory address, comprises the following steps: at first a plurality of data write commands and a plurality of data read command of the acceptance test first memory test block; And, optionally carry out the data write command in one second memory test block and by the second memory block response memory reading order.

The method of the high memory address of described test, wherein a mapping circuit is in order to mapping to this second memory block with these data write commands and these data read commands, and this mapping circuit can change the level of the higher pin position, address in these data write commands and these data read commands.

The method of the high memory address of described test, the address of this second memory block is higher than the address of this first memory block.

The method of the high memory address of described test, this second memory block has identical size with this first memory block.

The method of the high memory address of described test, the size of this first memory block and this second memory block is all 4GB.

The method of the high memory address of described test, these data write commands and these data read commands are sent by a central processing unit.

The method of the high memory address of described test, this central processing unit are to carry out an internal memory test module.

The invention has the advantages that:

Control circuit and control method with the high memory address function of test of the present invention, it directly provides the mapping circuit of hardware in north bridge chips, and utilize mapping circuit to switch, reach at the following execution internal memory test module of big actual pattern and can carry out the test of the above memory address space of 4GB.

The present invention also will be described in further detail embodiment in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 illustrate is the test structure of known personal computer;

Fig. 2 is the corresponding memory address with respect to Fig. 1;

Fig. 3 illustrate has the control circuit of test memory high address for the present invention;

Fig. 4 is the corresponding memory address with respect to Fig. 3;

Fig. 5 is the inner mapping circuit connection diagram of north bridge chips; And

Fig. 6 is a circuit diagram within the mapping circuit 28.

Wherein, description of reference numerals is as follows:

10 CPU (central processing unit)

12 Front Side Buss

20 north bridge chips

22 rambus

24 specific format buses

28 mapping circuits

30 internal memory control modules

40 South Bridge chips

50 hard disks

26 host interface

The 21DRAM controller

The 27AGP controller

281 multiplexers

Embodiment

Because known internal memory test module only can be carried out the test of the memory address space below the 4GB under big actual pattern.That is to say that CPU (central processing unit) only can change 32 address wire under big actual pattern, that is bit31～bit0.Please refer to Fig. 3, it has control circuit and Fig. 4 corresponding memory address of test memory high address to its illustrate for one embodiment of the invention.Present embodiment is in order to the address between processing rambus 22 and the Front Side Bus 12 and the conversion of data at north bridge chips 20 indoor designs one mapping circuit 28.According to present embodiment, when testing with the internal memory control module 30 of 8GB, mapping circuit 28 can be controlled the 33rd address wire, that is bit32.

At first, set mapping circuit 28 outputs the 33rd address wire and be low level and carry out internal memory test module that therefore, CPU (central processing unit) 10 can be tested between 0～4GB to internal memory control module 30.In when test, CPU (central processing unit) 10 can be carried out data write to the addressing space of 0～4GB of internal memory control module 30, and north bridge chips 20 promptly is responsible for the Data transmission read write command and is write read data to CPU (central processing unit) 10 or internal memory control module 30.

After 0～4GB of internal memory control module 30 test was finished, setting mapping circuit 28 output the 33rd address wires (bit32) were for high level and carry out internal memory test module.Therefore, though the read write command that CPU (central processing unit) 10 is sent at Front Side Bus 12 still is at the addressing space of 0～4GB, yet, because the 33rd of mapping circuit 28 is set at high level, therefore, in fact the memory address on rambus 22 is 4GB～8GB.And when internal memory control module 30 was passed reading of data back, the 33rd bit address line of mapping circuit 28 may command Front Side Buss 12 was a low level.That is to say, CPU (central processing unit) 10 when carrying out secondary internal memory test module, though still CPU (central processing unit) 10 at the addressing space of access 0～4GB.Because the setting of mapping circuit 28, in fact north bridge chips 20 is the addressing spaces at the 4GB～8GB of access memory control module 30.Therefore, the present invention can reach under big actual pattern and utilize the mapping circuit 28 of design in the north bridge chips 20 to finish the test that is higher than the addressing space more than the 4GB.

In like manner, if mapping circuit 28 can be controlled the 33rd, 34 address wire (bit32, bit33), then as long as CPU (central processing unit) 10 is carried out 4 internal memory test modules, and mapping circuit 28 is exported " 00 ", " 01 ", " 10 ", " 11 " in regular turn on the 33rd, 34, then can test the internal memory control module 30 to 16GB.

And the switching time of above-mentioned mapping circuit 28 can utilize setting BIOS manually to control, and perhaps, utilizes timer (not illustrating) to control automatically.That is manually control is that the user changes the output of the mapping circuit 28 in the BIOS and sets after internal memory test module each time is complete, and sets at BIOS and to carry out internal memory test module once more after finishing.And control is to calculate to carry out a required test duration of internal memory test module automatically, and mapping circuit 28 automatically switches to another set of address lines after surpassing the test duration, and carries out internal memory test module once more in regular turn.

In addition, please refer to its illustrate of Fig. 5 and be north bridge chips inside mapping circuit connection diagram.In general, reading order that CPU (central processing unit) 10 is sent and reading of data can be received by host interface (P6IF) 26 after entering north bridge chips 20, can deliver to mapping circuit 28 in regular turn and deal with judgement after receiving.And reading order after treatment and reading of data can be delivered to dram controller (DRAMC) 21 back output north bridge chips 20 further.Certainly, except central processing unit 10, north bridge chips 20 can also receive reading order and the reading of data of being exported by drawing chip (not illustrating).In like manner, can receive by AGP controller (AGPC) 27 after reading order and the reading of data input north bridge chips 20, after receiving, can deliver to mapping circuit 28 in regular turn and deal with judgement.And reading order after treatment and reading of data can be delivered to dram controller (DRAMC) 21 back output north bridge chips 20 further.As for the internal circuit synoptic diagram of mapping circuit 28 then as shown in Figure 6, the 33rd address wire, that is the output of bit32 is the control that is subjected to a control signal H, when control signal H=0, the bit32 signal of 281 original inputs of output of multiplexer, but when control signal H=1, the signal of 281 output levels of multiplexer " 1 ".

Therefore, the present invention proposes control circuit and control method with the high memory address of test, it directly provides the mapping circuit of hardware in north bridge chips, and utilize mapping circuit to switch the high address line, can reach at the following execution internal memory test module of big actual pattern and can carry out the test of the above memory address space of 4GB.

In sum; though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; certainly can be used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that appended claim defines.

Claims

One kind the test high memory address control circuit, comprising:

One internal memory control module, this internal memory control module is divided into a plurality of memory blocks;

One CPU (central processing unit), in order to carrying out a memory test software, it can send a plurality of data write commands and a plurality of data read command in order to one of to test in this internal memory control module first memory block; And

One north bridge chips, be connected between this CPU (central processing unit) and this internal memory control module, in order to receive these data write commands and these data read commands, and optionally carry out those data write commands in this internal memory control module one second memory block and respond these memory read commands by this second memory block, this north bridge chips comprises a mapping circuit, in order to these data write commands and these data read commands are mapped to this second memory block, and this mapping circuit can change the level of the higher pin position, address in these data write commands and these data read commands.
2. the control circuit of the high memory address of test as claimed in claim 1 is characterized in that the address of this second memory block is higher than the address of this first memory block.
3. the control circuit of the high memory address of test as claimed in claim 1 is characterized in that this second memory block has identical size with this first memory block.
4. the control circuit of the high memory address of test as claimed in claim 1 is characterized in that the size of this first memory block and this second memory block is all 4GB.
5. the control circuit of the high memory address of test as claimed in claim 1 is characterized in that also comprising:

One South Bridge chip, it is coupled to this north bridge chips; And

One hard disk is coupled to this South Bridge chip and stores this internal memory test module.
6. the method for the high memory address of test comprises the following steps:

A plurality of data write commands and a plurality of data read command of acceptance test one first memory block;

Optionally change the level of the higher pin position, address in these data write commands and these data read commands, these data write commands and these data read commands are mapped to one second memory block; And

Respond these data read commands by this second memory block.
7. the method for the high memory address of test as claimed in claim 6, it is characterized in that it is performed by a mapping circuit that these data write commands and these data read commands are mapped to this second memory block, and this mapping circuit can change the level of the higher pin position, address in these data write commands and these data read commands.
8. the method for the high memory address of test as claimed in claim 6 is characterized in that the address of this second memory block is higher than the address of this first memory block.
9. the method for the high memory address of test as claimed in claim 6 is characterized in that this second memory block has identical size with this first memory block.
10. the method for the high memory address of test as claimed in claim 6 is characterized in that the size of this first memory block and this second memory block is all 4GB.
11. the method for the high memory address of test as claimed in claim 6 is characterized in that these data write commands and these data read commands are sent by a central processing unit.
12. the method for the high memory address of test as claimed in claim 11 is characterized in that this central processing unit carries out an internal memory test module.