CN1252595C

CN1252595C - Storage-device address decoding method and apparatus thereof conducted in mutual exclusive pit-pattern comparison

Info

Publication number: CN1252595C
Application number: CN 03108516
Authority: CN
Inventors: 刘明熙
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2003-03-28
Filing date: 2003-03-28
Publication date: 2006-04-19
Anticipated expiration: 2023-03-28
Also published as: CN1438578A

Abstract

The present invention provides a method and a relevant device for decoding addresses in a memory device so as to judge which section a given address belongs to in the memory device. Multiple sections are formed in the memory device, and a plurality of memory units are arranged in each section. The method comprises the steps: firstly, different memory units correspond to different binary element addresses according to the number of memory units in each section; moreover, parts of bits in each unit address form a common address; different memory units in the same section have the same common addresses; moreover, common addresses of the memory units in different sections are mutually excluded. When the section to which a given address belongs needs to be judged, common addresses corresponding to all sections are compared with corresponding bits of the given address so as to determine whether the common addresses corresponding to all sections are coincident with the corresponding bits of the given address or not.

Description

The decoded memory address method and the relevant apparatus that relatively carry out with the mutual exclusion bit pattern

Technical field

The present invention relates to a kind of method and relevant apparatus that carries out the preliminary address decoder of storer, particularly a kind of method and relevant apparatus that utilizes the mutual exclusion bit pattern relatively to carry out the preliminary address decoder of storer.

Background technology

In modern society, can fast processing, manage the microprocessor system of various numerical datas, file, data and audio and video information, become the most important basis of information society and one of be equipped with.In general, in order to realize various complexity, diversified function, microprocessor system can be provided with the memory storage (similarly being random access memory) of temporal data, with required program and data during the temporary microprocessor running.Microprocessor reads and carries out program, the data that are temporary in the memory storage, just can control microprocessor system and finish various functions.Therefore, the speed of microprocessor accessing storage devices and efficient have also just influenced the speed and the efficient of microprocessor overall operation.Especially in the modern times, the memory capacity of memory storage is increasing, how to make the microprocessor system memory storage of access high power capacity fast and effeciently, also becomes one of emphasis of present information manufacturer research and development.

Please refer to Fig. 1.Fig. 1 is the function block schematic diagram of a normatron 10.Computing machine 10 wherein is provided with a central processing unit 12, a chipset 14, a memory storage 16, a display card 18, a display 20, a peripheral unit 22 and a ROM-BIOS 24 as a microprocessor system.Central processing unit 12 is used for deal with data, data, with the running of main control computer 10; Memory storage 16 promptly is used for required program, data during temporary central processing unit 12 runnings of the mode of volatibility.Display card 18 is used for handling image signal, is shown as image frame with the situation with computing machine 1O running on display 20; 22 of peripheral units can comprise man-computer interfaces such as keyboard, mouse, be used for Winchester disk drive, the CD player of non-volatile manner storage data, be used for making computing machine 10 to be connected in the networking card at networking or handle adlib of sound signal or the like.The setting that some basic scrutiny programs carried out when 24 of ROM-BIOS (BIOS, basic input/outputsystem) were used for storing computing machine 10 starts and procedure code or the like.And chipset 14 promptly is used for managing the data contact transmission of 24 of central processing unit 12 and memory storage 16, display card 18, peripheral unit 22, ROM-BIOS.Can be provided with north bridge circuit 26A and south bridge circuit 26B in the chipset 14; North bridge circuit 26A is used for managing the data transmission of central processing unit 12 and

memory storage

16,18 higher speeds of display card, and south bridge circuit 26B then is used for managing central processing unit 12 and

peripheral unit

22,24 data transmission than low speed of ROM-BIOS.In order to manage access, also be provided with a control circuit 28 among the north bridge circuit 26A to memory storage 16.

Under the computer architecture in modern times, memory storage 16 is made of jointly several memory modules usually, has just drawn four memory module 30A to 30D in the image pattern 1 as representative.Respectively include a plurality of storage unit 34 among each memory module 30A to 30D, each storage unit 34 is used for writing down the numerical data of (bit); Gathering storage unit 34 all among all memory module 30A to 30D, is exactly the memory capacity that memory storage 16 can provide altogether.Under existing technology, memory module is made into independently circuit mostly, can be connected in computing machine 10 by the slot in the computing machine 10 to form memory storage 16; Different memory modules can have the storage unit (that is to say that each memory module can have different memory capacity) of varying number, and the user can choose the memory module of different capabilities according to need, equipment memory storage 16.Generally speaking, the storage unit in the memory module is distributed in two arrays (rank) storage array; For instance, shown in the image pattern 1, memory module 30A promptly has two storage array 32A in upright arrangement, 32B.Control circuit 28 then can be respectively controlled data access to a storage array in upright arrangement with a controlling signal.Just as shown in fig. 1, controlling signal CSp0, CSp1 promptly distinguish two storage array 32A in upright arrangement, 32B among the corresponding stored module 30A; Controlling signal CSp2 to CSp7 then corresponds respectively to the storage array in upright arrangement of memory module 30B, 30C and 30D.

In general, memory storage 16 can both be supported the function of random access (random access), just can arbitrary access memory storage 16 in data in any one storage unit 34; In order to manage the random access to each storage unit 34 in the memory storage 16, each storage unit 34 in the memory storage 16 can be assigned (assign) to a unique address, as the element address.When central processing unit 12 is wanted the data of a certain particular memory location 34 in the accessing storage devices 16, central processing unit 12 just can be to the address of control circuit 28 these particular memory location 34 of prompting, go out the memory module at these particular memory location 34 actual places by control circuit 28 according to this address decoder, this particular memory location 34 is carried out data access with reality.That is to say, when control circuit 28 receives the given address (similarly be by central processing unit 12 appointments) of a corresponding particular memory location, control circuit 28 will decode the memory module at this place, given address, or even the storage array in upright arrangement at this place, given address, remove to trigger this array storage array with the controlling signal of this array storage array correspondence again, to cooperate the memory module at this particular memory location place, access is to the data (have the address decoding circuitry of oneself usually in each memory module, can further decode the particular memory location of this given address correspondence) of this particular memory location.

About the situation that each memory unit address in the memory storage 16 is assigned, please refer to Fig. 2 (and in the lump with reference to figure 1).Fig. 2 is under the known technology, each storage unit is carried out the synoptic diagram of address assignment in memory storage 16.As shown in Figure 2, suppose that memory module 30A to 30D has 2 respectively ²⁵(two 25 powers), 2 ²⁷, 2 ²⁸And 2 ²⁶Individual storage unit that is to say, the memory capacity of memory module 30A to 30D is respectively 32 megabits, 128 megabits, 256 megabits and 64 megabits.Megabit (Megabit) is here also just represented 2 ²⁰Individual position, just 2 ²⁰The individual storage unit that respectively stores.Behind computer booting, the address that control circuit 28 will increase progressively numerical linear is distributed to each storage unit among the memory module 30A to 30D in regular turn.Certainly, in digital circuit, binary bit is the most basic numeric representation mode, and the corresponding address of each storage unit is also represented with binary bit.For instance, as shown in Figure 2, the corresponding address of each storage unit all represents with 32 positions under the binary bit, with the 0th be least important position, the 31st be most important.After address assignment, first storage unit among the memory module 30A can be designated as address 36A, and its value is two-symbol " 000 ... 0 ", and just all positions are all " 0 ".The corresponding address of ensuing each storage unit will increase progressively in regular turn, and the address that similarly is second storage unit is 36B, and its value is " 00 ... 01 " (only the 0th is " 1 "); And the address of the 3rd storage unit is 36C, and its value continues to increase progressively 1 and become and be " 0 ... 010 " (only the 1st is " 1 ") by address 36B, by that analogy.Arrived penult storage unit among the memory module 30A the (just the 2nd ²⁵+ 1 storage unit), the value of its corresponding address 36D will be incremented to two-symbol " 0 ... 01 ... 10 " (by the 1st to the 24th be " 1 ", surplus is " 0 "); And last storage unit among the memory module 30A the (just the 2nd ²⁵Individual storage unit), its corresponding address 36E also increases progressively 1 and become " 0 ... 01 ... 1 " (the 0th to the 24th is " 1 ", and surplus is " 0 ") again by address 36D.

Control circuit 28 can be considered as an integral body with all storage unit of all memory modules in the memory storage 16 when assigned address; So when control circuit 28 with address assignment during to memory module 30B, the value of its address can be continued to increase progressively by address 36E (address of memory module 30A intermediate value maximum just).As shown in Figure 2, first storage unit can be corresponded to address 38A among the memory module 30B, its value can increase progressively 1 by the value of address 36E, and becomes two-symbol " 0 ... 010 ... 0 " (only the 25th is " 1 "), represents this storage unit can be regarded as the 2nd in the memory storage 16 ²⁵+ 1 storage unit is just by the 2nd of first storage unit of memory module 30A (storage unit of address 36A correspondence) calculation ²⁵+ 1 storage unit.In like manner, second storage unit can be regarded as the 2nd in the memory storage 16 among the memory module 30B ²⁵+ 2 storage unit, its corresponding address 38B can increase progressively 1 by address 38A again, becomes two-symbol " 0 ... 010 ... 01 " (only the 0th and the 25th is " 1 ").Owing to have 2 among the memory module 30B ²⁷Individual storage unit so arrived latter two storage unit among the memory module 30B, just becomes in the memory storage 16 the (2 respectively ²⁵+ 2 ²⁷-1) and the (2 ²⁵+ 2 ²⁷) individual storage unit, its

corresponding address

38C, 38D then are incremented to two-symbol " 0 ... 01001 ... 10 " respectively, and (the 1st to the 24th, the 27th is " 1 ", surplus is " 0 ") and " 0 ... 01001 ... 11 " (the 0th to the 24th, the 27th is " 1 ", and surplus is " 0 ").

Analogize according to above-mentioned principle, arrived memory module 30C (the 3rd memory module just), the corresponding address 42A of its first storage unit (the minimum address of its value among the memory module 30C just) can increase progressively 1 by the value of address 38D, become two-symbol " 0 ... 01010 ... 0 " (only the 25th and the 27th is " 1 "), also representing this storage unit is in the memory storage 16, by the number of memory cells of address 36A come the (2 ²⁵+ 2 ²⁷+ 1) individual storage unit.Arrived the 2nd among the memory module 30C ²⁸ Individual address 42B (the maximum address of its value among the memory module 30C just), its value will be incremented to two-symbol " 0 ... 011001 ... 1 ", and (the the the 0th to the 24th, the 27th, the 28th is " 1 ", Yu Weiwei " 0 "), representing it has been since address 36A increases progressively in regular turn the (2 ²⁵+ 2 ²⁷+ 2 ²⁸) individual address.In like manner, to the 4th memory module 30D, its first storage unit corresponding address 44A promptly continues to increase progressively 1 by address 42B, become two-symbol " 0 ... 011010 ... 0 " (the the 25th, the 27th and the 28th is " 1 "), and the address 44B of last storage unit of memory module 30D also just continues to be incremented to " 0 ... 011101 ... 1 " (the the the 26th to the 28th, the 0th to the 24th is " 1 ", Yu Weiwei " 0 "), since representing it to be address 36A, the (2 ²⁵+ 2 ²⁷+ 2 ²⁸+ 2 ²⁶) individual address.

After address assignment,, just can draw up ending (ending) address at each memory module by first address in each memory module (first storage unit corresponding address just) and last address.As shown in Figure 2, because all addresses of being assigned to are all less than first address 38A among the memory module 30B among the memory module 30A, location, old place 38A can be considered the end addresses 46A of memory module 30A correspondence.In like manner, all less than the address 42A of its value minimum among the memory module 30C, location, old place 42A can be considered the end addresses 46B of memory module 30B correspondence in the address that each storage unit is assigned among the memory module 30B (and memory module 30A).And memory module 30C together with the address that is assigned among memory module 30A, the 30B all less than the end addresses 46C (the lowest address 44A of memory module 30D just) of memory module 30C correspondence.At last, all addresses among the memory module 30D are all less than end addresses 46D.Note that the result that each end addresses 46A to 46D just adds up with each memory module capacity of binary representation.As end addresses 46A representative is two-symbol 2 ²⁵, the memory capacity of memory module 30A (being the quantity of memory module 30A storage unit) just; What end addresses 46B represented is two-symbol (2 ²⁵+ 2 ²⁷), represent the summation of

memory module

30A, 30B memory capacity; What end addresses 46C represented is two-symbol (2 ²⁵+ 2 ²⁷+ 2 ²⁸), the result that adds up of

memory module

30A, 30B and 30C memory capacity just.At last, end addresses 46D representative is two-symbol (2 ²⁵+ 2 ²⁷+ 2 ²⁸+ 2 ²⁶), the result of the memory module that just adds up 30A to 30D memory capacity.

By foregoing description as can be known, even each storage unit in the memory storage 16 may adhere to different memory modules separately, control circuit 28 still can be considered as each storage unit one integral body, to each storage unit, the storage unit that makes things convenient for other circuit in the computing machine 10 that each memory module is provided is considered as an integral body to carry out access with the address assignment that increases progressively continuously.But, as previously mentioned, when central processing unit 12 (or other circuit) will be with the data of given address access one a corresponding storage unit, control circuit 28 will carry out preliminary address decoder, determine the memory module (or even the storage array in upright arrangement at storage unit place) at this storage unit place earlier, could in follow-up process, further actual access arrive this storage unit.

Please continue with reference to figure 3 (and Fig. 1,2).Fig. 3 is in the known technology, and control circuit 28 carries out the function block schematic diagram of preliminary address decoder function.In control circuit 28, be provided with an access module 51, a plurality of subtraction block 48A to 48D and a logic module 50.Access module 51 is used for keeping in the given address 54 that central processing unit 12 (or other circuit) reaches control circuit 28; And control circuit 28 promptly can carry out preliminary address decoder to this given address.In known technology, when control circuit 28 will carry out preliminary address decoder and judge which memory module a given address 54 belong to, control circuit 28 available software or hardware mode realized out the function of subtraction block 48A to 48D and logic module 50.Subtraction block 48A to 48D is used for respectively (please in the lump with reference to figure 2) subtracted each other with end addresses 46A to 46D in given address 54, to subtract the positive and negative relative size of telling given address and each end addresses 46A to 46D of operation result.The result that subtracter draws can further be integrated by logic module 50, with the actual memory module of judging under the given address 54, and produces corresponding decoded result, similarly is to represent memory module under the given address 54 with indicating signal HPA to HPD.For instance, if given address 54 belongs to memory module 30A, given address 54 will be less than each end addresses 46A to 46D.If given address 54 belongs to memory module 30B, given address 54 will be less than end addresses 46B to 46D, but is not less than end addresses 46A.In like manner, when the storage unit of given address 54 correspondences belonged to memory module 30D, 54 meetings in given address were less than end addresses 46D, but were not less than end addresses 46A to 46C.Similarly be in Fig. 3, to draw, if given address 54 is " 0 ... 010010 ... 0 " (only the 25th, the 28th is " 1 "), then it is not less than

end addresses

46A, 46B but less than

end addresses

46C, 46D, logic module 50 just can judge that this given address 54 is corresponding to the storage unit among the memory module 30C thus.And logic module 50 just can make the voltage rising of indicating signal HPC be the high level of representative numeral " 1 " (or logic " very "), belongs to memory module 30C to represent given address 54; The voltage of other indicating signals HPA, HPB and HPD then is the low level of representative " 0 " (or logic " puppet "), does not belong to

memory module

30A, 30B and 30D to represent given address 54 respectively.

Sum up the running of control circuit 28, after computing machine 10 starts, control circuit 28 can scan the memory capacity size of each memory module in the memory storage 16, and each storage unit is carried out address assignment, and this moment, control circuit 28 also can calculate the required end addresses of preliminary address decoder.By the time it is follow-up when the storage unit that other circuit want certain given address of access is arranged, control circuit 28 just can be according to end addresses, utilize its subtraction block, logic module to carry out preliminary address decoder, obtain the affiliated memory module in this given address, and in follow-up process, cooperating memory module under this given address, actual access is to the storage unit of this given address correspondence.

But, no matter the known technology among Fig. 3 is to realize subtraction block with hardware circuit, or realize the function of subtraction block, the neither height of its efficiency of operating with the microcontroller software program for execution of north bridge circuit 26A.Embodiment with hardware circuit, realize subtraction block and two binary digits are subtracted each other, a number wherein can be got complement (similarly be 1 complement, or 2 complement), form the negative of this number, the negative that will count with two-symbol totalizer is counted addition with another again.Because two-symbol totalizer with two binary digit additions the time, be counted least important position (LSB, just the 0th) by two and begin, and carry out the addition of bit-by-bit, carry could be finished two additions of counting in ground, a position gradually to next bit again.For instance, there are two binary digit A1, A2 to be respectively " 101 " and " 011 "; Want addition and draw one and (sum) during S when two numbers, earlier the 0th additions from two numbers, drawing " 0 " by " 1 "+" 1 " becomes with S the 0th, and wants carry " 1 " to next.After obtaining carry, next just can carry out the calculating of two several the 1st additions,, add by two several the 0th additions " 1 " of carry by the 1st " 1 " of the 1st " 0 " the addend A2 that counts A1, so draw with first of S be " 0 ", carry " 1 " is to time one again.After obtaining the carry of two several first addition, just can proceed the addition of the 2nd of number A1, A2, the 2nd " 0 " by the 2nd " 1 " the addend A2 that counts A1, add " 1 " come by two several the 1st carries, draw with the 2nd of S be " 0 ", carry " 1 ", draw at last with S for " 1000 ".

By foregoing description as can be known, because when carrying out the addition of binary digit, not only addition is wanted in the corresponding position of two numbers, also will wait for last position carry and the result that comes, just can draw the correct operation result that adds; And two numbers add the required time of computing, are exactly that each corresponding position adds computing accumulative total required time sum respectively.That is to say that the position of binary digit is many more in the addition, the required time of additive operation also will be tired out and increased.And the above-mentioned characteristic that consumes operation time that adds can directly be reflected in the known preliminary address decoder technology; When the known technology among Fig. 3 will with subtraction block carry out subtract the magnitude relationship of the more given respectively address of computing 54 and each end addresses 46A to 46D the time, will consume the suitable time is subtracting in the computing, and it is low to cause known control circuit 28 to carry out the efficient of preliminary address decoder, can't decode the memory module under the given address apace.In case the efficient of address decoder is low, central processing unit 12 (see figure 1)s just can not be fast the storage resources of accessing storage devices 16 efficiently, whole computing machine 10 efficiency of operating also can't effectively be promoted.

Summary of the invention

Therefore, fundamental purpose of the present invention is to provide a kind of address decoder method and relevant apparatus that directly relatively carries out with the mutual exclusion bit pattern, can carry out the preliminary address decoder of given address fast efficiently, overcomes the shortcoming of known technology.

In order to realize above-mentioned and other purposes of the present invention, a kind of method of decoded memory address is provided, to judge whether a given address belongs to one of a plurality of sections of this storer, each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, this method includes: make the corresponding address with the many sections of number of memory cells, less than the corresponding address of the few section of number of memory cells; By these corresponding address, each section is obtained a bit pattern respectively; And relatively whether at least one relatively position of this given address conforms to arbitrary bit pattern, if these compare this bit pattern that the position does not meet arbitrary section, then this given address of expression does not fall within this section, otherwise then this given address of expression falls within this section.

In order to realize above-mentioned and other purposes of the present invention, a kind of method of decoded memory address also is provided, to judge whether a given address belongs to one of a plurality of sections of this storer, each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, this method includes: carry out the big minispread of number of memory cells of these sections, make the corresponding address of the many sections of number of memory cells, corresponding address less than the section of storage unit small number, if when the number of memory cells size of at least one first section equaled the number of memory cells size of at least one second section after arranging, then the order of this first section and this second section can be exchanged; By these corresponding address, each section is obtained a bit pattern respectively; And relatively whether at least one relatively position of this given address conforms to arbitrary bit pattern, if these compare this bit pattern that the position does not meet arbitrary section, then this given address of expression does not fall within this section, otherwise then this given address of expression falls within this section.

In order to realize above-mentioned and other purposes of the present invention, a kind of control circuit of decoded memory address also is provided, to judge whether a given address falls within one of a plurality of sections of this storer, each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, this control circuit includes: an access module receives this given address; One order module, make the corresponding address of the many sections of number of memory cells, corresponding address less than the section of storage unit small number, if when the number of memory cells size of at least one first section equaled the number of memory cells size of at least one second section, then the order of this first section and this second section can be exchanged; One comparison module by these corresponding address, is obtained a bit pattern respectively to each section, with at least one relatively position that receives this given address compare whether conform to after, send a plurality of comparison signals; And a logic module, receive these comparison signals, send a decoded result, to judge that this given address falls within one of these sections.

In known technology, when carrying out preliminary address decoder and when judging that this given address belongs to which memory module (or which storage array in upright arrangement) to a given address, be to come the relatively magnitude relationship between this given address and every end addresses of establishing with the result who subtracts computing (just adding computing in the equivalence), belong to which memory module to judge this given address, finish preliminary address decoder.Yet, will be owing to add computing with the method for accumulative carry by turn, successively carry out in order position, a position, just can draw the correct operation result that adds.Therefore, to subtract the preliminary address decoder mode that computing is a comparison basis, the speed and the efficient of its running are lower in the known technology, cause computing machine can not be fast access storage resources efficiently.

In the present invention, then be to carry out preliminary address decoder in the mode of mutual exclusion bit pattern comparison.Ordering techniques via the present invention discloses just can make different storage unit corresponding to different addresses according to the size of each memory module memory capacity, and makes each address that belongs in each memory module have specific mutual exclusion bit pattern.In other words, in belonging to all addresses of same memory module, must there be certain several specific position to be fixing value, form the common common address in each address in this memory module, the common address of different memory module correspondences then is mutual exclusion (that is to say at least one position to be arranged for different in the common address of two different memory modules).Whether more given address meets the common address (just whether specific position meets fixing preset value in this given address) of each memory module, just can judge that given address belongs to that memory module, decodes the affiliated memory module in given address.Since pattern relatively be directly more given address with jointly between the address corresponding value whether conform to, do not need to tire out calculation, carry at different interdigits as adding in the computing, so technology of the present invention can be finished preliminary address decoder fast efficiently, promote the speed and the efficient of computer access storage device resources, and then improve the operational effectiveness of computing machine integral body.

Description of drawings

Fig. 1 is the function block schematic diagram of a normatron.

Fig. 2 is the synoptic diagram that computing machine is assigned each memory unit address in the memory storage among Fig. 1.

Fig. 3 carries out the function block schematic diagram of preliminary address decoder with a known method for computing machine among Fig. 1.

Fig. 4 is the function block schematic diagram of computing machine among the present invention.

Fig. 5 carries out the synoptic diagram of address assignment to each storage unit among Fig. 4 for the present invention.

Fig. 6 is the function block schematic diagram of control circuit among Fig. 4.

Fig. 7 is the function block schematic diagram of comparing unit among Fig. 6.

Fig. 8 A, 8B carry out the synoptic diagram of address assignment down with different sortords in another kind of memory module configuration for the present invention.

Fig. 9 A to 9D carries out the synoptic diagram of address assignment down with different sortords in the third memory module configuration for the present invention.

Graphic symbol description

10,60 computing machines

12,62 central processing units

14,64 chipsets

16,66 memory storages

18,68 display cards

20,70 displays

22,72 peripheral units

24,74 ROM-BIOS

26A, 76A north bridge circuit

26B, 76B south bridge circuit

28,78 control circuits

30A-30D, 80A-80D memory module

32A-32B, 82A-82B storage array in upright arrangement

34,84 storage unit

36A-36E、38A-38D、42A-42B、44A-44B、86A-86D、88A-88C、90A-90C、

92A-92C、132A-132E、136A-136F、151A-151B、152A-152B、153A-153B、

The 154A-154B address

The 46A-46D end addresses

The 48A-48D subtraction block

50,100 logic modules

51,101 access modules

96A-96D、134A-134D、138A-138D、161A-161D、162A-162D、163A-163D、

The 164A-164D bit pattern

The 98A-98D normal address

The 99A-99D shade

111 comparison modules

The 112A-112D comparing unit

116 order module

118A-118H, 122 AND gates

The 120A-120H biconditional gate

CSp0-CSp7, CS0-CS7 controlling signal

The HPA-HPD indicating signal

119 decoded results

Embodiment

Please refer to Fig. 4.Fig. 4 is the function block schematic diagram of the computing machine 60 among the present invention.Computing machine 60 is as a microprocessor system, and it is provided with a central processing unit 62, a chipset 64, a memory storage 66, a display card 68, a display 70, a peripheral unit 72 and ROM-BIOS 74.Central processing unit 62 is used for the operation of main control computer 60, and memory storage 66 is used for program required during temporary central processing unit 62 runnings of the mode of volatibility and data, data; Display card 68 is used for handling image signal, and the situation of computing machine 60 runnings can be shown on the display 70 with graphic picture.Peripheral unit 72 can comprise allow the user import to control instruction keyboard, mouse, be used for Winchester disk drive, CD player with non-volatile mode storage data, be used for handling the adlib of sound signal or be used for networking card that computing machine 60 is connected in the networking or the like.Carry out initialized setting value and relative program after then having stored computing machine 60 starts in the ROM-BIOS 74.And chipset 64 is used for managing the contact transmission of display card 68, memory storage 66, peripheral unit 72, ROM-BIOS 74 and 62 data of central processing unit.Can be provided with a north bridge circuit 76A, south bridge circuit 76B in the chipset 64; North bridge circuit 76A is used for the data transmission of master control memory storage 66, display card 68 and 62 higher speeds of central processing unit, and south bridge circuit 76B is used for master control peripheral unit 72, ROM-BIOS 74 and 62 data transmission than low speed of central processing unit.In the present invention, memory storage 66 can be continued to use typical configuration, is combined into the total memory capacity of memory storage 66 with a plurality of memory modules (drawing four memory module 80A to 80D among Fig. 4 as representative).Be respectively equipped with a plurality of storage unit 84 among each memory module 80A to 80D, each storage unit 84 is used for keeping in the data of 1 unit (similarly being); All storage unit of gathering each memory module just constitute the total memory capacity of memory storage 66.Just as typical configuration, a plurality of storage unit of each memory module also can be distributed in two storage arrays in upright arrangement (rank); With memory module 80A is example, and each storage unit among the memory module 80A just is divided into two storage array 82A in upright arrangement, 82B.For each circuit in the control computer 60 to the access of memory storage 66, be provided with a control circuit 78 among the north bridge circuit 76A, and control the access of different storage arrays in upright arrangement among each memory module 80A to 80D with controlling signal CS0 to CS7 respectively.Just as the practice under the existing technology, control circuit 78 also can be assigned to different addresses (element address just) respectively each storage unit 84 in the memory storage 66, so that memory storage 66 is carried out random access; Certainly, when central processing unit 62 (or other circuit) is wanted the storage unit of access one given address, control circuit 78 will carry out preliminary address decoder, calculating this corresponding stored unit, given address is to belong to which memory module (or further, belong to which storage array in upright arrangement), and then trigger this array storage array, the data of actual this storage unit of access with the controlling signal of correspondence.

Please refer to Fig. 5 (and in the lump with reference to figure 4).Fig. 5 is the present invention's synoptic diagram that the address distributes in each memory module when carrying out address assignment.For convenience and the known technology among Fig. 2 make comparisons, suppose also among Fig. 5 that the memory module 80A to 80D among the present invention has the memory capacity of 3,200 ten thousand, 12,800 ten thousand, 25,600 ten thousand and 64 megabits respectively, just has 2 respectively ²⁵, 2 ²⁷, 2 ²⁸And 2 ²⁶Individual storage unit; And the present invention also can be with 32 binary bit address assignment of linear increment to each storage unit.But, meeting of the present invention according to the capacity in each memory module what, carry out address assignment.Cardinal rule of the present invention is, the memory module that memory capacity is big more, and the address that it was assigned is just more little.So,, when carrying out address assignment, can assign the address that increases progressively by

memory module

80C, 80B, 80D and 80A in regular turn according to the descending order of memory capacity with technology of the present invention just as shown among Fig. 5.In other words, the memory module 80A of memory capacity minimum, the value maximum of the address that it was assigned to, the address value of memory module 80D occupies inferior, the address value that memory module 80B is assigned to is again less than each address value among the memory module 80D, and the memory module 80C of memory capacity maximum, the address value that it was assigned to is minimum on the contrary.As shown in Figure 5, first storage unit among the memory module 80C can be assigned to address 86A, its value is two-symbol " 0 ... 0 " (everybody is " 0 "), other address is then increased progressively by address 86A among the memory module 80C, similarly is that address 86B increases progressively 1 and become " 0 ... 01 " (only the 0th is " 1 ") by address 86A.After the address assignment that will increase progressively was in regular turn given 25,600 ten thousand storage unit of memory module 80C, its address 86C, 86D that latter two storage unit was assigned to also just was incremented to two-symbol " 00001 ... 10 " (the 1st to the 27th be " 1 ") respectively and reaches " 00001 ... 1 " (the 0th to the 27th is " 1 ").

When the present invention carries out address assignment, also the storage unit of each memory module can be considered as an integral body, so concerning memory capacity is only second to the memory module 80B of memory module 80C, first address 88A that it was assigned to (address of memory module 80B intermediate value minimum just), its value also is to increase progressively 1 and become two-symbol " 00010 ... 0 " (only the 28th is " 1 ") by address 86D; Other addresses among the memory module 80B then are by address 86D continuous increasing.Similarly be that second address 88B is exactly to increase progressively 1 and become " 00010 ... 01 " (only the 0th, the 28th is " 1 ") by address 88A.Arrived among the memory module 80B the maximum address 88C of its value, just be incremented to two-symbol " 000101 ... 1 " (the the 0th to the 26th, the 28th is " 1 "), representing address 88C has been since the 86A of address, individual address, the 38,400 ten thousand (25,600 ten thousand+12,800 ten thousand).In like manner, concerning memory capacity again less than the memory module 80D of memory module 80B, first address 90A that it was assigned to increases progressively 1 by the address 88C among the memory module 80B, and becomes two-symbol " 000110 ... 0 " (the 27th, the 28th is " 1 ").Other addresses among the memory module 80D are then increased progressively by address 90A, similarly are that address 90B is exactly to increase progressively 1 and become two-symbol " 000110 ... 01 " (the the 0th, the 27th, the 28th is " 1 ") by address 90A.Arrived last address 90C among the memory module 80D (address of maximum among the memory module 80D just), will be incremented to two-symbol " 0001101 ... 1 " (the the the 0th to the 25th, the 27th, the 28th is " 1 "), represent address 90C to calculate 1,000,000 addresses of the 448th (256+128+64) from address 86A.

According to spirit of the present invention, arrived the memory module 80A of memory capacity minimum, the address that it was assigned to is maximum.First address 92A among the memory module 80A, its value increases progressively 1 by the address 90C among the memory module 80D exactly, and become two-symbol " 0001110 ... 0 " (the 26th to the 28th is " 1 "), other address is then increased progressively by address 92A among the memory module 80A, similarly is that address 92B is exactly to increase progressively 1 and become two-symbol " 0001110 ... 01 " (the the 0th, the 26th to the 28th is " 1 ") by address 92A.Arrived last the address 92C (Zui Da address just) among the memory module 80A, its value also just is incremented to two-symbol " 00011101 ... 1 " (the the the 0th to the 24th, the 26th to the 28th is " 1 "), since representing it to be address 86A, the 48,000 ten thousand address.

As seen from the above description, after the present invention carried out address assignment according to memory capacity ordering, in the more memory module of storage unit, the address that its storage unit is assigned to also can be smaller.And after through the address assignment after the above-mentioned ordering of the present invention, the address in each memory module also can have specific bit pattern.As shown in Figure 5, concerning each address (similarly being address 86A to 86D) that belongs to memory module 80C, though the 0th to the 27th meeting of each address changes between " 0 " and " 1 ", the 28th to the 31st all can be maintained " 0 " in each address.In other words, each address in memory module 80C, in 32 positions of each address, just formed a common address in the 28th to the 31st equivalence, the 0th to the 27th then can be considered an individual address.The different addresses in memory module 80C, its individual address all is different, but common address then is identical.And this also just guides out the bit pattern 96A corresponding to memory module 80C.In bit pattern 96A, represent each address in memory module 80C with " x " mark sign for the 0th to the 27th, its 0th to the 27th may be respectively " 0 " or " 1 ", and its value is fixing, and different addresses has different values; And these also just form the individual address of inequality.Relatively, in bit pattern 96A, the 28th to the 31st fixed value that " 0 " is then arranged represented each address among the memory module 80C, and its 28th to the 31st must be " 0 "; Even the different addresses in memory module 80C, its 28th to the 31st all is fixed as " 0 ", and this common address of each address among the memory module 80C just.Generally speaking, in memory module 80C, each address can have the form of bit pattern 96A, though the 0th to the 27th meeting changes in different addresses, the 28th to the 31st all is fixed as " 0 ".

In like manner, observe the address (similarly being address 88A to 88C) that is dispensed to memory module 80B among Fig. 5 and can find out that the 31st to the 27th fixedly is all " 00010 " in each address, only the 0th to the 26th meeting changes with the address is different.And this has also just formed the bit pattern 96B corresponding to memory module 80B.In bit pattern 96B, the 0th to the 26th meeting forms individual address with different change the in address, but the 31st to the 27th has fixed value " 00010 " and become the common address of each address among the memory module 80C; In other words, each address among the memory module 80C all can meet bit pattern 96B, be fixed as " 00010 " at the 31st to the 27th, and the 0th to the 26th of bit pattern 96B indicates with " x " mark, representative each address in memory module 80B, its 0th to the 26th may be respectively " 0 " or " 1 ".

And as shown in Figure 5, each address among the memory module 80D (similarly being address 90A to 90C) can meet bit pattern 96C, its the 31st to the 26th has fixed value " 000110 ", and representative is in being assigned to 6,400 ten thousand addresses of memory module 80D, and its 31st to the 26th all is fixed as " 000110 ".By that analogy, 3,200 ten thousand addresses in memory module 80A all meet bit pattern 96D, and its 31st to the 25th is fixed as " 0001110 ".

In sum, the present invention can obtain corresponding bit pattern at the situation that address in each memory module distributes, just as in the example of Fig. 5, memory module 80A to 80D can have corresponding bit pattern 96D, 96B, 96A and 96C respectively, and each bit pattern is just represented the characteristic that different address had jointly in each memory module.And when the present invention will carry out preliminary address decoder and judge memory module under the given address, just relatively whether this given address met bit pattern 96A to 96D, to judge the memory module under the given address.For instance, meet bit pattern 96A, just represent given address to belong to memory module 80C if the 28th to the 31st of given address is all " 0 ".In like manner, if the 31st to the 25th of given address is " 0001110 ", just represent given address to belong to memory module 80A.Note that come assigned address through ordering of the present invention according to the amount of capacity of each memory module after, the bit pattern of each memory module correspondence also is mutual exclusion, that is to say, if given address character unification bit pattern, just must not meet other bit pattern.As shown in Figure 5, be " 0000 " if there is a given address to meet bit pattern 96A at the 31st to the 28th, then this given address must not meet bit pattern 96B to 96D, because the 28th of bit pattern 96B to 96D is " 1 ".In like manner, be " 00010 " if given address meets bit pattern 96B at the 31st to the 27th, then this given address must not meet bit pattern 96A and 96C, 96D.This is that the 27th of bit pattern 96C, 96D then is " 1 " because the 28th of bit pattern 96A is " 0 ".Similarly, the given address that meets bit pattern 96D must not meet bit pattern 96A to 96C because among the bit pattern 96A the 28th be " 0 ", and the 28th of bit pattern 96D is " 1 "; Among the bit pattern 96B the 27th is that " 0 " and bit pattern 96D the 27th is " 1 "; And among the bit pattern 96C the 26th is " 0 ", and the 26th of bit pattern 96D then is " 1 ".

The character of above-mentioned this bit pattern mutual exclusion is exactly because the present invention comes the cause of assigned address according to the memory capacity size of each memory module in fact.At first, can be found out do not have the position (just with " x " marked) of fixed value in each bit pattern by each bit pattern of corresponding each memory module, the memory capacity of its number and corresponding stored module has direct relation.Because address sequence when being incremented to maximum address by the lowest address in the same memory module, must have a certain number of position changing in each address, just can make different storage unit corresponding to different addresses.Similarly be the memory module 80C in Fig. 5, it always has 25,600 ten thousand (2 ²⁸) individual storage unit, so among its corresponding bit pattern 96A, the 0th to the 27th will change, and just can be combined into (2 ²⁸) plant different addresses.In like manner, in the memory module 80A of memory capacity minimum, because memory module 80A has only 3,200 ten thousand (2 ²⁵) memory capacity of position, so in its corresponding bit pattern 96D, as long as the 0th to the 24th change, just can be combined into 225 different addresses, distribute to the different storage unit among the memory module 80A.Above-mentioned characteristic is added in the bit pattern and is increased progressively and " 1 " of carry, promptly can be used to make different bit pattern mutual exclusions.For instance, between address pattern 96A, 96B, the characteristic of both mutual exclusions comes from the difference of the 28th value, but " 1 " that is positioned at the 28th among the address pattern 96B is (the asking compare address 86D, 88A) of being come by the 27th carry of address 86D in fact, the 28th " 1 " has just represented the memory capacity of memory module 80C in fact among the pattern 96B of location, old place, and each address among the memory module 80C, can carry to the 28, so the bit pattern 96A of memory module 80C correspondence, its 28th just is fixed as " 0 ".On the other hand, because the memory capacity of memory module 80B is less than the memory capacity of memory module 80C, so corresponding bit pattern 96B is as long as can be combined into different addresses among the memory module 80B the 0th to the 26th change, so " 1 " that is positioned at the 28th among the bit pattern 96B will be fixed up and can not change, and becomes the common address of each address among the memory module 80B; And therefore the alternative between bit pattern 96A, 96B is also just set up.In like manner, in bit pattern 96C, " 1 " in its 27th is to be increased progressively carry and got by the address 88C among the bit pattern 96B, and each address among the memory module 80B can carry to the 27; And the memory module 80D of bit pattern 96C correspondence only has the memory capacity of 64 megabits, thus only need the 0th to the change of the 25th interdigit, can be combined into 6,400 ten thousand addresses.Therefore, bit pattern 96C is arranged in the 27th " 1 ", also just allows bit pattern 96C and bit pattern 96B mutual exclusion.By that analogy, increase progressively and " 1 " of carry by address 90C at the 26th among the bit pattern 96D, also just can allow bit pattern 96D and bit pattern 96C mutual exclusion.

The mutual exclusion bit pattern that utilizes the present invention to obtain, just can via bit pattern determine memory module under the given address more uniquely because meet the given address of a bit pattern, must not meet the bit pattern of other memory module correspondences.If the sequencer procedure that discloses via the invention described above does not just carry out address assignment, though the address in each memory module has common address, but the common address between different memory module then can not be mutual exclusion.For instance, also can be summarized in fact by the address assignment situation among Fig. 2: in Fig. 2, each address of memory module 30A is fixed as " 0 " at the 25th to the 31st, and each address also is fixed as " 0 " at the 28th to the 31st among the memory module 30B.Even but the 28th to the 31st of a given address this given address still might be to belong to memory module 30A for " 0 " meets the common address of memory module 30B, but not memory module 30B.

Application during actual for convenience enforcement is by deriving corresponding normal address and shade in each bit pattern.Similarly be the normal address 98A to 98D that lists among Fig. 5, just correspond respectively to bit pattern 96A to 96D; Cooperate the application of each normal address 98A to 98D, each normal address 98A to 98D also has the shade 99A to 99D of a correspondence respectively.In each shade, its value is used for representing the position that does not have fixed value in the bit pattern for the position of " 0 ", just the position that indicates with mark " x " in the bit pattern; Relatively, its value then is used for representing the position that has fixed value in the corresponding bit pattern for the position of " 1 ".As for its value of position that has fixed value in the address pattern why, then be recorded among corresponding of the normal address corresponding with each shade.For instance, similarly be in shade 99B corresponding to bit pattern 96B, its 0th to the 26th is all " 0 ", and representing the 0th to the 26th in bit pattern 96B is not have fixed value; And among the shade 99B the 27th to the 31st " 1 ", then represent the 27th among the bit pattern 96B to have fixed value to the 31st.As among the bit pattern 96B the 27th to the 31st value respectively why, then be recorded among the 27th to the 31st of corresponding normal address 98B.In other words, the 27th to the 31st of normal address 98B and bit pattern 96B equates respectively, and other positions of normal address 98B then can be arbitrary value (similarly be in Fig. 5, " 0 " are not all inserted corresponding to the position of shade meta " 1 " in each normal address).Lift an example again, bit pattern 96D has corresponding shade 99D and normal address 98D; Because the 31st to the 25th in shade 99D is " 1 ", represent the 31st to the 25th of bit pattern 96D to be fixed value, its value is exactly the 31st to the 25th " 0001110 " among the 98D of normal address.As previously mentioned, because in the bit pattern of each memory module correspondence, the position number that does not have fixed value is relevant with the memory capacity of corresponding stored module, and the shade of corresponding each memory module also just can produce with the memory capacity of memory module.For instance, memory module 80C has 25,600 ten thousand memory capacity, and the value of its memory capacity represents to be " 00010 ... 0 " (only the 28th is " 1 ") with 32 binary digit.Become two-symbol " 00001 ... 1 " (the 0th to the 27th is " 1 ") after storage capacity value subtracted 1, again will everybody anti-phase becoming " 11110 ... 0 " (the 28th to the 31st is " 1 "), also just drawn the shade 99A of memory module 80C.

Please refer to Fig. 6 (in the lump with reference to figure 5).Fig. 6 is the function block schematic diagram that is used for realizing preliminary address decoder function in the control circuit 78 of the present invention.Be provided with an access module 101, an order module 116, a comparison module 111 and a logic module 100 in the control circuit 78.Be provided with four each comparing unit 112A to 112D in the comparison module 111 corresponding to a memory module.Wherein access module 101 is used for keeping in the given address 104 that central processing unit 62 (or other circuit) transmits, and each comparing unit 112A to 112D in the comparison module 111 is used for respectively checking whether given address 104 meets the bit pattern of each memory module correspondence; According to the comparative result of each comparing unit 112A to 112D, logic module 100 just can provide a decoded result 119, is used for reflecting whether given address 104 belongs to memory module 80A to 80D.The situation of control circuit 78 runnings can be described below.When computing machine 60 starts, control circuit 78 will scan each memory module 80A to 80D in the memory storage 66, to judge the memory capacity of each memory module.Next order module 116 just can be according to principle of ordering of the present invention (that is Fig. 5 and relevant discussion address), according to the memory capacity of each memory module, and the order of decision address assignment; And control circuit 78 just can be according to the order of order module 116 decision, makes storage unit in each memory module corresponding to an address.Simultaneously order module 116 also can be according to the result of ordering, address assignment, determines the corresponding bit pattern of each memory module (and shade, normal address), and sets each comparing unit 112A to 112D and logic module 100 according to this.So, in the process of follow-up running, when central processing unit 62 (or other circuit) is wanted in the accessing storage devices 66 a certain storage unit, just can with the address of this storage unit temporary to access module 101 as given address 104, and control circuit 78 will carry out preliminary address decoder to given address 104, by each comparing unit 112A to 112D in the comparison module 111 bit pattern of given address 104 and each memory module correspondence is compared, look at that given address 104 meets that bit pattern; And logic module 100 just can provide decoded result 119 according to each comparing unit 112A to 112D result relatively, reflects the result of preliminary address decoder.

For the process that practical illustration control circuit 78 preliminary address decoders more carry out, Fig. 6 has also continued to use the example among Fig. 5, so comparing unit 112A to 112D is used for more given address 104 respectively and whether meets bit pattern 96A to 96D; Because after ordering, bit pattern 96A to 96D corresponds respectively to memory module 80C, 80B, 80D and 80A (please in the lump with reference to figure 5), so logic module 100 promptly is used for the comparative result with comparison module 112A to 112D, and judge whether given address 104 belongs among the memory module 80A to 80D.In Fig. 6, also reality has supposed that given address 104 is " 000110 ... 01 " (the the 0th, the 27th and the 28th is " 1 ").After each comparing unit running, can find that this given address 104 meets bit pattern 96C, its the 31st to the 26th is " 000110 ", so the result of comparing unit 112C exportable " very " (similarly being the voltage with high level) reflects that given address 104 belongs to memory module 80D.Relatively, for instance, the given address 104 of example can not meet bit pattern 96D among Fig. 6, because of its 31st to the 25th be " 0001100 ", the 31st to the 25th of bit pattern 96D then is " 0001110 "; So comparing unit 112D can export result's (similarly being low level voltage) of " puppet ", represents given address 104 not belong to memory module 80A.In fact, the given address 104 of the example among Fig. 6 promptly is the address 90B that belongs to memory module 80D among Fig. 5.

Please refer to Fig. 7, Fig. 7 is to be example with the comparing unit 112B among Fig. 6, shows the synoptic diagram of comparing unit function square among the present invention; Whether the function of comparing unit 112B promptly is to be used for more given address 104 to conform to bit pattern 96B.As once describing among Fig. 5, can derive corresponding normal address and shade by each bit pattern, and when reality realizes comparing unit 112B, just can utilize the shade 99B and the normal address 98B of bit pattern 96B correspondence.As shown in Figure 7, in comparing unit 112B, can be provided with a plurality of AND gates and biconditional gate.Each AND gate is used for respectively AND operation is done in the position of position of given address 104 and shade 99B, similarly be AND gate 118A to 118G be exactly be used for the 31st to 25 of given address 104 respectively with shade 99B in the 31st to the 25th do AND operation.Biconditional gate then be used for the result of each AND gate computing further with the normal address in a position make exclusive NOR, similarly be that biconditional gate 120A to 120G among Fig. 7 promptly is used for respectively making exclusive NOR with the 31st to the 25th among the output result of AND gate 118A to 118G and the normal address 98B.The result of each biconditional gate output can do AND operation via an AND gate 122 again, by the comparative result of AND gate 122 output comparator 112B.When each AND gate is done AND operation with the position of shade each and given address 104, just can be with " the covering " that need not compare in the given address 104, and will need the value of the address of comparison to transfer to biconditional gate; And result that biconditional gate transmits each AND gate and each in the normal address are made exclusive NOR, be exactly in more given address 104, need relatively its value of position whether with the normal address in the value of corresponding position equal; 122 outputs of integrating each biconditional gate of AND gate.With regard to the example among Fig. 7, among the shade 99B the 27th to the 31st be " 1 ", represent its corresponding bit pattern 96B fixed value to be arranged, and comparing unit 112B will check whether the 27th to the 31st equal the 27th among the 98B of normal address respectively to the 31st in the given address 104 at the 27th to the 31st.In " 1 " of shade 99B the 31st to the 27th, the output result that can make AND gate 118A to 118E is equivalent to the 31st to the 27th value of given address 104 is transferred to biconditional gate 120A to 120E respectively respectively by the 31st to the 27th decision in the given address 104.And the exclusive NOR that biconditional gate 120A and 120E carry out just be equivalent to the 31st to the 27th of more given address 104 whether respectively with normal address 98B in the 31st to the 27th equate.If the words that equate are just exported " very " to AND gate 122.Relatively, similarly be the 26th, the 25th " 0 " among the shade 99B, will make the output of AND gate 118F, 118G must be " puppet ", no matter the 26th, the 25th value is why in the given address 104; And this also just is equivalent to the 26th, the 25th in the given address 104 is covered." puppet " of AND

gate

118F, 118G output cooperates the 26th, the 25th that is received in " 0 " among the last normal address 98B more respectively, will make the output perseverance of

biconditional gate

120F, 120G be " very ", allow the result of AND gate 122 outputs come master control by biconditional gate 120A to 120E.The value of also having supposed given address 104 among Fig. 7 just with Fig. 6 in the same; In the case,, be not inconsistent,, make that comparison module 112B also is " puppet " in the output result of AND gate 122 so biconditional gate 120E is output as " puppet " with the 27th " 0 " of normal address 98B because given address 104 is " 1 " in the 27th value.

Each is used for realizing that function square of the present invention all can use hardware in Fig. 6, Fig. 7, or realizes with software program for execution in the micro-control circuit, or or even realizes with the mode of mixing.For instance, the order module 116 among Fig. 6, logic module 100 available software realize that each comparing unit 112A to the 112D then logical circuit of available hardware realizes.Though be to realize comparing unit among the present invention with AND gate, biconditional gate among Fig. 7, the function of comparing unit also can realize with the mode of software.When the function square of realizing in the executive software mode among Fig. 6,7, software code can be stored in the ROM-BIOS 74 and (ask for an interview Fig. 4).

By above-mentioned discussion to embodiment of the present invention as can be known, because the present invention carries out preliminary address decoder in the mode of bit pattern comparison, so the present invention can quick efficient enforcement.Because carry out bit pattern relatively the time at each comparing unit, be to have in the comparison bit pattern whether corresponding position conforms in the position of fixed value and the given address 104, can be simultaneously, abreast to the comparing of each desire comparison, promptly integrate out the result of comparison again.For instance, when the comparing unit 112B in Fig. 7 operates, can check the 25th to the 31st the corresponding position of whether distinguishing conformance with standard address 98B of given address 104 simultaneously, the result with each bit comparison does AND operation again, obtains the result of comparison.With the running time of digital circuit, in the present invention, each comparing unit is finished in can be at one time simultaneously to everybody shade computing in the given address 104, finish the comparison of each corresponding position more simultaneously, and the result of each corresponding bit comparison done AND operation, draw the last result relatively of comparing unit.Carry out the required time of said process, be exactly haply: the single AND gate that is positioned at is carried out the required time of shade computing, carries out a bit comparison required time in biconditional gate, adds each biconditional gate output result's of AND gate integration time.In three kinds of above-mentioned nonidentity operations, each computing is all quite simple, even can realize with the unity logic door, so the present invention can very finish the running of whole comparison module apace.In comparison, carry out preliminary address decoder with subtraction (being addition in the equivalence) in the known technology, when everybody adds computing, also will wait for time carry that adds computing, so its required time is the result that everybody adds computing required time cusum; With 32 address decoder, a highest wisdom is got 31 to 25 interdigits needs 7 individual bits computing required times (7 gate delays just) just can finish at least.Clearly, preliminary address decoder method of the present invention can be carried out efficiently faster.

As previously mentioned, the present invention is to be that first memory capacity at each memory module sorts basically, decide the address that is dispensed to each memory module with the memory capacity according to each memory module, make the memory module that memory capacity is bigger, the address that its storage unit is assigned is smaller; Therefore and can derive mutual exclusion bit pattern from the address that different memory module was assigned to corresponding to each memory module, with the foundation as preliminary address decoder, if when having 2 memory modules sizes identical, its order is not limit front and back certainly.In addition, in each memory module, there are one or more memory modules (convenient for discussing, below these memory modules are classified as memory module B) the memory capacity sum equals another memory module memory capacity of (being called memory module A) (or total volume of some memory modules, also be called memory module A at this) time, address among the memory module A should be arranged continuously with the address of each memory module B, but the address of memory module A can be greater than or less than the address of each memory module B.No matter the address of each storage unit is the address that is greater than or less than each memory module B among the memory module A, all can produce the bit pattern of mutual exclusion.About this situation, please refer to Fig. 8 A, 8B.Fig. 8 A, 8B for the present invention under the configuration of same memory module, carry out the synoptic diagram of address assignment with different sortords.In Fig. 8 A, 8B, suppose that all memory module 80A to 80D has 3,200 ten thousand, 3,200 ten thousand, 6,400 ten thousand and 51,200 ten thousand memory capacity respectively.In Fig. 8 A, the situation of each memory module address assignment is exactly according to basic principle of ordering of the present invention, memory capacity size according to each memory module is come assigned address, so the address in each memory module can follow the order of memory module 80D, memory module 80C, memory module 80A and memory module 80B to increase progressively, make the memory module 80D of memory capacity maximum, the address minimum that it was assigned to.Maximum and minimum address (similarly being address 132A to 132E) and the bit pattern 134A to 134D that derives out in each memory module have also been indicated among Fig. 8 A.Can find out by each bit pattern 134A to 134D, the mutual exclusion really between each bit pattern.

But, in the configuration of the memory module of Fig. 8 A, 8B, memory capacity 64 megabits that can find memory module 80C just equal memory module 80A, 80B two memory module memory capacity (each 32 megabit) and.Can be considered as memory module 80C one memory module A this moment, and its memory capacity equals two memory module B (just memory module 80B, 80A) memory capacity sum.In this case, even each address of memory module 80C greater than each address of memory module 80A, 80B, also still can produce the bit pattern of mutual exclusion.Shown in Fig. 8 B, to be the address that will increase progressively continuously be assigned to storage unit in each memory module according to the order of memory module 80D, 80A, 80B and 80C to the sortord among Fig. 8 B in regular turn.Also demonstrated the maximum and minimum address (similarly being address 136A to 136F) of each memory module under this kind ordering among Fig. 8 B, and the corresponding bit pattern 138A to 138D that derives out.By can finding out among Fig. 8 B, though the memory capacity of memory module 80C is all come manyly than the individual other memory capacity of memory module 80A, 80B, it is mutual exclusion that the sortord among Fig. 8 B still can make the bit pattern of each memory module correspondence.

In general, under existing technology, the memory capacity of each memory module is 2 power, so when several memory modules B memory capacity sum equals the memory capacity of a memory module A, if make address sequence be incremented to memory module A by each memory module B, will in memory module A, cause extra carry, and " 1 " of this carry can become the fixed value of each address among the memory module A, and then make the corresponding bit pattern of memory module A be able to the bit pattern mutual exclusion with each memory module B.Shown in the example among Fig. 8 B, when the address sequence is incremented to the address 136E of memory module 80C by the address 136D of memory module 80B, can be in the 26th " the 1 " of causing carry of address 136E, and this 26th " 1 " can form the fixed value of each address among the memory module 80C, and the bit pattern 138D of memory module 80C correspondence is also just because of this 26th " 1 " bit pattern 138B, the 138C mutual exclusion corresponding with memory module 80A, 80B.Relatively, if in the ordering of Fig. 8 B, the memory capacity of memory module 80C is not 64 megabits but 128 megabits, and the address of memory module 80C is still increased progressively by address 136D, then the bit pattern of memory module 80C correspondence should be " 0010x ... x " (only the 31st to the 28th is fixed value " 0010 "), and this bit pattern just can be with the corresponding bit pattern 138B of memory module 80A, 80B, 138C mutual exclusion.

In other words, as long as the memory capacity summation of certain several memory module B equals memory module A (memory module A can be one or more memory module and constitutes), no matter address sequence is by the address increment of the memory module A address (situation of image pattern 8A) to each memory module B, or by the address increment of each memory module B address (situation of image pattern 8B) to memory module A, as long as the address of each memory module B and memory module A is continuously arranged, just can form the bit pattern of mutual exclusion.So-called here continuous arrangement, its condition is: arrange continuously the address of (1) each memory module B, except first memory module B (the memory module B of address value minimum just), the address of other memory module B all is the address increment by another memory module B.For instance, as in the example of Fig. 8 A, 8B, the address of memory module 80A, 80B forms the continual address sequence that increases progressively continuously.(2) minimum address begins to continue to increase progressively (similarly being the situation among Fig. 8 B) by address maximum among each memory module B among the memory module A, or minimum address is to begin to continue to increase progressively (similarly being the situation among Fig. 8 A) by address maximum among the memory module A among each memory module B.

Further application about mentioned above principle please refer to Fig. 9 A to 9D.Fig. 9 A to 9D for the present invention under the configuration of another kind of memory module, carry out the synoptic diagram of address assignment with difference ordering situation; Shown each memory module maximum and minimum address (similarly being address 151A to 151B, 152A to 152B, 153A to 153B and 154A to 154B) under address assignment among Fig. 9 A to 9D respectively, and bit pattern 161A to 161D, 162A to 162D, 163A to 163D and the 164A to 164D of each memory module correspondence.In the example of Fig. 9 A to Fig. 9 D, suppose that all the memory capacity of memory module 80A to 80D is respectively 3,200 ten thousand, 3,200 ten thousand, 6,400 ten thousand and 128 megabits.In this kind configuration, the memory capacity of memory module 80C equals the summation of memory module 80A, 80B memory capacity, and the memory capacity of memory module 80D equals the summation of memory module 80A to 80C memory capacity again.So the address of memory module 80C can be arranged in before or after memory module 80A, the 80B continuously, and the address of memory module 80D also can be arranged in before or after the memory module 80A to 80C continuously, always have four kinds of different ordering situations, all can produce the bit pattern of mutual exclusion; Fig. 9 A to 9D has just shown address assignment situation and the corresponding bit pattern under these four kinds of orderings respectively, exchanges if consider the order of identical big or small memory module (memory module 80A, 80B) again, then has 8 kinds of variations, points out no longer one by one at this.The ranking results of picture in Fig. 9 A promptly is according to cardinal rule of the present invention, according to the descending order of memory capacity, makes address sequence follow the order of memory module 80D, memory module 80C and memory module 80A, 80B to increase progressively.But, just as the preceding paragraph falls to being discussed, because the memory capacity of memory module 80D is the summation of memory module 80A to 80C memory capacity, so the address of memory module 80D also can be greater than the address of memory module 80A to 80C.Shown in Fig. 9 B, even being order according to memory module 80C, 80A, 80B to 80D, address sequence increases progressively, also can form the bit pattern 162A to 162D of mutual exclusion.In addition, because the memory capacity of memory module 80C equals the summation of memory module 80A, 80B memory capacity, so the order of memory module 80C and memory module 80A, 80B ordering also can be opposite among Fig. 9 A, become the situation among Fig. 9 C, allow address sequence increase progressively according to the order of memory module 80D, memory module 80A, memory module 80B and memory module 80C.And among Fig. 9 B the ordering of memory module 80A to 80C also rearrangeable be situation among Fig. 9 D, address sequence is increased progressively according to the order of memory module 80A, 80B, 80C and 80D.The ordering situation that please notes Fig. 9 A and Fig. 9 D is just opposite, but because the relation that the memory capacity summation equates between each memory module, the ordering among Fig. 9 D still can sternly be given birth to the bit pattern 164A to 164D of mutual exclusion.

No matter be the situation among Fig. 8 A, B or Fig. 9 A to 9D, all can use the control circuit 78 that shows among Fig. 6 to realize preliminary address decoder of the present invention.For instance, to under the ordering situation of Fig. 9 D, realize preliminary address decoder, bit pattern 164A to 164D can whether more given address 104 meets respectively among Fig. 9 D by the comparing unit 112A to 112D among Fig. 6, the logic module 100 among Fig. 6 then produces decoded result by the comparative result of comparing unit 112A to 112D.

Summing up principle of ordering of the present invention, is the descending order of memory capacity of following memory module basically, assigns cumulative address in regular turn.But if the memory capacity summation of some memory module B equals the memory capacity of another (a bit) memory module A, then the address of memory module A can be arranged in before or after each memory module B address continuously, meet " the memory module capacity summation of the front of certain memory module is the integral multiple of this memory module " as long as can enlarge in addition, this exchange that puts in order is set up.According to principle of ordering of the present invention, just can make the bit pattern of different memory modules, and can carry out preliminary address decoder in the mode of bit pattern comparison corresponding to mutual exclusion.Though aforesaid Fig. 5 to Fig. 9 D discusses the present invention to judge as bit pattern how which memory module given address belongs to, but but also vague generalization of above-mentioned discussion, memory module is considered as the section that storage unit is formed, and spirit of the present invention can derive corresponding bit pattern (and corresponding shade, normal address) by each section, judges section under the given address in the mode of bit pattern comparison.For instance, as long as the storage array in upright arrangement in each memory module is considered as a section, then the present invention also can be used for further judging which storage array in upright arrangement given address belongs to.

In known address decoder technology, be that given address and each end addresses are subtracted each other, judging the magnitude relationship between given address and the end addresses, and further judge given address and belong to which memory module (or storage array in upright arrangement), to finish preliminary address decoder.But given address is being subtracted each other in end addresses and carrying out two-symbol when adding computing, because everybody carry that adds the last position of the essential wait of computing, so the whole computing that given address is subtracted each other in end addresses can only be followed a ground one at each one in the two-address and add computing, the time that it consumed, just everybody adds the accumulated result of computing required time.The time of carrying out the required consumption of preliminary address decoder in the event known technology is longer, so efficient is lower.In comparison, the present invention carries out preliminary address decoder in the mode of bit pattern comparison; With the technology that the present invention discloses, can be by the corresponding bit pattern of deriving mutual exclusion in the different memory modules; As long as given address meets a certain bit pattern, just can judge that given address belongs to the memory module of this bit pattern correspondence.Whether because at bit pattern relatively the time, it is identical with the corresponding position in the given address compare a plurality of positions that have fixed value in the bit pattern simultaneously, no matter will more several positions, its required time just follows more single required time identical basically.So the present invention can carry out preliminary address decoder apace, compare given address with higher efficient and belong to which memory module or storage array in upright arrangement, and and then promote the efficient of whole computer system the storage resources access.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. whether the method for a decoded memory address belongs to one of a plurality of sections of this storer to judge a given address, and each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, and this method includes:

Make corresponding address, less than the corresponding address of the few section of number of memory cells with the many sections of number of memory cells;

By these corresponding address, each section is obtained a bit pattern respectively; And

Relatively whether at least one relatively position of this given address conforms to arbitrary bit pattern, if these compare this bit pattern that the position does not meet arbitrary section, then this given address of expression does not fall within this section, otherwise then this given address of expression falls within this section.

2. decoded memory address method as claimed in claim 1, wherein these sections are a plurality of memory modules.

3. decoded memory address method as claimed in claim 1 wherein obtains a bit pattern respectively to each section, is respectively by whole identical bits of corresponding address in each section, as these bit patterns.

4. decoded memory address method as claimed in claim 1 wherein has interchangeable its order of the identical section of number of memory cells.

5. decoded memory address method as claimed in claim 1, wherein in each section, in regular turn with the corresponding address of different storage unit with the linear increment or the mode of successively decreasing, make the value of a corresponding address and the value of last corresponding address differ certain value.

6. decoded memory address method as claimed in claim 1, wherein the quantity of storage unit is 2 power in each section.

7. whether the method for a decoded memory address belongs to one of a plurality of sections of this storer to judge a given address, and each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, and this method includes:

Carry out the big minispread of number of memory cells of these sections, make the corresponding address of the many sections of number of memory cells, corresponding address less than the few section of number of memory cells, if when the number of memory cells size of at least one first section equaled the number of memory cells size of at least one second section after arranging, then the order of this first section and this second section can be exchanged;

8. decoded memory address method as claimed in claim 7, wherein these sections are a plurality of memory modules.

9. decoded memory address method as claimed in claim 7 wherein obtains a bit pattern respectively to each section, is respectively by whole identical bits of corresponding address in each section, as these bit patterns.

10. decoded memory address method as claimed in claim 7, wherein in each section, in regular turn with the corresponding address of different storage unit with the linear increment or the mode of successively decreasing, make the value of a corresponding address and the value of last corresponding address differ certain value.

11. decoded memory address method as claimed in claim 7, wherein the quantity of storage unit is 2 power in each section.

12. the control circuit of a decoded memory address, to judge whether a given address falls within one of a plurality of sections of this storer, each section is provided with a plurality of storage unit, and the different corresponding address of all storage unit are the binary bit arrangement mode, and this control circuit includes:

One access module receives this given address;

One order module, make the corresponding address of the many sections of number of memory cells, corresponding address less than the few section of number of memory cells, if when the number of memory cells size of at least one first section equaled the number of memory cells size of at least one second section, then the order of this first section and this second section can be exchanged;

One comparison module by these corresponding address, is obtained a bit pattern respectively to each section, with at least one relatively position that receives this given address compare whether conform to after, send a plurality of comparison signals; And

One logic module receives these comparison signals, sends a decoded result, to judge that this given address falls within one of these sections.

13. as the control circuit of the decoded memory address of claim 12, wherein these sections are a plurality of memory modules.

14. as the control circuit of the decoded memory address of claim 12, wherein in the comparison module, each section is obtained a bit pattern respectively, is whole identical bits of getting corresponding address in these sections, as these bit patterns.

15. control circuit as the decoded memory address of claim 12, wherein this comparison module is to be made of a plurality of comparative units, each comparing unit comprises a plurality of first order AND gates, a plurality of partial sum gates and a second level AND gate constitute, each first order AND gate has a shade position that two input ends receive these bit patterns respectively and produced and corresponds to of this given address, each this partial sum gate has two input ends and receives output of one of these first order AND gates and the normal address that these bit patterns are produced respectively, the input end of this secondary AND gate is connected to these distance gate output terminals, and sends this comparison signal.