CN1245921A - Event-driven and cyclic context controller and its application processor - Google Patents
Event-driven and cyclic context controller and its application processor Download PDFInfo
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Abstract
A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) a foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to events and (2) a background task controller, cooperative with the foreground task controller, that cyclicly executes contexts corresponding to active background tasks subject to availability of processor resources while executing the contexts corresponding to the foreground tasks.
Description
The application that cross-reference is relevant
| Series number | Exercise question | The inventor | Date of application |
| ??60/077,469 | ??Context?Controller ??Having?Instruction- ??based?Time?Slice?Task ??Switching?Capability ??And?Processor ??Employing?The?Same | ??Diepstraten， ??et?al. | ??March?10， ??1998 |
| ??60/077,461 | ??Context?Controller ??Having?Status-based ??Background?Task ??Resource?Allocation ??Capability?and ??Processor?Employing ??the?Same | ??Diepstraten， ??et?al. | ??March?10， ??1998 |
| ??60/077,384 | ??Context?Controller ??Having?Automatic ??Entry?to?Power?Saving ??Mode?and?Processor ??Employing?the?Same | ??Diepstraten， ??et?al. | ??March?10， ??1998 |
| ??60/077,406 | ??Context?Controller ??Having?Context- ??specific?Event ??Selection?Mechanism ??and?Processor ??Employing?the?Same | ??Diepstraten， ??et?al. | ??March?10， ??1998 |
| ??60/077,575 | ??Context?Controller ??Having?Event- ??Dependent?Vector ??Selection?and ??Processor?Employing ??the?Same | ??Diepstraten， ??et?al. | ??March?10， ??1998 |
The application of listing is above transferred the possession of jointly with the present invention, at this as an overall reproduced and as a reference.
That this application also requires to transfer the possession of jointly with the present invention and in this U.S. Provisional Application series number 60/077 as a reference, 454 interests, it applies for that on March 10th, 1998 name is called " context in event-driven and cycle (context) controller and application processor thereof ".
Processor in the multi-purpose computer and generally be programmed as the processor of embedded controller and handle a plurality of tasks simultaneously.That a subclass of these tasks must respond is specific, external event is carried out in mode timely, and the execution of these task remainders can not be subjected to strict, restriction in real time.In order to use the individual data path to handle this two group task, effective device of these processor requirements is used for response external incident apace, handles and allow to carry out non real-time when not handling external event.
The dominant mechanism that is used for event response is program interrupt, and it at first is used in the mid-50.In 40 years of past, most of processor structures have comprised a program interrupt function, in case external event takes place, this function is hung up " backstage " task executions and startup " foreground " task executions.Be commonly referred to as each program interrupt of " interruption " and cause reversible variation the executing state of processor according to the requirement (being fit to be synchronized with the instruction stream of processor) of a suitable incident.
The preferential interruption of later stage fifties development is the general enhancing for the program interrupt function.In supporting the preferential processor that interrupts,, distribute different priority statically or dynamically for a plurality of incidents (interrupt request) signal.With in these signals each relevant be to be used for discerning total state the reversible variation of processor executing state unique.When starting the each generation selection preferentially interrupted when interruption status changes and the relevant total state of the highest preferential interrupt request that requires this moment.
Elemental motion when carrying out reversible the variation in the program execution state at processor is the executive address of preserving interrupt routine (and between implicit instruction state, as condition code), and begins Interrupt Process on the program address relevant with the incident that causes interruption.This program address generally obtains from the predetermined storage unit that is called interrupt vector.When interrupt handling routine finishes, the executive address that recovery is preserved (and state value, if any), allow to restart to carry out interrupt routine at the point that interrupts.In most of interrupt handling routines, the essential processor state of preserving and then recovering to add interrupts required operation to carry out response.This additional state mainly is the content of processor register rather than programmable counter.
Preserve these registers to storehouse or special-purpose memory block with recover these registers from storehouse or special-purpose memory block and may consume considerable time quantum.Therefore, owing to the cost and the size that begin to reduce hardware register at the mid-1960s integrated circuit, some processors are equipped with many group registers.By interrupting support hardware or select not on the same group register, allow interrupt response faster in fact to primary memory with from the overhead of primary memory recovery register by eliminating save register by Interrupt Process software.
The notion of multiregister collection (multiple register set) is embodied on the recent model of the IBM System/7 that introduced in 1970.System/7 has a register set special use, that hardware is selected and is used for each interrupt level, stores executive address (program counter value) and further reduces interruption context switching time by being included in each group a register when this grade tried to be the first by an interruption of higher priority.The result is the interruption context switching time of 800ns and the interruption time of return of 400ns, and both in fact are to use the more excellent speed of 16 small-size computers of technology composition in 1969.System/7 also initiates dynamic interrupt distribution, and the priority of being used by each interrupt source is by software setting here, and can be changed during system operation.
The final unification that this register set adds the programmable counter technology is that the permission incident starts handling procedure at their last executive addresss, and does not require that they always are to use interrupt vector address to begin.For control I/O device, data communication and procotol and according to other processing of communication state machine definitions, this is main benefit, because state machine is used for instruction addressing by use and as other programmable counter of level realization of (imply) status register.This does not only need independent status register, and has saved the overhead of selecting the scheduler program of suitable handling procedure according to the value of status register.In fact, register set adds the programmable counter structure provides direct hardware supported to " task " or " execution thread " notion of being supported by operating system software usually.
First machine that uses this technology to attempt to realize I/O state of a control machine and develop designed " Alto " in Xerox Palo Alto research centre in 1972 by Charles Thacker and tests personal computer.Because having developed, many variations of these interruptions of the initial stage seventies and context conversion equipment are used for one chip microcomputer and microprocessor.Yet neither one had been introduced a kind of fundamentally new equipment that is used for the quick context conversion of response external incident during these changed.
In high performance system, usually have special-purpose (one or more) processor and be used for I/O control and/or external event processing.Yet, if realize that to be similar to the technology of in the central processing unit of system, using the utilization of these I/O processors tends to very low.This is because for any specific circuit engineering, be used to realize that the logical device of processor data-path realizes that than being used to the memory device operation of primary memory gets soon significantly, and logic and memory spare can be than any additional higher data bandwidth of peripheral components support.
During the sixties, require a plurality of I/O controllers high performance system mechanical development a kind of technology in a plurality of controller functions, to share the individual data path, even separate on those function logics.This technology is used single physical data routing and command decoder, handles the instruction stream of a plurality of logic processors according to a kind of round-robin method.The unique private resource that is used for each logic processor is the storer that keeps its executing state (programmable counter and register value).Control circuit allows each logic processor to carry out the instruction of predetermined quantity (generally being) continuously, circularly.This control circuit that one of executing state of storage changes enters the data routing between the instruction cycle property that is used for the Different Logic processor easily.This technology at first is used for using on Control Data Corporation (CDC) model 6600 data routing single, that share to realize 10 I/O controllers (being called peripheral processor or " PPU ") by Seymour Cray at the initial stage sixties.
Notice that this logic processor state exchange took place according to time of a strictness, and response external incident not.Really, some the succession models for Control Data 6600 PPU realize the priority interrupt scheme design on their logic processor.Recent this data routing technology of sharing has been applied to central processing unit, and it is called as " the multiple processing of shared resource " here.A plurality of independent instruction streams from different CPU task or program are interlocked to reduce the pipeline dependence in this case, have therefore improved the resource utilization of superscale data routing.
Therefore, need a kind of mode to dispose in the art and distribute context, this context has more generally dirigibility and balance in the management of foreground and background task.
At the deficiency discussed above of prior art, the invention provides a kind of method that is used for context controller and this controller of operation of management processor multitasking.In one embodiment, the context controller comprises: (1) foreground task controller, activate context according to priority and response events corresponding to foreground task, and (2) background task controllers, with the cooperation of foreground task controller, it submits to available processor resource and carries out context corresponding to the background task that activates circularly, carries out the context corresponding to foreground task simultaneously.
The present invention has introduced task has been divided into criterion distribution processor resource that foreground and background task and use the be different in essence generalized concept to foreground and background task.Utilize incident (defining below) to determine when the activation foreground task.On the contrary, activate background task (according to timeslice, instruction sheet or any other periodic allocation) circularly.Foreground task still surpasses background task, allows foreground task with mode processing events timely.Setting up of the solution of relative priority between the foreground task to help in resources allocation, to conflict.
In one embodiment of the invention, a software transition status differentiates foreground task and background task.In the embodiment that will be illustrated and describe, software convert packets be contained in each context related task programmable register in.For the present invention, " context " is defined as all processor state information that can be used for restore processor to a given state (perhaps its any subclass, and as register value).The context controller detects the state (0 or 1) of conversion to determine that related task is foreground task or background task.Certainly, the indication of foreground and background task can be that cost produces in hardware to sacrifice dirigibility.
In one embodiment of the invention, selection incident from the group of (1) external event and (2) internal event formation." incident " is defined as a kind of excitation, and it can cause that the context controller responds from a foreground task and be transformed into another.External event has its source and can take place at any time outside processor.Internal event in processor, have it the source and with the clock synchronization of processor.
In one embodiment of the invention, allow next backstage context carry out before the background task controller according to each such context of carrying out some predetermined quantities instructions to contextual execution sequencing corresponding to background task.Here this is called as " instruction sheet (Slice) ".Can carry out the contextual execution in backstage according to the time (" timeslice ") in addition.Certainly, other that are used for carrying out circularly judgement are according to being in gamut of the present invention.
In one embodiment of the invention, each contextual state storage is in a register set of separating.Some processor structures are supported a plurality of physical register collection, on the logic register there of remapping when Task Switching.On the other hand, primary memory part can be used for the storage block storage register content of separating.
In one embodiment of the invention, when all foreground tasks and background task during in non-activation context controller set handling device in idle condition.In the embodiment that will be illustrated and describe, processor keeps preparing the generation of the incident that acts on during idle condition.
In one embodiment of the invention, but the foreground task controller is applicable to the context of activation corresponding to a specific foreground task by turning to the software select storage unit.Owing to allow the inlet point of specific foreground task to change, can set up state machine, the initial abnormal address that wherein is used for the context activation allows the function execution of foreground task as the incident of impelling it to carry out also as positioning indicator.Certainly, identical state machine is handled and can be produced with respect to the activation of background task.
The front has been summarized feature better and on the other hand of the present invention quite widely makes those skilled in the art can understand following detailed description of the present invention better.Other features of the present invention will be described in the claims of the present invention that after this form.It should be appreciated by those skilled in the art that they can easily use disclosed notion and certain embodiments as design or the basis of revising other structures that are used to realize the identical purpose of the present invention.Those skilled in the art should be realized that this similar structure does not deviate from the spirit and scope of the present invention with regard to form the most widely.
For a more complete understanding of the present invention, carry out following description now in conjunction with the accompanying drawings.
Fig. 1 has illustrated the state transition diagram of showing an embodiment operation of processor of the present invention with each contextual viewpoint;
Fig. 2 has illustrated to have the possible processing stream of demonstration on five foreground contexts and three the contextual processor operations in backstage, trying to be the first and the synoptic diagram of context internal communication;
Fig. 3 has illustrated each context control and status register of the demonstration that utilizes the embodiment of the invention can enter the software of carrying out in the processor.
Fig. 4 has illustrated in conjunction with the exemplary processor of context controller embodiment of the present invention or the system diagram of I/O controller;
Fig. 5 has illustrated the interaction diagram of showing context controller inner structure illustrated in fig. 4;
Fig. 6 has illustrated the fate map that event synchronization illustrated in fig. 5 is handled.
Fig. 7 A, 7B, 7C and 7D illustrated together the fate map of incident priority processing of Fig. 5 explanation;
Fig. 8 has illustrated a sequential chart that is used for by the context conversion of the present invention's control, wherein current contextual state storage is to synchronous (self-timing) SRAM or register file, and next contextual state loads from synchronous (self-timing) SRAM or register file;
Fig. 9 has illustrated a sequential chart that is used for by the context conversion of the present invention's control, and current here contextual state storage is to asynchronous SRAM or register file, and next contextual state loads from asynchronous SRAM or register file;
Figure 10 has illustrated the synoptic diagram of a circuit embodiments, and this circuit is applicable to realization event record, event mask and confirms for each incident that activates incident, and the management of context activating position, comprises initialization requests and waits for the request logic;
Figure 11 has illustrated according to one embodiment of present invention about the field of the machine instruction of communication and position distribution between context control and context in the instruction group;
Figure 12 has illustrated the potential source that is used to produce the control store address on the processor according to one embodiment of present invention;
Figure 13 has illustrated the exemplary data structure figure that is used for according to one embodiment of present invention at the control store initialization vector; And
Figure 14 has illustrated according to one embodiment of present invention and has described the figure that destination address produces by being used in the vector instruction of arranging and decipher specific context activating position on the processor by precedence.
At first with reference to Fig. 1, the state transition diagram of operation of showing an embodiment of processor of the present invention with each contextual viewpoint is described.The invention provides the criterion that the context controller that is used for the management processor multitasking and use be different in essence and introduce the generalized concept that task is divided into foreground and background task.Utilize incident (can cause the excitation of foreground context switching motion) to determine to carry out which foreground task in conjunction with the relative priority level of distributing to various tasks.On the contrary, background task is carried out with being recycled and can or be handled the distribution in any other cycle of resource based on timeslice, instruction sheet.
According to explanation embodiment of the present invention, the multitasking of context controller management foreground and background task activates.When front and back relations is that the generation that context activates only responds the generation according to the incident of priority under the guidance that can manage a collection of contextual foreground task controller during in foregrounding.When activating simultaneously, a plurality of foreground tasks between foreground task, set up relevant priority to help the solution of conflict.In addition, become the contextual execution of to try to be the first when activating when the foreground of higher priority context.
When front and back relations is under the guidance that can manage a collection of contextual background task controller during in consistency operation, can be by any foreground context that allows timely processing events this contextual execution of trying to be the first.Cooperation of background task controller and obedience are corresponding to the contextual activation of the foreground task of operating under the foreground task controller.Yet in the embodiment of explanation, all activated backstage context is shared processing device resource on the basis in cycle.Between the instruction number of software dictates (an instruction sheet) has been carried out with the backstage context that is activating, distribute liberally can obtain handling resource after, can the try to be the first backstage context of each operation of context controller.The contextual activation in backstage can be in addition according to time (timeslice).Certainly, other that are used for activating circularly are according to being in gamut of the present invention.
According to backstage time quantum rather than absolute time by the instruction number of software dictates or counting is the distinguished characteristic of explanation embodiment.This improved properties the fairness of processing resource allocation between the backstage context that activates.If use absolute time, between the task of occurring in the equal priority of moving on the conventional processors under the real-time system operating system, by activating the generation of the contextual incident in one or more foregrounds during the contextual timeslice in backstage, the instruction number that given backstage context can be carried out in its timeslice may reduce, may arrive zero.By for example using an instruction count or instruction sheet, present embodiment allows the backstage context of each activation to finish identical workload before the cycle of background process repeats.For a backstage context of giving the activation of determined number, spinoff the duration of being backstage cycle absolute be variable, obey that the foreground is contextual tries to be the first.
In many prior art systems, this can constitute a problem, i.e. the timely execution of interference period task.Yet in the embodiment of explanation, any activity with strict time restriction can be assigned on the foreground context of suitable priority.The embodiment that illustrates has improved the reliability that satisfies the real-time response restriction and has improved the fairness of the processor distribution between the background task group that activates.
In any preset time that processor is being operated, each context can be one of six states, and these six states multiply by two row (2 * 2) matrixes as two row and logically are divided into four groups.Top or foreground row 10 comprise three states: by Rf state 18, Pf state 20 and the Wf state 22 (each comprises " f " on an expression foreground here) of foreground context use.Bottom or backstage row 12 comprise three states: by Rb state 24, Qb state 26 and the Wb state 28 (each comprises " b " on an expression backstage here) of backstage context use.Activate row 14 and comprise by activating the one of four states 18,20,24,26 that context is used, comprise two states 22 and 28 that use by non-activation context respectively but not activate row 16.
Most of context conversions allow to occur in foreground row 10 or the backstage row 12, because only need in the ranks to change when the front and back relation is changed between the foreground that can be distinguished by the software conversion operations and consistency operation task.Yet this may activate, try to be the first and wait for and take place to such an extent that lack than context.The software conversion operations can be by controlling with each context related task programmable register.The context controller detects the state (0 or 1) of conversion to determine that related task is foreground task or background task.The indication of foreground and background task also can produce in hardware, is cost to sacrifice dirigibility certainly.When the conversion from the foreground to the backstage may only occur over just foreground context Rf 18 execution CLRFG (" removing the foreground ") functions 34 of operation, it caused being transformed into background queue state Qb 26 from foreground running status Rf 18.Because between the context of backstage without any relative priority level difference, the position of carrying out in the contextual background queue of CLRFG function 34 is arbitrarily.
The context of carrying out CLRFG function 34 is left foregrounding and is abandoned processor control (doing as the context of carrying out WAIT function 32 or 42) for the instruction cycle of a minimum valuably.If lower priority foreground context is at the state Pf 20 that tries to be the first, then this lower priority foreground context operation next (through limit priority conversion 36).State Pf 20 is unoccupied if try to be the first, and then the operation of the context of trying to be the first in background state Rb 24 is next, unless background state Rb 24 is also unoccupied.In this case, the context elapsed time sheet of background queue first place begins to change the 44 operation next ones in background queue state Qb 26.In the embodiment of explanation, this occurred in after the single instruction cycle of processor free time, because front stage operation state Rf 18 and background operation state Rb 24 are unoccupied.
When the conversion between backstage and the foreground generally occurred in context execution SETFG (" foreground is set ") function 30 of background operation state Rb 24, it caused its conversion from background operation state Rb 24 to front stage operation state Rf 18.But also can take place by turning to the specific contextual foreground of software select storage unit to activate.Owing to allow the inlet point of specific foreground task to change, can set up state machine, allow foreground task to carry out as the function of the incident of impelling it to carry out.Certainly, identical state machine is handled also and can be taken place with respect to the activation of background task.
For the mistake that prevents the context operation is interrupted, available function does not comprise a kind of device valuably in the context controller, can change any other contextual foreground or backstage setting and need not force this contextual initialization (INIT) yet by this device operation context.The INIT function can be carried out as the context of the operation of target by having any other context.The INIT function can be carried out the context of operation, unless but do not exist any reason to do certain embodiments like this to add that additional initialization spinoff is to the INIT function.As below will further going through, the execution of INIT function is set to predetermined initialization vector address to the foreground programmable counter that the target context of state Pf 20 stays it of trying to be the first.
Usually, the target of INIT function resides in foreground waiting status Wf 22 and enters the foreground state Pf 20 that tries to be the first through conversion 40.Perhaps it can reside in backstage waiting status Wb 28 and enter the foreground state Pf 20 that tries to be the first, and is transformed into the foreground through conversion 50 from the backstage.In fact, if the target context resides in background operation state Rb 24 or background queue state Qb 26, conversion 50 also is possible with identical, but Fig. 1 does not illustrate both of these case.
When processor reset finished, all contexts were at foreground waiting status Wf 22, except the lowest priority context at front stage operation state Rf 18.The software of carrying out context front stage operation state Rf 18 can be transformed into context foreground waiting status Wf 22 by carrying out 32 one of the startup of WAIT function.Foreground waiting status Wf 22 contexts are transformed into the foreground state Pf 20 that tries to be the first with any contextual activation incident of the requirement that allowed by contextual event mask, perhaps are transformed into this context foreground state Pf 20 that tries to be the first through conversion 40 when the operation context is carried out the INIT function.
In the embodiment of explanation, when the context of trying to be the first conversion may occur in the end of each instruction cycle, if any, limit priority context with the state Pf 20 that tries to be the first on the foreground enters front stage operation state Rf 18 through limit priority conversion 36, and if any, the context of the front in front stage operation state Rf 18 activates conversion 38 through higher priority and enters the foreground state Pf 20 that tries to be the first.
Can be at the software that context background operation state Rb 24 carries out by carrying out the conversion that WAIT function 42 starts to backstage waiting status Wb 28.The context of backstage waiting status Wb 28 is transformed into background queue state Qb 26, these incidents with any contextual activation incident of the requirement that allowed by contextual event mask.Can only occur in when moving (the state Rf 18 without any context) from the conversion of background queue state Qb 26 to background operation state Rb 24 without any the foreground context.In this case, if any, the context of operation is at background operation state Rb 24, and perhaps processor is in idle condition, because prepare on the foreground or running background without any context.
When each finished instruction cycle, along with the context operation at background state Rb 24, the timeslice counting successively decreased, and when counting arrives zero on the instruction cycle, the preferential generation of timeslice context conversion.In this point, the context in the first place of background queue enters background operation state Rb 24 through conversion 44, and before enters background queue state Qb 26 in the context of background operation state Rb 24 through conversion 46.
Usually, when previous operation backstage context entered background queue state Qb 26, " the circulating type processing " that employing takes place from the highest context quantity to minimum context quantity was with the context of having arranged and organized background queue of first in first out (FIFO).Should notice trying to be the first in the foreground comprises one through conversion 36 state exchange, and does not have the backstage to be tried to be the first by the foreground.In this case, the backstage context of previous operation be retained in state Rb 24 up to front stage operation state Rf 18 unoccupied once more and backstage context can move.
Forward Fig. 2 now to, illustrate have the possible processing stream of demonstration on five foreground contexts and three the contextual processor operations in backstage, try to be the first and context between the synoptic diagram of communication.Context can be activated by the requirement of an event signal.
Each relevant context can be 0 or more external event signal and 0 or more internal event signal.Main difference outside and the internal event signal is that external event has their sources outside processor, and can take place at any time, their signal was synchronized with the clock of processor valuably before context activated and judges in being used to the context controller.On the contrary, internal event has their sources in processor, and their signal supposition is synchronized with the clock generating of processor and can directly uses.
By under software control, in specific context event mask register, being provided with and the zero clearing position can allow and forbid each contextual activation incident.Except because from external source such as external disturbance, perhaps beyond the requirement of the activation incident that requires from the hardware signal of inside sources such as intervalometer, coprocessor or data transfer logic, can use signal instruction by software requirement some and all incidents, these instruction regulations event group internal object context quantity and event number relevant with the target context.Because any context can be sent out event signal and give itself or other contexts, this embodiment that allows explanation is used between context inside and the context communication as a kind of effective device and as priority interrupt control unit with as the timeslice controller.
In Fig. 2, Z-axis is represented context, and transverse axis is represented to activate for the context of one of eight contexts supporting at the context controller of demonstration.Transverse axis is the time, and unit is an instruction execution cycle.Be used for the contextual wide black line in foreground and be used for the context that the contextual wide cross hatch in backstage illustrates operation.The perpendicular line that has arrow illustrates the context conversion and is labeled the reason that takes place with the conversion of identification context.Pass little perpendicular line presentation directives's cycle of wide line.Being used for the backstage context when instruction is carried out is the value of timeslice instruction counter at each number above instruction cycle interval.Be used for the contextual narrow empty black line in foreground and be used for the context of trying to be the first that the contextual narrow intersection shadow in backstage is shown in dotted line activation.Narrow dotted line illustrates backstage context activation, queuing.This embodiment has eight contexts, is expressed as context 0 (limit priority) to context 7 (lowest priority), and with timeslice operating period eight instruction count or instruction sheet is arranged at this example.
When this example began, context 0,2,4 and 5 was non-activation foreground context (state Wf) entirely. Context 3,6 and 7 is the backstage context entirely, and context 3 is non-activation (state Wb), and context 7 is that (state Qb) and the context 6 of queuing is (the state Rb) of operation.
During the same instructions cycle 64, backstage context 3 is carried out first instruction of its timeslice 7, and external event 66 activates foreground context 0.Therefore, when the end of this instruction cycle 64, it is tried to be the first by foreground context 0 during the timeslice count value remains on seven try to be the first in backstage context 3.After carrying out three its activation incidents of instruction process, foreground context 0 is carried out the WAIT function during the 4th instruction cycle 69.This WAIT function is for the activated trigger zero clearing of foreground context 0, and foreground context 0 becomes non-activation after another instruction cycle, is turned back to waiting status Wf.This backstage context 3 that generally allows to try to be the first is restarted operation, but in this example when foreground context 0 is being moved external event 68 activated foreground context 5.Notice that this state that activates foreground context 5 changes to the state Pf that tries to be the first from waiting status Wf, this illustrates for the foreground context because how activation may enter the state of trying to be the first and do not carry out any instruction.
If backstage context 3 is in foregrounding, then foreground context 5 is that it doesn't matter at the state Pf of trying to be the first when foreground context 0 is turned back to waiting status Wf, because backstage context 3 is than the priority height of foreground context 5.Yet, context 3 is in consistency operation, so the WAIT function of being carried out by foreground context 0 69 causes context to be transformed into foreground context 5, this context 5 enters running status Rf and begins to execute instruction 70 and backstage context 3 remains on trying to be the first among the state Rb.
After carrying out two its activation incidents of instruction process, foreground context 5 is carried out the WAIT function during the 3rd instruction cycle 71.This WAIT function zero clearing activated trigger f or foreground context 5, and after another instruction cycle, context 5 becomes non-activation and is turned back to waiting status Wf.Because at this moment the foreground context without any other activates, the backstage context 3 of trying to be the first restarts to move and carry out at state Rb second instruction of its timeslice 72.In the next instruction cycle, backstage context 3 is carried out WAIT function 73.WAIT function 73 is more than the activated trigger zero clearing of backstage context 3, and after another instruction cycle, backstage context 3 becomes non-activation, is turned back to waiting status Wb.This allows the backstage context 6 of queuing to turn back to running status Rb in the instruction cycle 74.Even notice that this context conversion is not decremented to 0 by the timeslice counting and starts, backstage context 6 thinks that seven All Time sheet count value enters running status Rb in the instruction cycle 74, rather than the part-time sheet residue of inheriting when backstage context 3 is carried out WAIT function 73.
As its second instruction, owing to may recover from the software error the code of being carried out by context 1, backstage context 6 is carried out INIT function 76 to force foreground context 1 to enter a known state for foreground context 1.This INIT function activation context 1 is the foreground context state Pf that tries to be the first, and the context 1 initialization vector address of beginning in control store carried out and be provided with.Because the foreground context that activates now exists, after carrying out, another instruction is transformed into the context 1 backstage context 6 (trying to be the first a little 77) of trying to be the first by context.In its second instruction, context 1 is carried out CLREG (position, zero clearing foreground) function 78, and this function causes that context 1 enters background queue state Qb.Because context 1 is now in background queue and in context of state Rb existence, context 1 is abandoned the control (abandoning a little 80) of processor after following the instruction cycle that CLREG function 78 carries out, and therefore permission restarts to carry out the remainder of its timeslice 82 in the context 6 of state Rb.
At the remainder of this detailed description, numeric constant is metric, unless " 0x " before arranged, and they are sexadecimal in this case, and a position, position is digital, and position 0 is a least significant bit (LSB).
Forward Fig. 3 now to, illustrate and utilizing the embodiment of the invention can enter each context control and status register of the demonstration of the software of carrying out in the processor.In the embodiment of explanation, nine control bits of each context 84 have the value of being determined by software, nine mode bits of each context 86 have the value of being determined by the context controller hardware, but their value can otherwise be read or be detected by software.The context controller keeps each contextual a part of state.These mode bits are not the parts (it is saved and recovers in the context transition period) of executing state, because the specific context state in the context controller is used for by activating the input that logic is asked unceasingly and also decision logic is changed in conduct for context.
Each context control bit 84 comprises position 88, a foreground (FG) and event mask register 90.FG position 88 equals 1 when front and back concern on the foreground.When this context the FG position 88 that illustrates is carried out by the hardware reset of INIT function and is provided with during as the target of regulation, perhaps when this context is being moved by the execution setting of SETFG function.The FG position 88 of explanation is by the execution zero clearing of CLREG function when this context is being moved.Event mask register 90 have one corresponding in the activation incident relevant with context each the position.
In the embodiment of explanation, each context is assigned with eight activation incidents; Therefore event mask register 90 comprises eight.A given activation incident only activates a context when the value that equals the corresponding positions positional number of event number in context event mask register 90 is 1.Yet as below being further explained in detail, the requirement that activates incident is recorded in the event trigger, and this trigger keeps being provided with the execution up to the ACKNOWLEDGE that is used for predetermined bits (ACK) function.The setting of event trigger is not subjected to the influence of incident mask register 90 contents.
Each context mode bit 86 comprises an ACT position 92 and a state-event register 94.ACT position 92 equals 1 when the front and back relation activates.The requirement of incident is activated by non-shielding in ACT position 92, promptly be used for requirement activation incident unconfirmed the event mask position setting or be provided with when the execution of this context INIT function during as the target stipulated.ACT position 92 is passed through hardware reset zero clearing (except context 7, the ACT position is by the hardware reset setting) here, and removes by the execution of WAIT function when the front and back relation is being moved.State-event register 94 have one corresponding to the activation incident relevant with context each the position.These positions are also referred to as event trigger in the some parts of this detailed description.
As mentioned above, in the embodiment of explanation, each context is assigned with eight activation incidents, and regulation state-event register 94 comprises at least eight.Corresponding to the incident reading that requires the position equal 1, and corresponding to the failed call incident, comprise affirmation the incident reading the position equal 0.Each state-event register-bit (event trigger) is provided with by the context controller hardware according to the detection of the requirement (generally being one 0 to 1 conversion) of inside or external event signal.Also the execution as the SIGNAL function of the object event of purpose is set up according to regulation in this context in each state-event position.When this context was being moved, each state-event register-bit was by hardware reset with by object event is carried out the ACK function and zero clearing as the target of regulation.In some cases, special ACK function also may be as carrying out other instructions or visiting the spinoff of special data routing (general I/O port) register and produce.
The realization example that the explanation context defined and be used for IEEE 802.11 medium access control sublayers (MAC) controller is shown below.The function of mac controller has been divided into eight contexts, is expressed as 0 to 7,0th, limit priority.Context 0 to 5 is foreground and 6 and 7 backstages preferably preferably.Each context has the default situation below eight activation incidents and the general application of each activation incident:
A. use the SIGNAL function can not require an incident (unless this incident specially gives over to such purpose);
B. use the ACK function to remove an incident;
C. timer terminal count incident takes place when corresponding timer is decremented to 0;
D. write the control register of corresponding timer and, remove timer terminal count incident by ClearTC (position 2) being equaled 1 without the ACK function; F. " requirement " of external event signal be defined as 0 to 1 conversion; G. " non-" of external event signal means 1 to 0 conversion; And this title that H. selects when control bit equals 1 is significant.The context of demonstration and their corresponding activation incident are described below.(and high priority, real-time event) supported in context 0-debugging: activation incident: 0) Hardware Breakpoint (BKPTin); 1) software breakpoint (signal 0,1); 2) the GP serial-shift is finished or the UART transmitter is finished (GPDN/UTXDN); 3) intervalometer A terminal count (INTATC); 4) the UART receiver is finished (URXDN); 5) intervalometer B counting (INTBTC); 6) main frame (computer system) is noted (HATN); And 7) coprocessor is noted (CPATN).Low MAC (LMAC) abnormality processing of context 1-: the activation incident: 0) the modem data interface is noted (MDIATN); 1) physical layer data unavailable (! PDA); 2) IFS (interframe space) timer terminal count (IFSTC); 3) communication between the context of (signal 1,3) from MMAC to LMAC; 4) the Physical layer transmitter be not ready for (! TXR); 5) beacon/stop timer comparer equates (BCNTC); 6) modem data interface programmable bit border (MDIBIT); And 7) the modem management interface transmits and finishes (MMIDN).Context 2-is low, and MAC (LMAC) data transmit the activation incident: 0) the modem data interface is noted (MDIATN); 1) intervalometer B terminal count (INTBTC); 2) IFS (interframe space) timer terminal count (IFSTC); 3) communication between the context of (signal 2,3) from MMAC to LMAC; 4) TSFT (synchronizing function timer) circulating type is handled (TSFWRP); 5) NAV (network allocation vector) timer terminal count (INTCTC); 6) physical layer medium busy (MBUSY); And 7) physical layer medium be not in a hurry (! MBUSY).Context 3-host interface is supported: activation incident 0) 0 biasing of buffer access path solves (BUFATN0); 1) 1 biasing of buffer access path solves (BUFATN1); 2) be used to report to communication between the context of state of main frame (signal 3,2); 3) buffer access path 0 block boundary intersection (BLKATN0); 4) buffer access path 1 block boundary intersection (BLKATN1); 5) be used to report to communication between the context of state of main frame (signal 3,5); 6) the host interface register is noted (HATN); And 7) from communication between the context of backstage (signal 3,7).The medium MAC of context 4-(MMAC) media interviews and timing: activation incident: 0) from communication between the context of LMAC or HMAC (signal 4,0); 1) previous busy medium become available (MAVL); 2) IFS/ timeslice timer terminal count (IFSTC); 3) intervalometer A terminal count (INTATC); 4) beacon/stop timer comparer (BCNTC); 5) the modem data interface is noted (MDIATN); 6) software mark 3-0 (sharing) with context 7, incident 7; And 7) the modem management interface transmits and finishes (MMIDI).Context 5-WEP (wired equivalent privacy) deciphers support: the activation incident: 0) be used for communication between the context of status report (signal 5,0); 1) the decruption key flow valuve is prepared (DECRYPT); 2) the GP serial-shift is finished or the UART transmitter is finished (GPDN/UTXDN); 3) communication between context (signal 5,3); 4) the UART receiver transmits and finishes (URXDN); 5) communication between context (signal 5,5); 6) intervalometer D terminal count (INTDTC); And 7) the modem management interface transmits and finishes (MMIDN).The accessing points function that context 6-is additional: activation incident: 0) software mark 11-8; 1) software mark 15-12; 2) the GP serial-shift is finished or the UART transmitter is finished (GPDN/UTXDN); 3) intervalometer A terminal count (INTATC); 4) software mark 7-4; 5) intervalometer B terminal count (INTBTC); 6) intervalometer D terminal count (INTDTC); And 7) coprocessor is noted (CPATN).The higher MAC of context 7-(UMAC) and use mixedly support: activation incident: 0) software mark 19-16; 1) software mark 23-20;
2) software mark 27-24;
3) intervalometer A terminal count (INTATC);
4) beacon/stop timer comparer (BCNTC);
5) intervalometer B terminal count (INTBTC);
6) intervalometer D terminal count (INTDTC); And
7) software mark 3-0 (sharing) with context 4, incident 6.
Forward Fig. 4 now to, the exemplary processor of the embodiment of description taken in conjunction context controller of the present invention or the system diagram of I/O controller.This figure (and those in Fig. 5,6 and 7, illustrate) use by International Telecommunications Union (ITU) at telecommunication standardization sector's recommended technology standard known diagram syntactic representation of (03/93) standardized Specification ﹠ Description Language (SDL) Z.100.
Use the descriptive language of this form to represent that system performance is because can obtain more accurate and applicability widely.For example illustrated paragraph can be used to emphasize the realization feature of embodiment.Yet,, may omit the another kind of processor that the implicit aspect that is used for the control sequence of this processor still goes for using different structure for the diagram of par-ticular processor because this context controller can be applicable to the almost processor of any kind.Similarly, Chang Gui constitutional diagram is a kind of more informal symbolic representation of scheming similar purpose to the SDL processing that has.But SDL has the diagram grammer, clearer and more definite of strict difinition.Really, have been found that many in the characteristic of sort controller " boundary conditions " fully do not explain with conventional constitutional diagram.Here the example of all these boundary conditions that describe to be covered by SDL comprises: (1) if context between the execution of WAIT function and the execution of the WAIT function after, instructing, tried to be the first, can what's going on? (2) if carry out for the ACK function that causes the incident that it activates between the order period of a context after carrying out the WAIT function, can what's going on? and (3) are if the contextual timeslice in backstage is being carried out the identical instruction cycle end of SETFG function as it, does this context remain running in the foreground or carries out an instruction in the next context of state Qb before being tried to be the first by new foreground context? similarly, SDL can be than the characteristic of more accurately and more clearly describing the context controller that narration in English may be done.Therefore, the SDL that describes in the paragraph below is as the structure of the key property of some embodiments of the invention and the general and detailed guide of intended purposes.
The Figure 100 of SDL system is illustrated in the relevant top functional block of the processor that uses among the explanation embodiment. Textual character 102 and 104 comprises definition that particular system expands to the predefined data type of SDL, be used for through the explanation of the long-range variable of the implicit expression interblock communication of output/input device and be used for the title of signal of explicit interblock communication and the explanation of parameter type.Shown in the Figure 100 of system comprise five functional blocks: clock generator 106, sequencer 108, command decoder 112, data routing and interface resource manager 114 and context controller 110.
The time base reference (for example crystal-controlled signal) that clock generator 106 process ClocksIn channels 122 receive input clocks or produce clock, and process ResetIn channel 120 receives hardware reset signals.The cycle clock that clock generator 106 produces by every other use.These cycle clocks will be further divided into four parts that equate in fact the instruction cycle.This uses the square wave of pair of orthogonal to realize, causes at four clocks along starting different actions.At clock waveform actual shown in Fig. 8 and 9, major clock MCLK signal 504 defines the instruction cycle border, and the clock QCLK signal 506 of quadrature provides other clock edge in each instruction cycle.Four continuous order in edge are: the rising edge of MCLK signal 504, be expressed as Mr 517, the end of an instruction cycle of mark and the beginning in next instruction cycle, the rising edge of QCLK signal 506, be expressed as Qr 518, it is in the generation in 25% o'clock through each instruction cycle, and the negative edge of MCLK signal 504 is expressed as Mf519, it is in the generation in 50% o'clock through each instruction cycle, and the negative edge of QCLK signal 506, being expressed as Qf 520, it is in the generation in 75% o'clock through each instruction cycle.
In the SDL model, clock generator 106 sends suitable Mr 517, Qr 518, Mf 519 or Qf 520 signals and reset signal arrives every other functional block.When processor in operation or clock generator 106 operations when idle, but during very lower powered sleep pattern, can close its most of circuit, comprise the generation of MCLK signal 504 and QCLK signal 506, when clock generator 106 receives sleep signal from context controller 110 through channel ClkCctl 140, can enter sleep pattern.
In many realizations, can not during each clock period, carry out an instruction.Therefore, be true time (seeing textual character 102) what discern by long-range Boolean variable " ien ", command decoder 112, sequencer 108 and context controller 110 are only finished their function during the actual cycle of carrying out of instruction.
Data routing and interface resource manager 114 expression processor remainders comprise ALU, the visible register of programmer or the like.All I/O devices, principal computer (if any) and local data memory interface (channel 126,128,130,132) are connected to this functional block.Data routing and interface resource manager 114 sends event signals to context controller 110 and receive AckEv signal from context controller 110 (it represent that software carried out the ACK function to confirm a specific previous incident), CsLoad and CsStore signal (recovering and storage context status information) and SetCy and ClearCy signal (being used for setting and removing carry flag hardware reset and INIT function after) through CctlIDP channels 143.This functional block is also exported ien (if present clock period is the instruction performance period then equals true) and the sheet value of (be used for the last value of the software dictates that initial order counts or be used for the instruction sheet of each backstage timeslice).
Forward Fig. 5 now to, show that the SDL of the inner structure of context controller 110 illustrated in fig. 4 handles interaction diagram.Here do not represent other inner structures of top, because they are not parts of the present invention and do not require that they understand the characteristic of context 110 controllers.
Two kinds of processing that are included in the context controller block 110 are described.Event synchronization device 150 receives from the external event signal of AsyncEvents signal route 158 and they and major clock rising edge Mr 517 are synchronous, and this rising edge is provided through ClkSyn signal route 156 by clock generator 106.These course of events SyncEvents signal route 166, as event signal just (intrinsic synchronous) event signal from inside sources on PriDP signal route 164 send.
Basic in this embodiment context state of a control machine is arranged operation in the processor 152 at Event Prioritization.The input signal that Event Prioritization arrangement machine 152 receives from clock generator 106 through ClkPri signal route 154 is through the event signal of SyncEvents signal route 166 receptions from the data routing CctlDP function 143 of event synchronization device 150 and process PriDP signal route 164.In addition, be used for context control and context between the decoded signal of the relevant various instructions of communication receive from command decoder on InstCctl channel 142 through InstPri signal route 162.
Forward Fig. 6 now to, the processing figure that the event synchronization of key diagram 5 is handled, it has described the operation of data synchronization unit 150.This is handled and guarantees to preserve each input ExtEvent signal 208 up to major clock rising edge Mr 206 generations, and the ExtEvent signal 214 of all preservations this moment is received and delivers to Event Prioritization arrangement machine 152 at once as Event signal 218.
Forward Fig. 7 A, 7B, 7C and 7D now to, their illustrated together the processing figure of incident priority processing of the state exchange handled of the definition Event Prioritization arrangement machine 152 shown in Fig. 5.This processing has realized event-driven and timeslice context translation function for this embodiment of the present invention.
Fig. 7 A has defined starting and homing sequence.In " all states " symbol 272, preempt every other input signal and make that handling input queue (symbol 276-280) is brought down stocks in adding starting initialization (symbol 282) reset signal 274 before begin symbol 254 beginnings.The all correlated variables of sequence (symbol 256-270) initialization, remove event mask, state-event register and wait for trigger, it is the foreground that all contexts are set, and removes all ACT triggers, except the context 7 that is compelled to activate.
Fig. 7 B has defined the second half in each cycle, the operation of Mf during the Mr cycle (cycle of a next rising edge Mr) from major clock negative edge Mf to it, and follow hard on incident after the reception of major clock rising edge Mr 292.Operation all has identical conversion with idle condition 284, because carry out an instruction during the cycle after following the WAIT function closely, and because incident may take place and need be processed during any cycle, comprises that working as processor is the idle time.At Mf during the Mr cycle, except ACK (AckInst), WAIT or SLEEP function 300 all instruction decode signals are handled at once.These three signals are saved for after major clock rising edge Mr 292 and handle, because must handle them after treated all event signals 288.If context conversion takes place, the instruction of handling before at major clock rising edge Mr 292 (being signal 286,290,294,296,209) may change must be in the information of major clock rising edge Mr292 preservation.
After major clock rising edge Mr 292, go up the value (is-symbol 320,321 respectively) of upgrading CSW (the context conversion that is indicating), CTX (current context number), NCTX (next context number) and event mask and state-event register for the cycle of true (1) (293) at ien.Processor can enter sleep state (symbol 338), and processor clock stops during this period, and has only the operation of low frequency sleep timer to cross the generation of (a Wake signal is in symbol 340) or hardware reset up to the length of one's sleep.If not sleep, if the backstage context is moved (symbol 326,328), timeslice instruction count successively decrease (symbol 330).Be decremented to 0 (symbol 332) as the chankings counting, by circular treatment curBg (when the AM/BAM context) pointer being advanced a unit sheet start-up time context conversion, calculate contextual number (symbol 334) by mould, and the timeslice instruction count resets (symbol 335) to its programming value.Enter in a preferential order ordered state 336 then to handle Mr to the Qr cycle (a cycle) from major clock rising edge Mr to next orthogonal clock rising edge Qr.
Fig. 7 C has defined the operation in during the first quartile in each cycle (Mr is to the Qr cycle).This time is to be updated when preparing to make context conversion judgement an orthogonal clock rising edge Qr 380 after at the incident conductively-closed of major clock rising edge Mr 292 sampling and ACT trigger.Before orthogonal clock rising edge Qr 380, handle ACK (AckInst) signal 352, WAIT signal 360 and SLEEP signal 366, and shielding and ACT upgrade sequence (symbol 386-392) and occur in after the orthogonal clock rising edge Qr 380.
In order to understand the relevant operation that is performed, the renewal of ACT position is described as iterative processing (symbol 388-392).This operation is generally carried out simultaneously for all contexts.A trickle but very important action is to handle WAIT function 360 among Fig. 7 C, in the occurrence record of WAIT function 360 index of (prev) context (symbol 362) formerly here (this context was moved before major clock rising edge Mr 292 when deciphering WAIT function 360).In current (ctx) contextual index, finish the removing of ACT trigger (symbol 382-384) then.Before the orthogonal clock rising edge Qr 380 and under all situations afterwards, except context conversion is right after when taking place before major clock rising edge Mr 292, the value of prev and ctx equates.This means on the final cycle of context before the context conversion keeps activating of carrying out the WAIT function, but its WAIT trigger (waiting for the position in the bit string) equals 1 instruction after the WAIT function be moved and be carried out to that context can once more.Another interesting action is to send AckEv signal 356 to data routing when handling ACK function 352 among Fig. 7 C.Realize this feasible spinoff that when confirming a particular event, allows to finish in device or the host interface logic.
Fig. 7 D has defined each cycle second quadrant, the operation of Qr during the Mf cycle (cycle from orthogonal clock rising edge Qr to next major clock negative edge Mf).This is the time cycle when in a preferential order arranging incident and carrying out context conversion judgement.Possible the trying to be the first of first group of action (symbol 422-428) search.This search is as describing for the iterative processing of understanding the relevant operation that is performed.This operation is generally carried out simultaneously for all contexts.If the context of operation is on the foreground, search is at scope 0:ctx, if the context of operation be on the backstage then search at scope 0:7 because the contextual priority height in any backstage of contextual priority ratio, all foregrounds (symbol 423).Precedence level code lies in rising context several 424 (decline priority) sequence.If find an activation, the foreground context, its number is recorded in nctx (symbol 452).Otherwise, search (symbol 430-434) be directed being used for one start from representing when the AM/BAM context and proceed to the backstage context of the activation of higher context number (mould 8).
If timeslice (symbol 334 of Fig. 7 B) finishes at the major clock rising edge Mr 292 in this cycle, then Biao Shi curBg will increase progressively, if mean that search will begin in the context after the current context of moving and will only reselect identical context without any other contexts at the state Qb that arranges.Under the situation that the context of trying to be the first in background operation state Rb can be restarted now, this detection (symbol 430) will be withdrawn into one group of new context number (nctx) 450 at once.If a context operation is found in foreground (symbol 452) or backstage (symbol 450) search, new context number (nctx) is compared (symbol 454) need to determine whether a context conversion with current context number (ctx).If do not need the context conversion, during this cycle, there are not other context control activation generation and controller to turn back to running status 458.
If require the context conversion, controller enters the Start-CSW state 456 that keeps input signal 462 and up to major clock negative edge Mf (symbol 460) takes place.Require CSW (symbol 474,476) then, and the loading (symbol 478) that starts next contextual preservation state asks to preserve current context state (symbol 480) simultaneously.More fully explain the storage reason of request of loading before below in conjunction with Fig. 8 and 9.
If there is not the context of activation, controller is preserved all input signals (symbol 440) and up to major clock negative edge Mf (symbol 438) is taken place, represent then idle condition 442 and actual enter idle condition 448 before request preserve current context state 446.Preserving the context state, will be first context of operation when idling cycle finishes because can not guarantee identical context.In fact, be transformed into idle condition 448 and be a kind of context conversions that separate, preserve (symbol 442-446) being transformed into idle period of time, loading (symbol 466-470) from the idle transition period from the conversion of idle condition 448.During idle condition, clock continues operation and incident continues to be sampled, and is not performed but instruct both not to be removed also.Yet processor keeps preparing working to incident during idle condition.
If use complementary metal oxide semiconductor (CMOS) (CMOS) or another kind of power consumption is very low or be that 0 treatment technology is realized processor basically, when circuit part does not have regularly or changes level, idle condition 448 provides distinctive power saving mode for most of processors, comprises sequencer, command decoder and data routing.If still require the lower-wattage operator scheme, SLEEP function 366 (among Fig. 7 C) can stop high-frequency clock, and hangs up event-monitoring, only stays the low frequency sleep timer in operation.
Forward Fig. 8 now to, sequential chart by the context conversion of the present invention's control is described, wherein current contextual state storage is to synchronous (self-timing) SRAM or register file, and next contextual state loads from synchronous (self-timing) SRAM or register file.The sequential chart of describing (in Fig. 8 and 9) shows the difference of requirement use in one of two kinds of different kinds of memory technology of storing the contextual executing state of inoperative.Context is stored in the register set separately.Some processor structures are supported many physical registers collection, on thereunto the logic register of remapping when convert task.On the other hand, primary memory part can be used for storage register content in the group of separating.
Each has advantage in these timing sequences, and promptly the context conversion operations does not need the extra cycle to preserve and recovers the context executing state, but realizes this function simultaneously with the execution of the contextual final injunction of changing.In order to use this technology, processor data-path should comprise each register that special-purpose register file or static RAM (SRAM) (SRAM) array are used for executing state.Can use explanation embodiment of the present invention in conjunction with the processor data-path that this storage is not provided.Yet, because in order to preserve and recover the execution of possible additional cycles of context executing state and extra-instruction, the conversion relevant with the context of sort processor has more overhead.
When using synchronous (self-timing) static RAM (SRAM) (SRAM) to realize storage array, obtain simple timing shown in Figure 8 and control signal sequence.This also is to handle the timing that is produced by direct realization according to the SDL that defines among Fig. 7.Though programmer's visible properties is identical, the asynchronous static RAM (SRAM) that is used for storage array requires complicated (as discussing in conjunction with Fig. 9) more.Suppose that synchronous SRAM has identical performance with the Asynchronous SRAM device, use synchronized sram method to allow short cycle length and lower power consumption, this is because the conversion of signals number that reduces and than the elimination of 50% of instruction cycletime short control signal duty factor.
SRAM writes at each and allows the forward position of pulse to catch write address and data synchronously, and uses the inner control signal that produces to finish write operation, and does not need stable input signal (except power supply) during the remainder of write cycle time.Utilize to use the synchronized sram integrated circuit of the register file cell of read port with absolute address and write port to obtain easily based on element, semi-custom.As shown in Figure 8, the control signal for the context conversion regularly becomes quite simple when using these synchronous SRAM elements to finish storage array.
Context controller 514 is used for the major clock rising edge Mr 517 sampling activation event signals of arrangement and gating synchronizing signal (time interval 532) at the first quartile in the cycle of permission during each instruction execution cycle 500,502.At orthogonal clock rising edge Qr 518, upgrade the needs that a context conversion is determined in all ACT triggers and precedence level code and compare operation, if next context (time interval 533) is selected in requirement.When activating with these context controllers, processor has been carried out 516 instructions that start at major clock rising edge Mr 517, and does not consider whether the context conversion needs during this instruction execution cycle.If processor data-path has the path by the combination of internal register source, it is considered to stable in the whole performance period, and then the value on these paths must be locked in major clock negative edge Mf 519 and read beginning (time interval 540) with what allow next contextual preservation state.On the other hand, be used to read the context state of storage, then do not require this locking if the processor deviser likes adding the overhead cycle.But, in most of the cases, if insert one or more cycles and these lockings are removed, net effect will be to handle and the slowing down of real-time response, and cause that one-period can not execute instruction between old contextual final injunction cycle and new contextual first instruction cycle.
At major clock negative edge Mf 519, the context controller can determine whether to need a context conversion (time interval 534), and if like this then require CSW signal 522.By the contextual context number of the next one is placed NCTX[2:0] dbjective state of indicating to be resumed on the sets of signals 530.Use NCTX[2:0] sets of signals 512 beginnings next contextual " store status " read (time interval 540) addressable storage array when finishing with current contextual final injunction, their context number remains on CTX[2:0] on the sets of signals 524.
When this context change-over period by major clock rising edge Mr 517 expression finishes (cycle 500 and cycle 502 separate), the current contextual executing state that is included in the output of generation during this performance period 500 is used CTX[2:0] sets of signals 510 stores with the addressable storage array.(time interval 522) is by major clock rising edge Mr 517 startup storage array write operations (time interval 542) when requiring CSW signal 508.
Owing to write synchronized sram useful characteristic, next contextual first instruction can get started execution (time interval 536), because do not write the address or the essential maintenance of data of storage array after the major clock rising edge Mr 517 of end period 500 takes place.Cycle length can not be in order normally to carry out, comprise the synchronous SRAM that writes recovery above 50% during the instruction cycle.Starting identical major clock rising edge Mr 517 conversions that SRAM writes also can be used for valuably with CSW signal 508 of negating and the CTX[2:0 that upgrades] sets of signals 510 finishes context and is transformed into new context several 526.
Forward Fig. 9 now to, the sequential chart with the context conversion of the present invention's control is described, wherein current contextual state storage is to Asynchronous SRAM or register file, and next contextual state loads from Asynchronous SRAM or register file.It is stable in the appropriate section of whole write cycle time that conventional or asynchronous SRAM requires write address and data.This retention time that needs a Time Created and after this edge, back, require a weak point sometimes before writing the back edge that allows pulse.The integrated circuit technique of many semi-custom can use Asynchronous SRAM that array ram or register file are provided, and this SRAM provides the individual address and the FPDP that can be used to read or write.Cao Zuo SRAM that separates and register file chip also can easily obtain by this way.
As shown in Figure 9, for use such routine, single port SRAM realizes storage array, regularly becomes complicated more for the control signal of context conversion.General timing is the same with Fig. 8, uses identical reference number to show similar part.The main NCTX[2:0 that is not both] generation of sets of signals 512, (as describing in detail in the time 522,528,530,534,535,537,540,541,543 of Fig. 9) is by context controller 514 and data routing 516 operations during the requirement of CSW signal 508 and and then.Suppose when storage and do not carry out any instruction when recovering a context state, must use Asynchronous SRAM, be no more than this cycle length and comprise that 25% during the instruction cycle of writing recovery is so that avoid the insertion in overhead cycle with the one-period time.This rate request is the twice of the same processor cycle rate when need using synchronous SRAM.(time interval 532,533,538) context conversion activation is identical between the preceding semiperiod of context change-over period.At the major clock negative edge Mf 519 of context change-over period, requiring CSW signal 508 (time interval 522) and NCTX[2:0] sets of signals 512 is set to next context number (time interval 534).Address and data message must be stable when the result of the final injunction that will be carried out by current context writes storage array.Therefore, have only one-period to can be used for reading (time interval 540) of next context store status from major clock negative edge Mf 519 to next orthogonal clock negative edge Qf 520.This exports best locked and maintenance during the one-period from orthogonal clock negative edge Qf 520 to next major clock rising edge Mr 517 then.So these lock values are sent to the work register (time interval 543) of processor valuably.At orthogonal clock negative edge Qf 520, NCTX[2:0] value of sets of signals 512 changes back current context number (time interval 535), and the current context state that allows to comprise this instruction (cycle 500) result is write storage array (time interval 541).At major clock rising edge Mr 517, NCTX[2:0] sets of signals 512 execution of changing back next context number (time interval 530) and next contextual first instruction begins (time interval 537).
Unlike SRAM realization synchronously, write operation is realized at major clock rising edge Mr 517.The request for utilization data routing result of Asynchronous SRAM quite early is exactly stable to allow writing storage array from orthogonal clock negative edge Qf 520 to the interim of major clock rising edge Mr 517.And during with synchronous SRAM, not needing the data routing result up to exactly before major clock rising edge Mr 517, this is convenient to shorten the instruction cycle and therefore accelerates and handles.
Forward Figure 10 now to, the synoptic diagram of a circuit embodiments is described, this circuit is applicable to realization event record, event mask, activates the incident affirmation of incident and the management of context activating position for each, comprise initialization requests and wait for the request logic, can understand the details of logout, shielding and affirmation in the context controller here better.
The general signal paragraph of representing " sheet " of a context controller affair logic is used to comprise the contextual ACT position relevant with this incident and the individual event of WAIT function logic.In this drawing, all logical signals are considered to require at " height " true (logical one) state.This signal paragraph is the explanation of affair logic embodiment and does not mean that it is actual restriction of the present invention.
Because event trigger D input 570 is hardware setting is true (being shown as being logical one), " non-" of event signal do not cancel this incident after event trigger 570 is set.If processor provides the instruction of SKPn as explanation embodiment, but event trigger output 570 can be by reading (describing as following) as the testing conditions in 1 in the state-event register 94 and the event condition sets of signals 596.Output by hardware reset 555 or AND door 572 is applied to removing event trigger 570 through OR door 574, their by " with " input added the execution of the ACK of event number (affirmations) function 554 hereto, the while this context move (signal 556).
From the suitable position of this context incident of contextual event mask register 94, event mask position 558 AND door 580 with event trigger output 570 by " with " and be applied to the input end of ACT trigger 590 through OR door 584.As will be described in further detail below, when the precedence level code of the context incident that realizes being used for the VECTOR function, also use the output of this AND door 580.From the event signal of the shielding of AND door 580 with from the event signal of the shielding of the every other incident relevant with this context together in OR door 584 by " or ", these signals comprise through the signals of AND door 582 from the out gate of waiting for logic.
The logical truth output condition of OR door 584 enables ACT trigger 590, allows ACT trigger 590 to be set on the output valve of NOT phase inverter 586 at orthogonal clock rising edge Qr 518.Output by using AND door 582 and anti-phase through the same signal of NOT phase inverter 586 can enable ACT trigger 590 D input.If require one or more activation incidents, ACT trigger 590 is provided with at orthogonal clock rising edge Qr 518, and does not carry out any WAIT function during the instruction cycle in front.ACT trigger 590 also can directly be set on this context by the execution of INIT function 588, and by hardware reset signal 555 direct zero clearings.ACT trigger output 590 is also used by the context prioritization logic and is anti-phase with zero clearing WAIT trigger 578 by NOT phase inverter 592.If in front during the instruction cycle no matter whether require any activation incident to carry out the WAIT function, then pass through NOT phase inverter 586 zero clearing ACT triggers 590.
Because context may be tried to be the first between the instruction after carrying out the WAIT function and carrying out the WAIT function, so need WAIT trigger 578.(this example occur in shown in Figure 2 53,54 and 58).When this context was moved (signal 556) simultaneously by AND door 576 decoding WAIT functions 557, WAIT trigger 578 allowed to be provided with at major clock rising edge Mr 517.Because context must be activated carrying out the WAIT function, this action record the generation of WAIT function remove the input of WAIT trigger 578 because negate through NOT phase inverter 592 in the output of the ACT of true state trigger 590.
At next orthogonal clock rising edge Qr 518, this context is at a running status (signal 556) at this moment, because the requirement of AND door output 582, ACT trigger 590 is cleared.If this context goes up and to be tried to be the first or by timeslice, will not move context in that the same instructions cycle boundary of WAIT trigger 578 (major clock rising edge Mr 517) is set.Therefore, the context run signal 556 of before next quadrature rising edge Qr 518, will negating, and ACT trigger 590 will keep being provided with.When this context restarts to move, ACT trigger 590 will cause that context becomes the orthogonal clock rising edge Qr 518 of nonactivated first instruction cycle and is cleared after carrying out such instruction.ACT trigger output 590 is through the NOT phase inverters 592 zero clearing WAIT trigger 578 of negating.
Forward Figure 11 now to, illustrate according to one embodiment of present invention about the field of the machine instruction of communication and position distribution between context control and the context in the instruction group.The details of instruction decode and code field is directly not related with the present invention, and this figure is mainly used in the description operation digital section, the information that this field provides the context controller to need.
Use SKPx instruction 600 detections of finishing most effectively at context state-event register 94 metas.These instructions are finished the detection under shielding or are finished " condition group " (C group) 604 of the regulation of eight coherent signals and be included in comparing by turn between eight bit mask values 605 in the instruction word.If by detecting operation 603 defined terms is genuine, then skip SKPx instruction afterwards.Relevant with the present invention is C group 01, " EVENTS " group 608, and it is not subjected to the influence of event mask and detects the content of the contextual state-event register 94 of operation.
Forward Figure 12 now to, the potential source that is used to produce control store address on the processor according to one embodiment of present invention is described.The initialization vector address that is used for specific context initialization vector above-mentioned can be by forming being placed in the position, position 5 to 3 that comprises all address word of 0 seen in the inlet that is used for INIT instruction 666 as shown in figure 12 in the context digital section 625 of (Figure 11) INIT instruction 640.
Forward Figure 13 now to, the exemplary data structure figure that is used for according to one embodiment of present invention at the control store initialization vector is described.As directed, this embodiment uses one group of eight initialization vector 670-677, is positioned at four continuous word intervals, and control store address pattern 678 begins at control store address 0x0000.Select four words vector spacings because long a, absolute branch requires three words on this processor, and all require such branch probably except last (context 7) vectorial 677.Do not require that for context 7 any branch is useful, because context 7 is the unique contexts that are activated after hardware reset.
Therefore, the code of context 7 initialization vectors be used for after hardware reset initialization other context and be used to handle INIT function for context 7.The vectorial spacing of using on other processors can be selected with the mode that depends on embodiment.The content that is preferably in use initialization vector on some processors is as the address of realizing indirect branch through vector, rather than start program is carried out on vector address.As shown in figure 11 VECTOR instruction 610 is useful for the decoding based on the incident of priority that causes that context activates.
Forward Figure 14 now to, illustrate according to one embodiment of present invention by the vector instruction that is used on processor, arranging and decipher specific context activating position and describe the synoptic diagram that destination address produces by precedence.As mentioned above, VECTOR instruction 610 is useful for the decoding based on priority of the incident that causes the context activation.When being performed, this instruction is branched off into and is arranged in one of 690 1 groups of eight handling procedure 680-687 of control store vector table.
Regulation vector table base address 613 in ten lowest orders of VECTOR instruction word 610.By precedence level code context state-event register 94 " with " context event mask register 90 selects a specific vector.Then, the event number 694 of use generation is carried out as the continuation that begins of one group of 0 692 eight word processor position 680-687 that cause in the non-masked event that is assigned to limit priority (minimum number) requirement in the position 3 to 0, position of positions 6 to 4, position and vector address 678 (as Figure 13 finding).Because VECTOR shown in Figure 11 instruction 610 is generally used soon, have reason to expect that at least one non-masked event trigger is genuine (equaling 1) after the activation again that follows WAIT instruction 654 closely.If not this situation, context will can not become activation.Yet, might be under situation about being set up without any event bit in the base address+64 words 688 comprise a vector.
For the instruction group of current embodiment, the vectorial spacing of these eight words allows many handling procedures not require when handling this incident fully in the vector table scope in branch.For the embodiment that such vectorial decoding function is provided, because handling procedure is regional than general require much longer, can select spacing making the entire process package be fit to vector table and staying a kind of balance of acquisition between sizable untapped control store amount.
From as can be known top, obviously the invention provides a kind of method that is used for context controller and this controller of operation of management processor multitasking.In one embodiment, the context controller comprises: (1) foreground task controller, according to priority with in response to the context of incident activation corresponding to foreground task, and (2) background task controllers, with the cooperation of foreground task controller, it submits to available processor resource and carries out circularly corresponding to the context that activates background task when the context carried out corresponding to foreground task.
Though described the present invention in detail, it should be appreciated by those skilled in the art that they can make various variations, replacement and change here and not deviate from the spirit and scope of the present invention with form the most widely.
Claims (22)
1. context controller that is used for the management processor multitasking comprises:
A foreground task controller according to priority and in response to incident, activates the context corresponding to foreground task; And
A background task controller with the cooperation of described foreground task controller, submits to the described contextual activation corresponding to described foreground task, activates the context corresponding to background task circularly.
2. context controller as claimed in claim 1, wherein the software transition status distinguishes described foreground task and described background task.
3. context controller as claimed in claim 1, wherein said incident is selected from the group of following formation:
External event, and
Internal event.
4. context controller as claimed in claim 1, wherein said background task controller is according to the described context of the instruction number activation of being carried out by each described background task corresponding to background task.
5. context controller as claimed in claim 1, wherein said context are stored in the register set separately.
6. context controller as claimed in claim 1, wherein described context controller places idle condition with described processor when all described foreground tasks and described background task are non-activation.
7. context controller as claimed in claim 1, but wherein said foreground task controller is applicable to the context of activation corresponding to a specific foreground task by turning to a software select storage unit.
8. the method for multitasking in the management processor comprises step:
According to priority and in response to incident, activate context corresponding to foreground task; And
Obedience activates the context corresponding to background task circularly corresponding to the described contextual activation of described foreground task.
9. method as claimed in claim 8 also comprises the step that described foreground task and described background task are distinguished.
10. method as claimed in claim 8, wherein said incident is selected from the group of following formation:
External event, and
Internal event.
11. method as claimed in claim 8, wherein the described step that activates circularly comprises according to the described contextual step of the instruction number activation of being carried out by each described background task corresponding to background task.
12. method as claimed in claim 8 also is included in the described contextual step of register centralized stores separately.
13. method as claimed in claim 8 also comprises the step that described processor is placed idle condition when all described foreground tasks and described background task are non-the activation.
14. method as claimed in claim 8, but the contextual described step that wherein activates corresponding to described foreground task comprises by turning to the contextual step of software select storage unit activation corresponding to specific foreground task.
15. a processor comprises:
A command decoder, its decoding receive described processor and corresponding to the instruction of a plurality of tasks;
A plurality of register set corresponding to described a plurality of tasks, comprise and want operated operand.
Carry out core for one, be connected to described command decoder and described a plurality of register set, its carries out all instructions corresponding to an activate a task in described a plurality of tasks to operate all in described all operands; And
A context controller is connected to described command decoder and described execution core, and its management comprises about the multitasking of described a plurality of tasks:
A foreground task controller, according to priority and in response to incident its activate corresponding to described a plurality of are all contexts of all of task of all foreground tasks of appointment, and
A background task controller with the cooperation of described foreground task controller, is obeyed the described all contextual activation corresponding to described all foreground tasks, activate circularly corresponding to described a plurality of are all contexts of all of task of all background tasks of appointment.
16. processor as claimed in claim 15, wherein the software transition status distinguishes described foreground task and described background task.
17. processor as claimed in claim 15, wherein said incident is selected from the group of following formation:
External event, and
Internal event.
18. processor as claimed in claim 15, wherein according to the instruction number of being carried out by each described background task, described background task controller activates the described context corresponding to background task.
19. processor as claimed in claim 15, wherein said context are stored in the register set separately.
20. processor as claimed in claim 15, wherein described context places idle condition with described processor when all described foreground tasks and described background task are non-activation.
21. processor as claimed in claim 15, but wherein by turning to the described foreground task controller of software select storage unit to be applied to activate context corresponding to specific foreground task.
22. processor as claimed in claim 15, wherein said processor forms the part of multi-purpose computer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US7745498P | 1998-03-10 | 1998-03-10 | |
| US21398398A | 1998-12-17 | 1998-12-17 | |
| US09/213983 | 1998-12-17 | ||
| US60/077454 | 1998-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1245921A true CN1245921A (en) | 2000-03-01 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99103958 Pending CN1245921A (en) | 1998-03-10 | 1999-03-10 | Event-driven and cyclic context controller and its application processor |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0942366A2 (en) |
| JP (1) | JPH11296385A (en) |
| CN (1) | CN1245921A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104699218A (en) * | 2013-12-10 | 2015-06-10 | 华为终端有限公司 | Task management method and equipment |
| CN108235757A (en) * | 2017-12-22 | 2018-06-29 | 深圳前海达闼云端智能科技有限公司 | A kind of method, apparatus and electronic equipment of operating system screen locking |
| CN108469985A (en) * | 2013-12-31 | 2018-08-31 | 华为终端（东莞）有限公司 | A kind of management method and equipment of application program |
| CN110457071A (en) * | 2018-05-08 | 2019-11-15 | 罗伯特·博世有限公司 | Method and apparatus for activating the task in operating system |
| CN114610472A (en) * | 2022-05-09 | 2022-06-10 | 上海登临科技有限公司 | Multi-process management method in heterogeneous computing and computing equipment |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901507B2 (en) * | 2001-11-19 | 2005-05-31 | Intel Corporation | Context scheduling |
| US6874080B2 (en) | 2001-11-19 | 2005-03-29 | Intel Corporation | Context processing by substantially simultaneously selecting address and instruction of different contexts |
| EP1805603A4 (en) * | 2004-08-19 | 2009-08-05 | Copernic Technologies Inc | Idle cpu indexing systems and methods |
-
1999
- 1999-03-02 EP EP19990301550 patent/EP0942366A2/en not_active Withdrawn
- 1999-03-10 CN CN 99103958 patent/CN1245921A/en active Pending
- 1999-03-10 JP JP6412699A patent/JPH11296385A/en not_active Abandoned
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104699218A (en) * | 2013-12-10 | 2015-06-10 | 华为终端有限公司 | Task management method and equipment |
| WO2015085887A1 (en) * | 2013-12-10 | 2015-06-18 | 华为终端有限公司 | Task management method and device |
| CN104699218B (en) * | 2013-12-10 | 2019-04-19 | 华为终端（东莞）有限公司 | A kind of task management method and equipment |
| US10345890B2 (en) | 2013-12-10 | 2019-07-09 | Huawei Device Co., Ltd. | Task management method and device |
| US11209894B2 (en) | 2013-12-10 | 2021-12-28 | Huawei Device Co., Ltd. | Task management method and device |
| US11662802B2 (en) | 2013-12-10 | 2023-05-30 | Huawei Device Co., Ltd. | Task management method and device |
| CN108469985A (en) * | 2013-12-31 | 2018-08-31 | 华为终端（东莞）有限公司 | A kind of management method and equipment of application program |
| CN108235757A (en) * | 2017-12-22 | 2018-06-29 | 深圳前海达闼云端智能科技有限公司 | A kind of method, apparatus and electronic equipment of operating system screen locking |
| CN110457071A (en) * | 2018-05-08 | 2019-11-15 | 罗伯特·博世有限公司 | Method and apparatus for activating the task in operating system |
| CN114610472A (en) * | 2022-05-09 | 2022-06-10 | 上海登临科技有限公司 | Multi-process management method in heterogeneous computing and computing equipment |
| CN114610472B (en) * | 2022-05-09 | 2022-12-02 | 上海登临科技有限公司 | Multi-process management method in heterogeneous computing and computing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0942366A2 (en) | 1999-09-15 |
| JPH11296385A (en) | 1999-10-29 |
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