CN1245739C - Method for forming grid electrode of semiconductor - Google Patents
Method for forming grid electrode of semiconductor Download PDFInfo
- Publication number
- CN1245739C CN1245739C CN 02132233 CN02132233A CN1245739C CN 1245739 C CN1245739 C CN 1245739C CN 02132233 CN02132233 CN 02132233 CN 02132233 A CN02132233 A CN 02132233A CN 1245739 C CN1245739 C CN 1245739C
- Authority
- CN
- China
- Prior art keywords
- layer
- conductor layer
- density plasma
- substrate
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a method for forming grid electrodes of semiconductors. A stack structure which comprises a conductor layer and a top cover layer is formed on a substrate, and then, a high-density plasma dielectric layer is formed on the substrate and is exposed out of the top cover layer, wherein the top of the high-density plasma dielectric layer is higher than the top of the conductor layer. Subsequently, the top cover layer is removed, since the top of the high-density plasma dielectric layer is higher than the top of the conductor layer, a dent is formed on the conductor layer. The side wall of the dent forms an oxidation gap wall, and the other conductor layer which covers the dent is deposited on the substrate, so the conductor layer and the originally-formed conductor layer are connected to form the grid electrode of a semiconductor device.
Description
Technical field
The present invention is the formation method of relevant a kind of semiconductor device, and particularly relevant for a kind of method that forms grid electrode of semiconductor.
Background technology
Have in the semiconductor fabrication process at present and a kind ofly need not carry out cmp (chemicalmechanical polishing, be called for short CMP) as the grid production method of planarization manufacture craft because possess than environmental protection and advantage cheaply, and gazed at gradually.The method of this making grid electrode of semiconductor mainly is to utilize the cap layer (cap layer) that is formed on the grid, and the high-density plasma that is deposited at the bottom of the ligand (high density plasma, be called for short HDP) oxide layer, remove part high-density plasma oxide layer up to exposing cap layer with hydrogen fluoride (HF) then, utilize the step of removing cap layer again, high-density plasma oxide layer unnecessary on the grid is removed in the lump, and obtained to have flat surfaces high-density plasma oxide layer.And, after the dimensions of semiconductor devices miniaturization, in order to keep raceway groove (channel) width, it is extremely narrow that the grid live width will become, therefore need on grid, form in a big way a polysilicon layer again as the top of grid, in order to by increasing manufacture craft nargin that gate upper surface guarantees follow-up manufacture craft and reducing resistance.
Yet, the method of above-mentioned formation grid electrode of semiconductor is but easily because the interface between high-density plasma oxide layer and grid has defective (defect), and the danger that runs through substrate is arranged when in a big way grid top of follow-up formation, cause single position (single bit) fault, and then influence its reliability (reliability).And, after semiconductor device develops towards miniaturization, in order to reach the purpose that increases gate upper surface and reduction of device size simultaneously, must shorten the distance between two grids as far as possible, so device fault that generation is caused because of misalignment (mis-alignment) in follow-up little shadow manufacture craft easily, and then reduction grid coupling efficiency (gate coupling ratio is called for short GCR).
Summary of the invention
Purpose of the present invention is providing a kind of method that forms grid electrode of semiconductor, with the single position fault that prevents to be caused because of the interface defective between high-density plasma dielectric layer and the polysilicon gate.
A further object of the present invention is providing a kind of method that forms grid electrode of semiconductor, to prevent reliability issues (issue).
Another object of the present invention is providing a kind of method that forms grid electrode of semiconductor, to increase grid coupling efficiency.
Another purpose of the present invention is providing a kind of method that forms grid electrode of semiconductor, when grid being carried out little shadow manufacture craft to enlarge to wrong nargin (window).
According to above-mentioned and other purpose, the present invention proposes a kind of method that forms grid electrode of semiconductor, is included in and forms the stack architecture that comprises one deck conductor layer and one deck cap layer (cap layer) in the substrate earlier.Then, form one deck high-density plasma dielectric layer and expose cap layer in substrate, wherein the high-density plasma dielectric layer top is higher than the conductor layer top.Subsequently cap layer is removed, because the high-density plasma dielectric layer top is higher than the conductor layer top, so after removing cap layer, can on conductor layer, form a recess.Then, form the oxidation clearance wall in the recess sidewall, the conductor layer of another layer of deposition covering recess in substrate makes itself and the conductor layer that has been formed at before under it link the grid that becomes semiconductor device again.
The present invention is by formed oxidation clearance wall on the conductor layer recess sidewall, completely cut off high-density plasma dielectric layer and the interface of polysilicon gate interpolar and extraneous contacting, so can avoid the single position fault that caused because of the interface defective between high-density plasma dielectric layer and the polysilicon gate, and then prevent the problem of reliability, to increase grid coupling efficiency.In addition because formed oxidation clearance wall has stopped the segment conductor layer on the conductor layer recess sidewall, so the present invention can enlarge when grid carried out little shadow manufacture craft to wrong nargin.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process profile according to the floating boom utmost point of the flash memory of the present invention one first embodiment;
Fig. 2 A to Fig. 2 E is the manufacturing process profile according to the floating boom utmost point of the flash memory of the present invention one second embodiment.
Label declaration
100,200: substrate
102,114,114a, 114b, 202,214,214a, 214b: conductor layer
104,204: cap layer
106,206: high-density plasma dielectric layer
108,208: recess
110,110a, 210: oxide layer
112: the patterning photoresist layer
210a: oxidation clearance wall
Embodiment
First embodiment
The present invention is a kind of method that forms grid electrode of semiconductor, mainly is by a kind of embedded oxidation clearance wall (buried oxide spacer), solves the defective of high-density plasma (high densityplasma is called for short HDP) dielectric layer.And the present invention can be widely used in the various semiconductor fabrication process that comprise grid electrode of semiconductor, such as the manufacture craft of mask-type ROM (maskROM), flash memory (FLASH memory) or embedded type bit line (buried bit line) etc., and following embodiment is the floating boom utmost point (floating gate) the formation method in the flash memory.
Figure 1A to Fig. 1 E is the manufacturing process profile according to the floating boom utmost point of the flash memory of the present invention one first embodiment.
Please refer to Figure 1A, in a substrate 100, form the stack architecture that comprises one deck conductor layer 102 and one deck cap layer (cap layer) 104, wherein the material of conductor layer 102 is polysilicon (polysilicon) for example, and the material of cap layer 104 is silicon nitride (Si for example
3N
4), and between substrate 100 and conductor layer 102, also comprise a tunnel oxide (not illustrating).Then, in substrate 100, form one deck high-density plasma dielectric layer 106 and expose cap layer 104, wherein high-density plasma dielectric layer 106 tops are higher than conductor layer 102 tops, and its material is high-density plasma oxide layer (HDP oxide layer) for example.And the step that forms high-density plasma dielectric layer 106 for example is to form a high-density plasma dielectric layer earlier to cover whole top cover layer 104 in substrate 100, utilize hydrogen fluoride (HF) to remove the part high-density plasma dielectric layer again, to expose cap layer 104.
Then, please refer to Figure 1B, cap layer 104 (please refer to Figure 1A) is removed, wherein remove the method for silicon nitride cap layer 104 and for example utilize hot phosphoric acid (H
3PO
4) remove.Because high-density plasma dielectric layer 106 tops are higher than conductor layer 102 tops,, can on conductor layer 102, form a recess 108 so remove after the cap layer 104.Subsequently, form layer of oxide layer 110 and cover recess 108 in substrate 100, wherein oxide layer 110 is the high-density plasma oxide layer for example.
Subsequently, please refer to Fig. 1 C, in substrate 100, form one deck patterning photoresist layer 112, and as etching mask oxide layer 110 is carried out etching, exposing conductor layer 102, and keep the oxide layer 110a of recess 108 sidewalls with it.
Then, please refer to Fig. 1 D, patterning photoresist layer 112 is removed, in substrate 100, deposit another layer conductor layer 114 again, cover recess 108 and oxide layer 110a, make this conductor layer 114 and conductor layer 102 bindings that are positioned under it become the floating boom utmost point of flash memory cell, and reach the effect that increases floating boom utmost point upper surface, wherein the material of conductor layer 114 is a polysilicon for example.
Afterwards, please refer to Fig. 1 E, can also comprise definition conductor layer 114, forming several parts, be and be positioned at the floating boom utmost point that conductor layer 102 under it connects to a flash memory cell as the part conductor layer 114a in the icon; Another part conductor layer 114b then can become the floating boom utmost point of another flash memory cell.Especially after semiconductor device develops towards miniaturization,, must shorten the distance between two internal memories in order to reach the purpose that increases floating boom utmost point upper surface and reduction of device size simultaneously as far as possible.And the present invention is because have the protection of oxide layer 110a; shown in Fig. 1 E; so definition during conductor layer 114 will be to wrong nargin (mis-alignment window) obviously greater than known technology; thus; the grid coupling efficiency of the formed floating boom utmost point according to the present invention (gatecoupling ratio is called for short GCR) also will increase.
Second embodiment
Fig. 2 A to Fig. 2 E is the manufacturing process profile according to the floating boom utmost point of the flash memory of the present invention one second embodiment.
Please refer to Fig. 2 A, in a substrate 200, form the stack architecture that comprises one deck conductor layer 202 and one deck cap layer 204, wherein conductor layer 202 for example is that polysilicon layer, cap layer 204 are silicon nitride layers for example, and also comprises a tunnel oxide (not illustrating) between substrate 200 and conductor layer 202.Then, form one deck high-density plasma dielectric layer 206 and expose cap layer 204 in substrate 200, wherein high-density plasma dielectric layer 206 tops are higher than conductor layer 202 tops, and its material is the group that is selected from silica for example.
Then, please refer to Fig. 2 B, utilize as hot phosphoric acid cap layer 204 (please refer to Fig. 2 A) is removed.Because high-density plasma dielectric layer 206 tops are higher than conductor layer 202 tops, so after removing cap layer 204, on conductor layer 202, can form a recess 208.Subsequently, forming in this way in substrate 200, the oxide layer 210 of high-density plasma oxide layer covers recess 208.
Subsequently, please refer to Fig. 2 C, oxide layer 210 is carried out an etch-back manufacture craft (etchback process), forming oxidation clearance wall 210a in recess 208 sidewalls, and expose conductor layer 202.
Then, please refer to Fig. 2 D, another layer of deposition conductor layer 214 covers recess 208 and oxidation clearance wall 210a in substrate 200, wherein the material of conductor layer 214 is a polysilicon for example, in order to connecting to the floating boom utmost point of a flash memory cell, and reach the effect that increases floating boom utmost point upper surface with the conductor layer 202 that is positioned under it.
Afterwards, please refer to Fig. 2 E, can also define 214 one-tenth several parts of conductor layer, be and be positioned at the floating boom utmost point that conductor layer 202 under it connects to a flash memory cell as the part conductor layer 214a in the icon; Another part conductor layer 214b then becomes the some of the floating boom utmost point of another flash memory cell.Particularly after semiconductor device develops towards miniaturization; in order to reach the purpose that increases floating boom utmost point upper surface and reduction of device size simultaneously; must shorten the conductor layer 214a of the two floating boom utmost points and the distance between the 214b as far as possible; and the present invention is because there is the protection of oxidation clearance wall 210a, thus during definition conductor layer 214 will be to wrong nargin obviously greater than known technology.
In sum, feature of the present invention comprises:
1. the present invention utilizes formed oxidation clearance wall on the conductor layer recess sidewall, completely cut off high-density plasma dielectric layer and the interface of polysilicon gate interpolar and extraneous contacting, so can avoid single position (single bit) fault of being caused because of the interface defective between high-density plasma dielectric layer and the polysilicon gate, and then prevent the generation of reliability issues.
2. work as the present invention because the oxidation clearance wall has stopped the segment conductor layer, so the present invention can enlarge to definition little shadow manufacture craft that grid carried out to wrong nargin, and reach the purpose that increases floating boom utmost point upper surface and reduction of device size simultaneously, and then increase grid coupling efficiency.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claims.
Claims (12)
1, a kind of method that forms grid electrode of semiconductor is characterized in that: comprising:
In a substrate, form the stack architecture that comprises one first conductor layer and a cap layer;
Form a high-density plasma dielectric layer in this substrate, expose this cap layer, wherein the top of this high-density plasma dielectric layer is higher than the top of this first conductor layer;
Remove this cap layer, on this first conductor layer, to form a recess;
Form an oxidation clearance wall in this recess sidewall;
Deposition one second conductor layer covers this recess in this substrate, and this second conductor layer and this first conductor layer are connected.
2, the method for formation grid electrode of semiconductor as claimed in claim 1 is characterized in that: wherein the material of this first conductor layer and this second conductor layer comprises polysilicon.
3, the method for formation grid electrode of semiconductor as claimed in claim 1 is characterized in that: wherein the material of this cap layer comprises silicon nitride.
4, the method for formation grid electrode of semiconductor as claimed in claim 3 is characterized in that: the step of wherein removing this cap layer comprises utilizes hot phosphoric acid to remove.
5, the method for formation grid electrode of semiconductor as claimed in claim 1 is characterized in that: wherein the material of this high-density plasma dielectric layer comprises the high-density plasma oxide layer.
6, the method for formation grid electrode of semiconductor as claimed in claim 5 is characterized in that: wherein form the step of this high-density plasma dielectric layer in this substrate, comprising:
In this substrate, form a high-density plasma dielectric layer, cover this cap layer;
Utilize hydrogen fluoride to remove this high-density plasma dielectric layer of part, to expose this cap layer.
7, a kind of method that forms the floating boom utmost point of flash memory is characterized in that: comprising:
In a substrate, form the stack architecture that comprises one first conductor layer and a cap layer;
Form a high-density plasma dielectric layer in this substrate, expose this cap layer, wherein the top of this high-density plasma dielectric layer is higher than the top of this first conductor layer;
Remove this cap layer, on this first conductor layer, to form a recess;
In this substrate, form an oxide layer, to cover this recess;
Define this oxide layer, exposing this first conductor layer, and keep this oxide layer of part that is positioned at this recess sidewall;
Deposition one second conductor layer covers this recess in this substrate, and this second conductor layer and this first conductor layer are connected; And
Define this second conductor layer, to form a plurality of floating boom utmost points.
8, the method for the floating boom utmost point of formation flash memory as claimed in claim 7 is characterized in that: wherein the material of this first conductor layer and this second conductor layer comprises polysilicon.
9, the method for the floating boom utmost point of formation flash memory as claimed in claim 7, it is characterized in that: wherein the material of this cap layer comprises silicon nitride.
10, the method for the floating boom utmost point of formation flash memory as claimed in claim 9 is characterized in that: the step of wherein removing this cap layer comprises utilizes hot phosphoric acid to remove.
11, the method for the floating boom utmost point of formation flash memory as claimed in claim 7, it is characterized in that: wherein the material of this high-density plasma dielectric layer comprises the high-density plasma oxide layer.
12, the method for the floating boom utmost point of formation flash memory as claimed in claim 11 is characterized in that: wherein form the step of this high-density plasma dielectric layer in this substrate, comprising:
In this substrate, form a high-density plasma dielectric layer, cover this cap layer;
Utilize hydrogen fluoride to remove this high-density plasma dielectric layer of part, to expose this cap layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02132233 CN1245739C (en) | 2002-09-03 | 2002-09-03 | Method for forming grid electrode of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02132233 CN1245739C (en) | 2002-09-03 | 2002-09-03 | Method for forming grid electrode of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1480987A CN1480987A (en) | 2004-03-10 |
| CN1245739C true CN1245739C (en) | 2006-03-15 |
Family
ID=34145132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02132233 Expired - Fee Related CN1245739C (en) | 2002-09-03 | 2002-09-03 | Method for forming grid electrode of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1245739C (en) |
-
2002
- 2002-09-03 CN CN 02132233 patent/CN1245739C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1480987A (en) | 2004-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7259067B2 (en) | Method for manufacturing flash memory device | |
| US20050062095A1 (en) | Structure and fabricating method to make a cell with multi-self-alignment in split gate flash | |
| CN101859777A (en) | Structure and fabricating process of non-volatile memory | |
| CN1245739C (en) | Method for forming grid electrode of semiconductor | |
| CN1324693C (en) | Manufacturing method of flash memory | |
| CN107731730B (en) | Method for forming semiconductor structure | |
| CN1905133A (en) | Method for forming floating gate electrode in flush memory device | |
| KR100824630B1 (en) | Semiconductor device having spacer patterns on the sidewalls of the gate pattern and method of fabricating the same | |
| CN1649095A (en) | Method for forming a contact of a semiconductor device | |
| CN1275322C (en) | Manufacturing method of read only memory | |
| KR100554834B1 (en) | Method of manufacturing flash memory device | |
| CN1992174A (en) | Method for manufacturing flash memory cell | |
| CN1271707C (en) | Manufacturing method of flash storage having separated floating grid and its structure | |
| CN100346471C (en) | Flash memory storing element and method for making same | |
| CN1299353C (en) | Manufacturing method of flash memory | |
| CN1264212C (en) | Flash memory and its manufacture | |
| CN1286164C (en) | Method of making memory element having a self-aligning contacting window and structure thereof | |
| CN1302553C (en) | Separation grid flash storage unit and its manufacturing method | |
| CN117976619A (en) | Method for forming air gap in interconnection layer | |
| CN1287422C (en) | Method for forming contact window with sphering corner and semiconductor structure | |
| CN1279618C (en) | Flash memory unit with selective grid positioned in substrate and its making method | |
| CN1156895C (en) | Manufacture of floating grid for quick-erasing memory unit | |
| CN115472615A (en) | Flash memory and manufacturing method thereof | |
| CN1294643C (en) | Method for forming clearance wall between grid and capacitor | |
| CN1290159C (en) | Gate manufacture and structure of embedded memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060315 Termination date: 20190903 |