CN1242568C - Receiving device and signal receiving method - Google Patents
Receiving device and signal receiving method Download PDFInfo
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- CN1242568C CN1242568C CN 98109758 CN98109758A CN1242568C CN 1242568 C CN1242568 C CN 1242568C CN 98109758 CN98109758 CN 98109758 CN 98109758 A CN98109758 A CN 98109758A CN 1242568 C CN1242568 C CN 1242568C
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Abstract
The present invention relates to a receiving device and the object is to make the data conducted a high precision maximum likelihood sequence estimation and transmitted can be restored with further improved accuracy. Since the receiving means (31, 32) for outputting received signal (S27) upon receiving the transmission signal, the weighting means (35) for calculating the weight coefficient showing the reliability of slot by which said received signal is transmitted based on the received signal transmitted from the receiving means and multiplying this weight coefficient by the received signal and outputting it, and the decoding means (16) for decoding the received signal (S29) to be transmitted from the weighting means and restoring the data transmitted are provided, the maximum likelihood sequence estimation can be conducted upon adding the reliability of slot in the decoding means, and thereby, even in the case where the qualities of communications vary by slot, the transmitted data can be restored with further improved accuracy by conducting a high precision maximum likelihood sequence estimation.
Description
The present invention relates to a kind of receiving equipment and signal acceptance method, particularly may be used on the receiving equipment and the signal acceptance method of the wireless communication system such as mobile telephone system.
In such wireless communication system, regional portion that communication service is provided is divided into some mesh with requirement size and is provided as base station at fixing wireless station respectively and carries out radio communication as the base station that the portable telephone equipment of mobile radio station is arranged in the mesh that exists with this portable phone in each mesh.Though various types of communication systems have been proposed,, a kind of typical equipment is the time-division multiple address system that is called TDMA.
This tdma system be divide respectively pre-specified frequency channel for set time width F0, F1 shown in Figure 1A and 1B ... frame and further to divide frame be the time slot of set time width TS0 to TS1, with when utilizing a common frequency channel that time slot TS0 is distributed to his oneself station, the user sends this system of transmission signals makes realization multichannel communication (being multiplexed communications) become possibility, and each user shares a public frequency and frequency can effectively utilize.Distribute the time slot TS0 of transmission to be called time slot TX and will to be called time slot hereinafter by the data block that a sending time slots TX sends.
The transmitting apparatus and the receiving equipment of the wireless communication system that utilizes tdma system transmission and receiving digital signals are described with reference to Fig. 2 A, 2B, 3A and 3B below.About this, be illustrated in the portable telephone equipment and base station that transmitting apparatus among Fig. 2 A, 2B, 3A and the 3B and receiving equipment be arranged on mobile telephone system, and be used for communicating by letter from the portable telephone equipment to the base station or from the base station to the portable telephone equipment.
Shown in Fig. 2 A, transmitting apparatus 1 is made up of convolutional encoding circuit 2, interlace buffers 3, one-tenth time slot treatment circuit 4, difference quadrature phase shift keying (DQOSK) modulation circuit 5, transtation mission circuit 6 and antenna 7 roughly, at first, the transmission data S1 of transmission is input to convolutional encoding circuit 2.
Becoming time slot treatment circuit 4 to divide described transmission code element S3 be in each time slot, so as to distribute send code element S3 to each sending time slots TX neutralization sequentially each the time unoccupied place output branch time slot transmitted symbol S4 to DQOSK modulation circuit 5.DQOSK modulation circuit 5 applies the DQOSK modulation treatment by the transmission signal S4 that every time slot is presented, and forms the transmission code element S5 of the code element information of being represented by phase value and exports this signal to transtation mission circuit 6.
On the other hand, as shown in Figure 3A, receiving equipment 10 reconciles circuit 13, time slot connection processing circuit 14, deinterleave buffer 15 by antenna 11, receiving circuit 12, DQOSK roughly and Veterbi decoding circuit 16 is formed and import this signal to receiving circuit 12 by antenna 11 receptions from the transmission signal S6 of transmitting apparatus 1 transmission with as received signal S11.Receiving circuit 12 is after amplifying this receiving inputted signal S11, by described received signal S11 being applied frequency translation extracts baseband signal and by after this baseband signal is applied Filtering Processing, by the transform-based band signal is digital signal, extract the received signal S12 of DQOSK modulation and export this signal to DQOSK demodulator circuit 13.
But, in receiving equipment 10, carry out the maximum likelihood sequence estimation by Veterbi decoding circuit 16, recover the data S16 that receives.Yet for the data of recovering with high accuracy to receive, the efficient of further improving the maximum likelihood sequence estimation is that people expect.
This point will more specifically be described in the paragraph below.The receiving symbol S13 that presents from DQOSK demodulator circuit 13 is a multi-level signal as mentioned above.The value of this multi-level signal is represented the reliability of receiving symbol roughly.The such multi-level signal of Veterbi decoding circuit decoding generally is called soft decision Veterbi decoding circuit, and usually, when adding the reliability of each code element, this circuit is by carrying out maximum likelihood sequence estimation restore data.On the other hand, the decode Veterbi decoding circuit of binary value signal with " 1 " or "+1 " value generally is called hard decision Veterbi decoding circuit.When this hard decision Veterbi decoding circuit and soft decision Veterbi decoding circuit were compared, in general, described soft decision Veterbi decoding circuit can carry out higher precision maximum likelihood sequence estimation than hard decision Veterbi decoding circuit.Reason is under the situation of soft decision Veterbi decoding circuit, because the multi-level signal of reflection reliability is imported, can reflect the estimation of reliability.Therefore, in order to increase the precision of maximum likelihood sequence estimation, think that if the reliability of code element has been reflected to will be reasonable in the signal that is input to the Veterbi decoding circuit.
But under the situation of tdma system, receiving symbol sends after being divided into each time slot respectively and has communication quality and pursues the possibility that time slot changes.Therefore, in this case, think that then the maximum likelihood sequence estimation of Veterbi decoding circuit can carry out with higher precision if representing the value of the communication quality reliability of time slot is reflected in the described symbol value that sends by this time slot.Particularly, be when multi-slot carries out when interlocking, if do not reflect reliability, because reliability is with the time slot variation, so may carry out wrong estimation.
In view of top described, the objective of the invention is provides the receiving equipment and the signal acceptance method of the data that send of can decoding more accurately by carrying out high accuracy maximum likelihood sequence estimation.
Receive the method for reseptance that comprises one group of predetermined information cell signal by providing, above-mentioned purpose of the present invention and other purpose realize.This method of reseptance comprises received signal; Each predetermined information unit is calculated the weight coefficient of the reliability of expression received signal; By weight coefficient weighting received signal; The step of signal with the decoding weighting.
In addition, according to the present invention, the receiving equipment that is used to receive the signal that comprises one group of predetermined information unit comprises: the receiving system of received signal; Be used for each predetermined information unit is calculated the weight coefficient calculation element of expression from the weight coefficient of the reliability of receiving system output signal; Utilize the weighting device of weight coefficient weighting from the signal of receiving system output; Be used to decode from the decoding device of the signal of weighting device output.
According to the present invention, the method for reseptance that is used to receive the signal that is made of one group of predetermined information unit is provided, comprise step: receive described signal; Calculate one group of weight coefficient, this group each coefficient in weight coefficient corresponding to shown in the reliability of each information unit in one group of predetermined information unit; Utilize the weight coefficient of described correspondence to come each information unit in the described one group of predetermined information unit of weighting; With each information unit that is weighted in the described one group of predetermined information unit of decoding.
According to the present invention, the receiving equipment that is used to receive the signal that is made of one group of predetermined information unit is provided, comprising: the receiving system that is used to receive described signal; The weight coefficient calculation element is used to calculate one group of weight coefficient, and this group each coefficient in weight coefficient is corresponding to the reliability of each information unit from one group of predetermined information unit shown in the described receiving system output; Weighting device utilizes corresponding weight coefficient to come weighting each information unit from the described predetermined information unit of described receiving system output; And decoding device, be used for decoding from each information unit of described one group of predetermined information unit of described weighting device output.
When reading this specification in conjunction with the accompanying drawings, characteristic of the present invention, principle and purposes will become clearer from following detailed, and in each accompanying drawing, identical part is by identical label or character representation.
In each accompanying drawing:
Figure 1A and 1B are the principle schematic of explaining tdma system;
Fig. 2 A and 2B are the block diagrams of the transmitting apparatus of expression conventional wireless communication system;
Fig. 3 A and 3B are the block diagrams of the receiving equipment of expression conventional wireless communication system;
Fig. 4 is the block diagram according to the transmitting apparatus of the wireless communication system of one embodiment of the present of invention;
Fig. 5 is the block diagram of the receiving equipment of this wireless communication system of expression;
Fig. 6 is the block diagram of the random phase shift circuit of this transmitting apparatus of expression;
Fig. 7 is the block diagram of the anti-phase shift circuit at random of this receiving equipment of expression;
Fig. 8 is the block diagram of the demodulator circuit of expression receiving equipment;
Fig. 9 is the block diagram of the computing unit of this demodulator circuit of expression;
Figure 10 is the block diagram of the adjustment circuit of this counting circuit of expression;
Figure 11 explains the error ratio characteristic curve chart that compares between the situation that the reliability of the situation of reliability reflection of time slot and time slot do not reflect;
Figure 12 is the performance diagram that compares between the power signal-to-noise ratio S/N of the power signal-to-noise ratio S/N that explain to calculate and measurement;
Figure 13 is the block diagram of expression according to the demodulator circuit of second embodiment;
Figure 14 is the block diagram of expression according to the demodulator circuit of the 3rd embodiment;
Figure 15 is the block diagram of expression according to the computing unit of the demodulator circuit of the 3rd embodiment;
Figure 16 is the block diagram of expression according to the demodulator circuit of the 4th embodiment;
Figure 17 is the simple linear figure that explains the phase place of the receiving symbol of just going up quadrant that transforms to complex number plane when receiving symbol π/4 phase shifts;
Figure 18 is the phase place schematic diagram of explaining when being interfered wave action;
Figure 19 is the block diagram of expression according to the computing unit of the demodulator circuit of the 4th embodiment;
Figure 20 is the block diagram of expression according to the demodulator circuit of the 5th embodiment;
Figure 21 is the block diagram of expression according to the demodulator circuit of the 6th embodiment;
Figure 22 is the figure of expression picked up signal/interference noise power than the table of S/ (I+N);
Figure 23 is the block diagram of expression according to the demodulator circuit of the 7th embodiment;
Figure 24 is a schematic diagram of explaining receiving symbol when moving on to the I axle of complex number plane mutually;
Figure 25 is the schematic diagram of explaining under the situation that receives disturbing wave;
Figure 26 be the expression deviation value than RQ/I and signal/disturbing wave than the performance diagram that concerns between the S/I;
Figure 27 is the block diagram of expression according to the demodulator circuit of the 8th embodiment;
Figure 28 is that explanation is by calculating the performance diagram of the signal/noise power ratio S/N that obtains;
Figure 29 is a block diagram of representing the formation of computing unit in other embodiments;
Figure 30 is a block diagram of representing the demodulator circuit that constitutes in other embodiments;
Figure 31 is a block diagram of representing the transmitting apparatus of wireless communication system in other embodiments; With
Figure 32 is a block diagram of representing the receiving equipment of wireless communication system in other embodiments.
Each preferred embodiment of the present invention is described with reference to each accompanying drawing:
(1) first embodiment
The general structure of the wireless communication system of the present invention's application at first, is described with reference to Figure 4 and 5.In Fig. 4, represented with identical label with each parts that Fig. 2 A and 2B are corresponding, 20 generally represent the transmitting apparatus of the wireless communication system such as mobile telephone system, with this equipment have almost be illustrated in Fig. 2 A and 2B in the identical structure of transmitting apparatus, except increasing the random phase shift circuit.In this transmitting apparatus 20, be fed to DQPSK modulation circuit 5 from the transmission code element that becomes 4 outputs of time slot circuit.DQPSK modulation circuit 5 is to apply the DQPSK modulation treatment to form its code element information be to represent to send the circuit of signal with phase value by sending code element S4.Under the situation of this embodiment, produce π/4 phase shifts the DQPSK modulation treatment (that is, and by from before code element phase shift variations π/4, maximum phase shift variations is controlled to be ± 3 π/4).The transmission signal S5 that is formed by this processing is fed to random phase shift circuit 21.
Random phase shift circuit 21 takes advantage of input to send signal S5 by the phase data of utilizing every code element to produce at random continuously, applies random phase shift to sending signal S5.In this case, random phase shift circuit 21 is made up of random phase shift data generating circuit 21A and multiplier 21B as shown in Figure 6.Random phase shift data generating circuit 21A has an initial phase place value, this value by communication channel (for example is, in mobile telephone system, by the base station) change in advance and on the basis of a pre-defined rule, sequentially produce the phase data S22 of random phase value and this phase value of output expression to multiplier 21B from described initial phase place value.About this, this phase data S22 has the plural number of amplitude for the random phase value of " 1 ".The plural number of the transmission signal S5 of the CM input of the phase data S22 of multiplier 21B by utilizing every code element continuously carries out random phase shift to sending signal S5.Therefore, the transmission signal S20 that utilizes random phase shift to produce sends to transtation mission circuit 6.
The receiver side of communication is arranged to such an extent that have an initial phase place value identical with above-mentioned initial phase place value, and produces the phase data identical with transmitter side according to identical program.Recover to handle if this phase data of received signal is divided, then the signal before the additional random phase shift can recover.About this, received the transmission signal that adds this random phase shift if not certain side of the opposing party of communication, then he can not recover original signal, because he does not have identical initial phase place value.Therefore, if communication will be undertaken by the different initial phase place values of each communication channel utilization, even become the situation of disturbing wave, non-communication party's signal mutually in each communication, be disturbing wave, the phase place of these disturbing waves still is in stochastic regime and these disturbing waves and can looks and become half noise.
In addition according to this embodiment, transtation mission circuit 6 is carrying out Filtering Processing for after sending signal S20, the described transmission signal of conversion S20 is analog signal and sends signal by conversion frequency for simulation, formation has the transmission signal S21 of fixed frequency channel and is amplifying this signal after predetermined power, sends this signal by antenna 7.
Then, in Fig. 5 with Fig. 3 A and 3B in corresponding component provide with same numeral, label 30 general expressions are according to the receiving equipment of wireless communication system of the present invention, with except have receiving circuit 31, at random anti-phase shift circuit 32 and the demodulator circuit 33, this equipment has and the receiving equipment structure much at one that is illustrated among Fig. 3 A and the 3B.At first, antenna 11 receives from the transmission signal S21 of transmitting apparatus 20 transmissions with as received signal S25 and imports this signal to receiving circuit 31.This received signal S25 that receiving circuit 31 is presented in amplification is behind predetermined level, by being applied frequency translation, described received signal extracts baseband signal, with after this baseband signal is applied Filtering Processing, extract the received signal S26 by the described baseband signal additional phase shift of digitlization and export this signal to anti-phase shift circuit 32 at random.About this, under the situation of output received signal S26, the A/D conversion circuit of this receiving circuit 31 amplify this received signal make the power of each time slot become constant after, export this signal.According to this wireless communication system,, therefore might change by each time slot of signal power because signal exists the variation possibility of each time slot of the decline that receives by sending by time slot on transmission route.
For input received signal S26, anti-phase at random shift circuit 32 is by applying the division processing to representing with the phase data of transmitter side same phase value continuously, and the random phase shift that recovers the described received signal S26 of regulation is original phase shift.In fact, as shown in Figure 7, anti-phase at random shift circuit 32 is made of random phase data generating circuit 32A and multiplier 32B.Random phase data generating circuit 32A has the initial phase place value identical with transmitter side, the unalterable rules identical with transmitter side with basis produce the phase value identical with transmitter side and export the phase data S33 (" * " represents the relation of gripping altogether in the drawings) that the phase value of representing with multiplier 32B has the phase value of the relation of gripping altogether from described initial phase place value.About this, this phase data S33 has the plural number of the amplitude of the phase value of gripping altogether with the phase value that produces at transmitter side for " 1 ".Multiplier 32B is by by the CM of the phase data S33 of the every code element plural number with the received signal S26 of input, offsets to append to the phase change on the described received signal S26 and return to original phase condition.Therefore, if utilize phase data S33, then utilize multiplier 32B to replace divider can carry out anti-phase moving with the relation of gripping altogether with the phase data of transmitter side.
The received signal S27 that returns to original phase place by anti-phase shift circuit 32 at random is fed to demodulator circuit 33 then.Demodulator circuit 33 is made up of DQPSK conciliation circuit 34 and weighting circuit 35 and is imported received signal S27 respectively to DQPSK demodulator circuit 34 and weighting circuit 35.DQPSK demodulator circuit 34 applies the DQPSK demodulation process by S27 to received signal and extracts code element information and export this signal to weighting circuit 35 as receiving symbol S28.Weighting circuit 35 calculates the reliability of time slots, sends and calculate weight coefficient corresponding to this reliability according to the every time slot of received signal S by the described received signal S27 of this reliability.Then, weighting multichannel 35 multiply by receiving symbol S28 with weight coefficient, reflect this time slot reliability on the signal level of described receiving symbol S28 and the receiving symbol S29 that produces of output to time slot connection processing circuit 14.
Time slot connection processing circuit 14 is the circuit that connect receiving symbol S29, the receiving symbol S29 that makes segmentation obtain becomes continuous signal, during with the memory capacity of the deinterleave buffer 15 that is stored in last level as this receiving symbol S29, connect described receiving symbol S29 and export this code element S30 that is connected to deinterleave buffer 15.Deinterleave buffer 15 has the memory capacity that is used for multi-slot, with after storage is fed to the receiving symbol S30 of internal storage region continuously, the receiving symbol S31 that order that the order of the described receiving symbol S30 of process change that utilization is opposite with the change order that the interlace buffers 3 of transmitting apparatus 20 is carried out and recovery are original and output produce is to Veterbi decoding circuit 16.
That Veterbi decoding circuit 16 is made up of soft decision Veterbi decoding circuit and carry out the maximum likelihood sequence estimation by receiving symbol S31 to input, recover the reception data S32 of the data that expression sends.
In this case, in the weighting circuit 35 of prime, the reliability of the time slot that receiving symbol S28 calculating and receiving symbol S28 send multiply by the weight coefficient of the reliability of this time slot of expression.Therefore, become corresponding to the degree of the reliability of this time slot with in the situation that communication quality changes with time slot, be reflected in the signal level by the reliability communication quality even will be fed to the signal level of the receiving symbol S31 of Veterbi decoding circuit 16.Therefore, if such receiving symbol S31 may be input to Veterbi decoding circuit 16, then Veterbi decoding circuit 16 is under the situation of the reliability of having added every time slot, carry out the maximum likelihood sequence estimation, so the maximum likelihood sequence estimation can carry out and receive data and can recover with the further transmission that improves precision with higher precision.
Below, the structure of demodulator circuit 33 is more specifically described with reference to Fig. 8.As shown in Figure 8, in demodulator circuit 33, the received signal S27 of the formation complex signal of presenting from anti-phase shift circuit 32 at random is fed to the DQPSK decoding circuit of being made up of multiplier 40 and delay circuit 41.Multiplier 40 receive a code element of delay that sends from delay circuit 41 received signal S35 and by utilize a received signal S35 code element before grip the received signal S27 with input on duty, extraction receiving symbol S28 from described received signal S27 altogether.Handle the code element information that the receiving symbol S28 that extracts is the DQPSK modulation by this multiplying each other.This receiving symbol S28 is fed to then advanced person-go out buffer (fifo buffer hereinafter referred to as) 42 earlier and stores continuously.Fifo buffer 42 keeps receiving symbol S28, and until an add up time slot and when this code element adds up a time slot of this code element, described receiving symbol S28 is to the multiplier of following 43 in fifo buffer 42 outputs.
And the receiving symbol S28 that takes out by multiplier 40 also is fed to the temporary transient decision circuit of being made up of weight coefficient computing unit 52 44.This temporary transient decision circuit 44 is temporarily judged the phase state of receiving symbol S28, and at this moment phase state is that the complex signal of the 4 phase states of DQPSK and the output amplitude that to have the temporary transient phase state of judging of expression be " 1 " is to multiplier 45.The received signal S35 of a code element of delay that sends from delay circuit 41 is fed to multiplier 45, with described multiplier 45 utilize postpone a code element received signal S35 multiply by complex signal S36 from temporary transient decision circuit 44, constitute DQPSK modulation signal, i.e. the regenerated signal of received signal S27 according to temporary transient result of determination.Hereinafter, this signal is called the reproducing signals S37 with respect to original received signal S27.
The received signal S37 that duplicates that is made of multiplier 45 is fed to subtracter 46.In subtracter 46, received signal S27 originally also imports and subtracter 46 deducts from original received signal S27 and duplicates received signal S37 and output expression is subtracted each other result's signal component S38 to the first square-law circuit 47.In this case, if the result of determination of temporary transient decision circuit 44 is correct, when carrying out exploratory judgement, the noise component(s) that this signal component S38 becomes in the code element that is included in the signal of two noise component(s)s among the received signal S27 this moment and is included in the front received signal makes up.
The first square-law circuit 47 is by the amplitude of the noise component(s) of square each code element, and the power and this noise power of the output S39 that obtain the noise component(s) of each code element arrive adder 48.First adder 48 additions are from the noise power S39 of each code element of the first square-law circuit 47 output, obtain to add that the noise power S40 of a time slot of noise power of all code elements that constitute a time slot and this power of output are to calculator 49.
And the received signal S27 that presents from anti-phase shift circuit 32 at random also is fed to the second square-law circuit 50.The amplitude of the second square-law circuit 50 by square received signal S27 obtains the power of each code element of received signal S27 and this signal power of output S41 to second adder 51.This second adder 51 is by will be from the signal power S41 addition of each code element of the second square-law circuit 50 output, calculating add all code elements of forming a time slot signal power a time slot signal power S42 and export this power to calculator 49.About this, this signal power S42 represents that the signal power of received signal S27 and this power are the signal powers that actual signal component power and noise component(s) power make up.
At this moment, the structural table of computing unit 49 is shown in Fig. 9.Computing unit 49 comprises weight coefficient computational chart 49A and adjusts circuit 49B.Weight coefficient computational chart 49A is by having stored weighting coefficient table and stipulated that the memory of predefined parameter constitutes, can having read corresponding to the weight coefficient of described parameter.This weight coefficient is expression time slot reliability, the i.e. coefficient of the power ratio of the coefficient of communication quality and expression signal and noise.Adjust circuit 49B calculates the weight coefficient of reading according to noise power S40 that imports and signal power S42 parameter S P, with in weight coefficient computational chart 49A by the described parameter S P of regulation, read corresponding to the weight coefficient of parameter S P and this coefficient of output as weight coefficient S43.
Here, the structure of adjusting circuit 49B will be described in the paragraph below.As shown in figure 10, for example adjusting circuit 49B is made up of 1/2 circuit 49BA, division circuit 49BB and counting circuit 49BC.At first, as mentioned above because noise power S40 be two code elements noise power S39 and, noise power is that the twice of actual noise power is so big.Therefore, noise power S40 is fed to 1/2 circuit 49BA and with described noise power S40 in two, obtains actual noise power.This noise power is fed to division circuit 49BB and carries out division here and handle.Divider 49BB utilizes the noise power of signal power S42 divided by input, obtains the ratio of noise " N " to signal power " S ".In this case, because signal power S42 contains noise component(s), obtainable here signal noise ratio is N/ (S+N).About this, if used code element number is different with code element number used when the signal calculated power S42 when calculating noise power S40, then noise power S40 can code element number normalization and after utilizing code element number normalized signal power S42, can obtain noise to signal power N/ (S+N) ratio.
In this case, an expression of storage noise compares with respect to signal the table of noise power S/N than (this value is the value of estimating according to actual value) signal power N/ (S+N) in weight coefficient computational chart 49A, the noise that to present from divider 49BB with counting circuit 49BC hypothesis to signal power N/ (S+N) than being parameter S P, from weight coefficient computational chart 49A, read corresponding signal to noise power S/N than and export this coefficient as weight coefficient S43.About this, if temporary transient decision circuit 44 carries out mistake and temporarily judges, then the value of noise power S40 is lower than actual noise power, therefore, for the part that may be stored among the weight coefficient computational chart 49A, noise is proofreaied and correct the table of noise power S/N ratio signal power N/ (S+N) ratio and signal.
According to said structure, under the situation of receiving equipment 30, demodulator circuit 33 is carried out the temporary transient judgement of receiving symbol S28, duplicates received signal S27 according to temporary transient result of determination S36 and a symbol signal S27 receiving previously, constitutes the duplicate that duplicates received signal S37.And duplicate by extracting this received signal S37 and poor between the received signal S27 originally, obtain the noise component(s) S38 of each code element and obtain the noise power S40 of each time slot according to this.In addition, at the same time, obtain the signal power S42 of the time slot of original received signal S27.According to the noise power S40 and the signal power S42 of this acquisition, the expression signal that obtains this time slot multiplies each other to the weight coefficient S43 of noise power S/N ratio and this coefficient and receiving symbol S28.Carry out this operation by each time slot, the signal of this time slot than in the amplitude that is reflected to receiving symbol S28, therefore, forms the receiving symbol S29 of reflection time slot reliability to noise power S/N.If the receiving symbol S29 of this reflection time slot reliability is input in the Veterbi decoding circuit 16 via the deinterleave buffer 15 of time slot connection processing circuit 14 and last level, then described Veterbi decoding circuit 16 can carry out the data of maximum likelihood sequence estimation and reception and can decode with higher precision under the situation of the reliability of having added each time slot.
About this, the situation of the reliability of in Figure 11, expressing time slot by multiply by receiving symbol S28 reflection by a weight coefficient and the error rate of the received signal of reliability situation about not reflecting.Usage factor and this coefficient that expression system load in the drawings is illustrated in channel in this wireless communication system are proportional to disturbing wave power.From Figure 11, know and find out, when the time slot reliability is reflected among the receiving symbol S28, can more accurately recover to receive data.
And, under the situation of receiving equipment 30, because it is that a weight coefficient is stored in the weight coefficient computational chart 49 that the signal of time slot likens to noise power S/N, with according to noise power S40 and signal power S42, signal is read from table 49A noise power S/N ratio, and make this liken to and be weight coefficient S43, represent that correctly the weight coefficient S43 of the reliability of time slot utilizes simple structure easily to calculate.About this, according to noise power S40 and signal power S42 picked up signal to noise power S/N ratio with this is than being used as weight coefficient S43.But, as shown in figure 12, when signal to noise power S/N than being in poor state and when having introduced error, by calculate the signal that obtains to noise power S/N than inconsistent with actual value.Yet, by to this part supplement, noise power ratio S/N may be prepared and tabulate if estimated value approaches actual signal, can obtain correct signal to noise power S/N with represent that correctly the weight coefficient S43 of reliability can obtain.
According to the above-mentioned structure and the signal power S42 of acquisition, noise power S40 can obtain from received signal S27, can calculate and multiply by this coefficient with received signal S28 according to noise power S40 and signal power S42 the weight coefficient S43 of noise power S/N with the expression signal, the reliability of time slot can be reflected among the receiving symbol S28.Therefore,, after the reliability of additional each time slot, can carry out the maximum likelihood sequence estimation, therefore, can recover to receive data S32 with higher precision if the receiving symbol S29 of reflection time slot reliability is fed to Veterbi decoding circuit 16.
(2) second embodiment
In Figure 13, the various piece of corresponding diagram 8 is to represent with identical label, and 60 general expressions are according to the demodulator circuit of second embodiment.Received signal S27 is input to multiplier 40 and the delay circuit 41 that constitutes the DQPSK demodulator circuit.Multiplier 40 receives the received signal S35 of the code element of delay that will present from delay circuit 41 and utilizes the received signal S27 that the complex multiplication of the value of gripping altogether of received signal S35 is imported before the code element to extract receiving symbol S28 from received signal S27.Suppose that the receiving symbol S28 that extracts by this multiplication process is the code element information of DQPSK modulation.This receiving symbol S28 is input to the fifo buffer 42 that is connecting and is stored in continuously in this fifo buffer 42.Fifo buffer 42 is preserved receiving symbol S28, and during until this time slot of code element storage with when time slot of this code element storage, fifo buffer 42 output receiving symbol S28 are to multiplier 43 then.
And the receiving symbol S28 that extracts by multiplier 40 also is input to the absolute value circuit of being made up of weight coefficient computing unit 59 61.This absolute value circuit 61 is by the I component of the received signal S28 of extraction formation QPSK signal and the absolute value of Q component, this code element information of conversion to the receiving symbol S50 that just goes up quadrant and output transform of complex number plane to the subtracter 62 and the second square-law circuit 50.
The reference symbols sn signal S51 that sends out from the RMA level circuit is input to subtracter 62.This reference symbols sn signal S51 is to be the average power of each code element in this time slot at the signal of π on the complex number plane/4 phase shifts and its amplitude.Subtracter deducts reference symbols sn signal S51 from receiving symbol S50, the signal component S52 that calculates this difference and this difference of output expression is to square-law circuit 47.About this, this signal component S52 represents to be included in the noise component(s) among the receiving symbol S50.
The first square-law circuit 47 obtains the noise component(s) power of each code element and exports this noise power S53 to first adder 48 by the signal component S52 of square each code element.The noise power of each code element that first adder 48 additions send out from the first square-law circuit 47 obtains the noise power S54 of a time slot and this power of output to calculator 49.
On the other hand, the second square-law circuit 50 obtains the signal power of each code element and exports this power to second adder 51 by square amplitude of the receiving symbol S50 that presents from absolute value circuit 61.The signal power S55 of each code element that these second adder 51 additions will send out from the second square-law circuit 50 obtains the signal power of a time slot and this power of output to calculator 49.About this, this signal power S56 just become with in the same actual signal component power of the situation of first embodiment and the signal power of noise component(s) power combination.
According to above-mentioned structure, in demodulator circuit 60 according to second embodiment, receiving symbol S28 absolute value circuit 61 transforms to complex number plane and is just going up quadrant, and poor between the receiving symbol S50 of computational transformation and the reference symbols sn signal S51, noise signal component S52 calculates and calculates according to this component the noise power S54 of a time slot.Meanwhile, obtain the signal power S56 of a time slot according to receiving symbol S50.Then, according to this noise power S54 and signal power S56, the signal of a time slot of acquisition expression multiplies each other to weight coefficient S43 and the receiving symbol S28 of noise ratio S/N.By the processing of this each time slot, therefore the signal of this time slot is reflected to noise ratio S/N in the amplitude of receiving symbol S28, forms the receiving symbol S29 of reflection time slot reliability.If the receiving symbol S29 of such reflection time slot reliability may be input in the Veterbi decoding circuit 16 of back level, the maximum likelihood sequence estimation that has then added the reliability of each time slot in Veterbi decoding circuit 18 can carry out and receive data S32 and can recover with degree of precision.
According to said structure, because conversion receiving symbol S28 be complex number plane just go up quadrant after, when from the receiving symbol S50 of conversion, deducting reference symbols sn signal S51, obtain noise power S54, with picked up signal power S56 from described receiving symbol S50, with according to noise power S54 and signal power S56, calculate and represent that signal multiplies each other to weight coefficient S43 and the receiving symbol S28 of noise ratio S/N, the reliability of time slot can be reflected among the receiving symbol S28.Therefore,, then the maximum likelihood sequence estimation can be under the situation of the reliability of having added each time slot, carried out, therefore data S32 can be recovered to receive more accurately if the receiving symbol S29 of reflection time slot reliability may be fed to Veterbi decoding circuit 16.
(3) the 3rd embodiment
At each parts corresponding to Fig. 8 is among the Figure 14 that represents with same numeral, 70 general expressions are according to the demodulator circuit of the 3rd embodiment, the same with the situation of first embodiment, received signal S27 is fed into multiplier 40 and the delay circuit 41 of forming the DQPSK demodulator circuit.The complex multiplication of the value of gripping altogether of the received signal S35 of the receiving symbol S27 front of multiplier 40 has received the delay that sends from delay circuit 41 the received signal S27 of a code element and input is extracted receiving symbol S28 from described receiving symbol S27.Suppose that utilizing this receiving symbol S28 that handles extraction that multiplies each other is QPSK modulated symbol information.This receiving symbol S28 is input to fifo buffer 42 then and storage continuously.Fifo buffer 42 is preserved receiving symbol S28, and until the full time slot of this code element storage with when a time slot is expired in storage, described receiving symbol S28 is to multiplier 43 then in fifo buffer 42 outputs.
And the receiving symbol S28 that utilizes this multiplier 40 to extract also is fed to weight coefficient computing unit 69.In weight coefficient computing unit 69, the I component of receiving symbol S28 is fed to first absolute value circuit 71 and the first square-law circuit 72, and the Q component of receiving symbol S28 is fed to second absolute value circuit 75 and the second square-law circuit 76.Amplitude and output that first absolute value circuit 71 utilizes the I component absolute value that obtains to obtain the described I component of each code element represent that the signal component S60 of this I component amplitude is to adder circuit 73.This first adder circuit 73 represent by addition the I component amplitude a time slot signal component S60 to the amplitude of summation of the I component amplitude of a time slot and output expression I component and signal component S61 to computing unit 79.
On the other hand, the I component of the first square-law circuit 72 by square each code element calculates the signal component S62 of the power of each code element I component and each code element I component power of output expression to second adder 74.The time slot of signal component S62 of the I component power of second adder 74 by adding each code element of expression, the power of the I component of a time slot of summation and output expression I component power and signal component S63 to computing unit 79.
Equally, second absolute value circuit of input Q component obtains the amplitude and signal component S64 to the three adder circuits 77 of exporting the amplitude of representing this Q component of the Q component of each code element by the absolute value that obtains Q component.The 3rd adder circuit 77 is by adding the time slot of the S64 that represents this Q component amplitude, and the signal component S65 of the amplitude of the Q component of a time slot of summation and output expression Q component amplitude is to computing unit 79.
The Q component of the second square-law circuit 76 by square each signal calculates signal component to the four adder circuits 78 of power of the Q component of the power of component of each code element Q and each code element of output expression.The signal component S66 of a time slot of power of the Q component of the 4th adder circuit 78 by adding each code element of expression, the signal component S67 of the power of the power of the Q component of a time slot of addition and output expression Q component is to computing unit 79.
Here, by first to the 4th adder circuit obtain the amplitude of I and Q component and power and, thereby simplify the structure.Yet, with code element number divided by this amplitude and power and, can obtain the mean value of amplitude and power.
Here, in Figure 15, express the structure of computing unit 79.As shown in figure 15, in computing unit 79, obtain amplitude square the same of I components with signal component S61 to the three square-law circuit 60 of amplitude by input expression I component, the amplitude of signal component S65 to the four square-law circuit 83 acquisition Q components of the amplitude by input expression Q component square.The square value of the I of these acquisitions and the amplitude of Q component is input to adder circuit 81 respectively and carries out addition and the signal component S68 of the quadratic sum of the expression amplitude that produces is fed to counting circuit 85.
On the other hand, after the signal component S67 of the signal component S63 of expression I component power and expression Q component power was fed to adder circuit 82 and carries out addition, they were fed to N doubling circuit 64 and increase the quantity of symbol time.Counting circuit 85 obtains the randomization value of I and Q component and stipulates this value as table parameter S P in weight coefficient computational chart 86 by the square value (S68) that deducts amplitude the power that increases from the quantity (S69) of symbol time.In weighted calculation table 86, the I in the table and the random value of Q component and corresponding weight coefficient (that is, expression signal to the coefficient of noise power ratio S/N and have coefficient) based on the value of measuring store and read corresponding regulation random value weight coefficient and with its output.The weight coefficient that receiving circuit 85 output is read from weight coefficient computational chart 86 as weight coefficient S43 to multiplier 43.Therefore, the signal of time slot is reflected among the receiving symbol S28 in multiplier 43 noise power ratio S/N.
According to said structure, it is I and Q component and the amplitude (S61) and the power (S63) that calculate the I component of a time slot from the I component of receiving symbol S23 that demodulator circuit 70 in the 3rd embodiment separates the receiving symbol S28 that extracts by multiplier 40, the amplitude (S65) and the power (S67) of the Q component of a time slot of calculating from the Q component of receiving symbol S28.Then, according to the amplitude of the I component of a time slot that is calculated and the amplitude and the power of power and Q component, calculate the random value of I and Q component and multiply by this coefficient to the weight coefficient S43 of noise power ratio S/N with receiving symbol S26 according to the signal that the random value of described I and Q component obtains the expression time slot.By this processing to each time slot, signal is reflected among the receiving symbol S28 noise power ratio S/N, therefore, forms the receiving symbol S29 of the reliability of this time slot of reflection.If the defeated people of this receiving symbol S29 of reflection time slot reliability is in the Veterbi decoding circuit 16 of back level, then Veterbi decoding circuit 16 can carry out the maximum likelihood sequence estimation according to additional time slot reliability, thereby, can recover to receive data S32 with higher precision.
According to said structure, from the I component of receiving symbol S28 and Q component, obtain the amplitude S61 of I component and the amplitude S65 and the power S67 of power S63 and Q component, with the random value that obtains I and Q component according to this signal, and according to this random value, the signal that calculates the expression time slot multiplies each other to the weight coefficient S43 of noise power ratio S/N and with receiving symbol S28, and the reliability of this time slot can be reflected among the described receiving symbol S28.Therefore, the receiving symbol S29 of reflection time slot reliability is fed to Veterbi decoding circuit 16, can carry out the maximum likelihood sequence estimation and can recover to receive data S32 with degree of precision under the situation of the reliability of adding each time slot.
(4) the 4th embodiment
In Figure 16, represent by same numeral corresponding to each parts of Fig. 8.General 90 expressions are according to the demodulator circuit of the 4th embodiment.Under the situation of this embodiment, weight coefficient is to determine according to the influence of the disturbing wave of receiving slot.At first, in this demodulator circuit 90, received signal S27 is fed in the multiplier 40 and delay circuit 41 of forming the DQPSK modulation circuit.Multiplier 40 receives from delay circuit 41 and sends and value of gripping altogether of postponing the received signal S35 before a code element and the code element and the received signal S27 of input carry out the received signal S35 of complex multiplication, extraction receiving symbol S28 from described received signal S27.Suppose by this multiplying each other and handle the code element information that the receiving symbol S28 that extracts is the QPSK modulation.This receiving symbol S28 is fed to fifo buffer 42 then and stores continuously.When fifo buffer 42 keeps this code element up to time slot of receiving symbol S28 storage with when time slot of receiving symbol S28 storage, export this code element to multiplier 43 then.
And the receiving symbol S28 that is extracted by multiplier 40 is fed to the absolute value circuit 91 that comprises weighted calculation unit 89.This absolute value circuit 91 by extracting the receiving symbol S28 that constitutes the QPSK signal I component and the absolute value conversion code metamessage of Q component to the receiving symbol S70 that just goes up quadrant and output transform of complex number plane to multiplier 92.In this multiplier 92, input is from the phase data S71 of π/4 phase-shift circuits, 88 outputs.This phase data S71 be have+amplitude of π/4 phase values is the plural phase data of " 1 ".Multiplier 92 utilizes this phase data of receiving symbol S70 complex multiplication S71, forms the receiving symbol S72 of phase place phase shift/4 of receiving symbol S79.
Here, if the influence of the interference-free ripple of receiving symbol S70, as shown in figure 17, the phase place that each code element of receiving symbol S72 moves in complex number plane is pi/2 and the position that is on the Q axle.Therefore, if the influence of the interference-free ripple of receiving symbol S70, then the I component of each code element becomes " 0 " and Q component becomes steady state value.On the other hand, if receiving symbol is subjected to the influence of disturbing wave, then each code element of receiving symbol S72 does not need to be on the position that phase place is a pi/2, as shown in figure 18, but is in the random scatter state that concentrates in pi/2 π/4 scopes on every side.Reason is that phase place can not turn back to former state if receive the electric wave that sends from the transmitting apparatus of the non-communication party such as disturbing wave, even may carry out phase-shift processing and remain on stochastic regime by anti-phase shift circuit 32 at random.Therefore, if the scattering state of the phase value of being represented by this receiving symbol S72 is that shift state is detected, so the be interfered influence of ripple of receiving symbol still is unaffectedly to become very clear.
Thereby the receiving symbol S72 that is obtained by multiplier 92 is separated into I component and Q component so that detect skew and I component is fed to second absolute value circuit 93 and the first square-law circuit 94, and Q component is fed to the 3rd absolute value circuit 95 and the second square-law circuit 96.Second absolute value circuit 93 obtains the signal component S73 of amplitude of the amplitude of described I component of each code element and this I component of output expression to first adder 97 by the absolute value that obtains I component.First adder 97 represent by addition the amplitude of I component of a time slot of signal component S73 summation of a time slot of amplitude of this I component and this I component of output expression amplitude and signal component S74 to computing unit 98.
The first square-law circuit 94 calculates the signal component S75 of the I component power of each code element and the I component power that each code element is represented in output to second adder 99 by the I component of each code element of square input.Second adder 99 represent by addition the I component power of a time slot of this signal component S75 summation of a time slot of I component power of each code element and this I component of output expression power and signal component S76 to computing unit 98.
Equally, Q component the 3rd absolute value circuit 95 of input obtains signal component S77 to the three adder circuits 100 of the amplitude of the amplitude of Q component absolute value of each code element and this Q component of output expression by the absolute value that obtains Q component.The 3rd adder circuit 100 represent by addition the amplitude of Q component of a time slot of signal component S77 summation of a time slot of amplitude of this Q component and this Q component of output expression amplitude and signal component S78 to computing unit 98.
The Q component of the second square-law circuit 96 by square each code element calculates signal component S79 to the four adder circuits 101 of power of the Q component of the power of Q component of each code element and each code element of output expression.The 4th adder circuit 101 represent by addition the power of Q component of a time slot of signal component S79 summation of a time slot of each code element Q component power and this Q component of output expression power and signal component S80 to computing unit 98.
Computing unit 98 is according to the power of the deviant I component amplitude and that (S74) obtain I component of input and I component with (S76), according to the power of the deviant Q component amplitude and that (S78) obtain Q component of input and Q component and (S80) and according to the deviant of I component and Q component calculate this time slot of expression be interfered ripple influence degree weight coefficient S81 (being signal-disturbing wave power ratio S/I) and export these coefficients to multiplier 43.About this,, this means that the influence of disturbing wave is remarkable and select little value as weight coefficient if deviant is big.Multiplier 43 utilizes this weight coefficient S81 to multiply by the receiving symbol S28 that sends out from fifo buffer 42, produces the signal-disturbing wave power ratio S/I on the amplitude that is reflected to described receiving symbol S28.Therefore, under the situation of this embodiment, the reliability of time slot can be reflected on the amplitude of receiving symbol S28 based on the influence of disturbing wave.
Here, the structural table of computing unit 98 is shown in Figure 19.As shown in figure 19, in this computing unit 98, represent signal component S74 to the three square-law circuit 102 of I component amplitude and represent that by input the signal component S76 of I component power is to N-doubling circuit 103 by defeated people, obtain I component amplitude square, the power of I component increases the multiple of code element.Produce square the I component amplitude and the I component power of the code element multiple of increase be fed to subtracter 104 respectively and from the code element multiple of the power of I component, deduct I component square amplitude calculate the deviant of I component.The signal component S83 of the deviant of expression I component sends to counting circuit 105 then.
And, computing unit 98 the signal component S78 of the amplitude of input expression Q component and obtain Q component amplitude square in, the signal component S80 of the power of input expression Q component has been increased the multiple of code element to N doubling circuit 107 and Q component power.Produce square the amplitude of Q component and Q component power multiple be fed to respectively subtracter 108 and by the code element multiple from the power of Q component deduct generation square amplitude can calculate the deviant of Q component.The signal component S84 of the deviant of this expression Q component sends to counting circuit 105 then.
Counting circuit 105 regulation input I unit and the Q unit deviant to the weight coefficient computational chart 109 is as the parameter of tabulation.In being stored property of the table weight coefficient computational chart 109 of the deviant of expression I unit and the deviant of Q unit and corresponding weight coefficient (coefficient and coefficient based on the value of this measurement of promptly representing the signal-disturbing wave power ratio S/I of this time slot), and counting circuit 105 is read corresponding to the weight coefficient of the deviant of the deviant of the I unit of regulation and Q unit and the weight coefficient that output is read like this from weight coefficient computational chart 109 and is given multiplier 43 as weight coefficient S81.Utilize this arrangement, at multiplier 43, the signal of this time slot-disturbing wave power ratio S/I reflects the amplitude to receiving symbol S28, and the reliability that can reflect time slot.
According to aforesaid structure, in the decoding circuit 90 according to the 4th embodiment, the code element S28 that utilizes absolute value circuit 91 to receive is transformed the right upper quadrant on the complex number plane, and the phase place of the receiving symbol of conversion is by multiplier 92 phase shift/4.Then, after the receiving symbol S72 of this phse conversion is separated into I unit and Q unit, obtain the I cell power sum (S76) of amplitude sum (S74) and a time slot of the I unit of a time slot, and obtain the Q cell power sum (S80) of amplitude sum (S78) and a time slot of the Q unit of a time slot.Then, based on these result of calculations (S74, S76, S78 and S80), obtain the deviant of I unit and the deviant of Q unit, and according to this weight coefficient S81 that obtains representing the signal-disturbing wave power ratio S/I of this time slot, this weight coefficient multiply by receiving symbol S28.Each time slot carries out this process, and signal-disturbing wave power ratio S/I reflects to the amplitude of receiving symbol S28 and constitutes reflection time slot reliability receiving symbol S29.If reflection time slot reliability receiving symbol S29 is imported into the Veterbi decoding circuit 16 of later step, then in described Veterbi decoding circuit 16, when adding the reliability of time slot, can carry out the maximum likelihood sequencal estimation, and the accuracy that the data S32 that receives can be higher is recovered.
According to aforesaid structure, because after carrying out variable π/4 phase shifts that are changed to the receiving symbol S70 of the right upper quadrant on the complex number plane, obtain from the I unit of the receiving symbol S72 of that phse conversion and the deviant of Q unit, with deviant based on this I unit and Q unit, calculate this time slot of expression signal-disturbing wave power ratio S/I weight coefficient S81 and multiply by the code element S28 of reception, can reflect to described receiving symbol S28 based on the reliability of this time slot of this disturbing wave.Therefore, if the receiving symbol based on the reflection time slot reliability of this disturbing wave can be presented to Veterbi decoding circuit 16, even in having the environment of disturbing wave, when adding the reliability of each time slot, can carry out the maximum likelihood sequencal estimation, therefore the accuracy that the data S32 that receives can be higher is recovered.
(5) the 5th embodiment
In Figure 20, wherein the parts corresponding to Figure 16 give identical label, according to the 5th embodiment 110 general expression demodulator circuits.Under the situation of this embodiment, handle the receiving symbol S72 that forms by the phse conversion of multiplier 92 and be not separated into I unit and Q unit, but this receiving symbol is converted to magnitude unit γ and phase unit θ by polar coordinate transform, and calculates weight coefficient in view of the above.
At first, in weight coefficient computing unit 121, the receiving symbol S72 that is obtained by multiplier 92 and the phase place of π/4 phase shifts thereof are input to polar coordinates translation circuit 111.Polar coordinates translation circuit 111 is applied to receiving symbol S72 with the polar coordinates conversion, extract the magnitude unit r of receiving symbol S72 and at the phase unit θ of each code element complex number plane and export described magnitude unit r to second absolute value circuit 112 and the first square-law circuit 113, and output phase unit θ to the three absolute value circuits 114 and the second square-law circuit 115.
Second absolute value circuit 112 obtains the absolute value of magnitude unit r and exports this being worth first add circuit 116.The magnitude unit r of first add circuit 116 by adding a time slot the magnitude unit r's that thoroughly deserves a time slot and and output expression one time slot magnitude unit r's and signal element S90 give computing unit 117.The first square-law circuit 113 calculates this power cell and exports it to second add circuit 118 by the magnitude unit r of square each code element.Second add circuit 118 by the power cell that adds a time slot obtain a time slot power and and the power of output expression one time slot and signal element S91 give computing unit 117.
On the other hand, the 3rd absolute value circuit 114 obtains the absolute value of phase unit θ and exports this value and give the 3rd add circuit 119.The 3rd add circuit 119 obtain by the phase unit θ that adds a time slot time slot phase unit θ's and and output expression one time slot phase unit θ's and signal element S92 give computing unit 117.The result of the phase unit θ of 115 squares of each code elements of the second square-law circuit and output square gives the 4th add circuit 120.The 4th add circuit 120 add square result of phase unit θ of a time slot and output expression one time slot that square the result's and signal element S93 give computing unit 117.
Computing unit 117 except based on magnitude unit r sum (S90) with square magnitude unit r sum (S91) obtain the deviant of magnitude unit r, also based on phase unit θ sum (92) with square phase unit θ sum (92) obtain the deviant of phase unit θ and according to the deviant of the deviant of this magnitude unit r and phase unit θ this weight coefficient of tabulating, and output to multiplier 43 as weight coefficient S94.In this connection, and under the situation of this embodiment, computing unit 117 has the weight coefficient computational chart, relation and corresponding to a table of this weight coefficient (coefficient of promptly representing the signal-disturbing wave power ratio S/I of time slot) between the deviant that comprises expression magnitude unit r and the deviant of phase unit θ, and according to the tabulate weight coefficient S94 of these weight coefficient computational chart calculating needs of the deviant of the deviant of magnitude unit r and phase unit θ.
According to aforesaid structure, in demodulator circuit 110, the code element S72 that should receive by polar coordinate transform extracts magnitude unit r and phase unit θ, and obtains the deviant of magnitude unit r and phase unit θ.According to the deviant of this magnitude unit r and phase unit θ, calculate the weight coefficient of the signal-disturbing wave power ratio S/I of expression time slot, and this deviant multiply by receiving symbol S28.Carry out this process by each time slot, this signal-disturbing wave power ratio S/I is reflected to the amplitude of receiving symbol S28 and forms the receiving symbol S29 of this time slot reliability of reflection.If the receiving symbol S29 of this time slot reliability of such reflection is imported into the Veterbi decoding circuit 16 of back level, described Veterbi decoding circuit 16 can carry out the maximum likelihood sequencal estimation when adding the reliability of each time slot, and the data S32 that should receive can be with higher accuracy decoding.
In this connection, under the situation of this embodiment, since deviant carry out polar coordinate transform be receiving symbol S72 and extract magnitude unit r and phase unit θ after obtain, so this deviant can be than detection more accurately under the situation of the 4th embodiment.Therefore, the influence degree and the reliability that can detect disturbing wave more accurately according to this embodiment can reflex to receiving symbol S28 more accurately.
According to aforementioned structure, because receiving symbol S72 is by polar coordinate transform and extract magnitude unit r and phase unit θ, and the deviant that obtains phase unit θ, so obtain the deviant of described magnitude unit r, and according to these, when the weight coefficient S94 of the signal-disturbing wave power ratio S/I that calculates the expression time slot, be multiplied by receiving symbol S28, can reflect to described receiving symbol S28 based on the time slot reliability of disturbing wave.Therefore, if reflection can be presented to Veterbi decoding circuit 16 based on the receiving symbol S29 of the time slot reliability of disturbing wave, even in having the environment of disturbing wave, when adding the reliability of each time slot, can carry out the maximum likelihood sequencal estimation, and the precision that the data S32 that receives can further improve is recovered.
(6) the 6th embodiment
In Figure 21, wherein corresponding figures 8 is marked with identical label with 16 parts, and 130 general expressions are according to the demodulator circuits of the 6th embodiment.Under the situation of this embodiment, use in any the weight coefficient computing unit 52,59 shown in first, second or the 3rd embodiment or 60 and at this weight coefficient of combination calculation of the weight coefficient computing unit 89 shown in the 4th embodiment.Even such demodulator circuit 130 compatibly use exist noise and disturbing wave the two environment and the environment that occurs strong single disturbing wave suddenly normally this disturbing wave become noise.
At first, in this line interface unit 130, received signal S27 presents to multiplier 40 and the delay circuit 41 that comprises the DQPSK modulation circuit.Multiplier 40 receives from delay circuit 41 and sends and the received signal S35 of the conjugate of the received signal S27 of the signal S35 that postpones to receive before a code element and code element of CM and input, extracts the code element S28 that receives from described received signal S27.But, be the code element information that QPSK modulates by this receiving symbol S28 that takes advantage of processing to obtain.The code element S28 of this reception presents to follow-up buffer FIFO 42 and stores successively.Fifo buffer keeps the code element S28 that receives to be stored a time slot up to it, and when storing the receiving symbol S28 of a time slot, it exports the multiplier 43 of the code element S28 of described reception to the back.
In addition, the receiving symbol S28 that is obtained by multiplier 40 presents to the first weight coefficient computing unit 52, but also presents to the second weight coefficient computing unit 89.Owing to be used as the first weight coefficient computing unit, can use weight coefficient computing unit 59 or 69 here, according to the second or the 3rd embodiment according to the weight coefficient computing unit 52 of first embodiment.And, be weight coefficient computing unit 89 according to the 4th embodiment second weight coefficient computing unit.
The first weight coefficient computing unit 52 as in first embodiment by confirming that temporarily receiving symbol S28 forms duplicating of received signal S37, and obtain noise power according to the difference between received signal S37 that duplicates and the original received signal S27.Then, the first weight coefficient computing unit 52 calculates the signal-noise ratio S/N weight coefficient S43 of expression time slot and exports this weight coefficient to the three weight coefficient computing units 131 according to the signal power tabulation of noise power S40 and received signal S27.
On the other hand, as under the situation of the 4th embodiment, at complex number plane up conversion receiving symbol S28 after right upper quadrant, this phase place of the second weight coefficient computing unit 89 displacement π/4 and to form its phase condition be to be the receiving symbol S72 at center around complex number plane Q axle.The second weight coefficient computing unit 89 extracts I unit and Q unit and calculates the deviant of described I unit and the deviant of Q unit from receiving symbol S72, according to these values, with these value lists, it calculates weight coefficient S81 and this coefficient of output of the signal-disturbing wave power ratio S/I of this time slot of expression and gives the 3rd weight coefficient computing unit 131.
According to signal-noise power ratio S/N of expression weight coefficient S43 and signal-disturbing wave power ratio S/I of expression weight coefficient S81, the 3rd weight coefficient computing unit 131 calculates the weight coefficient of expression signal-interference noise power than S/ (I+N), make up this two unit therein, and export it to the new weight coefficient S100 of multiplier 43 conducts.Therefore, multiply by receiving symbol S28 by the weight coefficient S100 that will comprise two unit, multiplier 43 makes signal-interference noise power reflect amplitude to receiving symbol S28 than S/ (I+N), and considers this two unit, forms the receiving symbol S29 of reflection time slot reliability.
At the 3rd weight coefficient computing unit 131, calculating under the situation of expression signal-interference noise power than the weight coefficient S100 of S/ (I+N), tabulate according to two weight coefficient S43 and S81, therefore obtain weight coefficient S100.Specifically, the value of weight coefficient S43 is L, and the value of weight coefficient S81 is M, and preparing in advance can be according to all these values L and M as shown in figure 22, and calculates corresponding weight coefficient S100 by input value L and M to this table.For example, be " 5 " if the value L of weight coefficient S43 is the value M of " 1 " and weight coefficient S81, then calculate weight coefficient with value EA.The value AA and the HH that represent at Figure 22 are in advance respectively by measuring the estimated value of signal-interference noise power than S/ (I+N).
According to aforesaid structure, because the weight coefficient S81 of the signal-disturbing wave power ratio S/I of the time slot that calculates by the second weight coefficient computing unit 89 than the weight coefficient S43 of S/ (I+N) and expression according to the signal-interference noise power of the time slot that calculates by the first weight coefficient computing unit 52, weight coefficient S100 represents that signal-interference noise power is than S/ (I+N), wherein calculating two unit is combined and multiply by receiving symbol S28, the reliability of time slot can correctly be calculated and under the situation that noise and disturbing wave all exist, receiving symbol S28 is given in reflection.Therefore, even in Veterbi decoding circuit 16, the accuracy that the data of reception also can be higher is recovered.
(7) the 7th embodiment
In Figure 23, the corresponding component of Fig. 8 gives identical label, according to the 7th embodiment 140 general expression demodulator circuits.And under the situation of this embodiment, consider in received signal S27, to comprise noise component(s) and interference components, as, calculate weight coefficient in the situation of the 6th embodiment.
At first, in this demodulator circuit 140, received signal S27 presents to multiplier 40 and the delay circuit 41 that comprises the DQPSK demodulator circuit.Multiplier 40 receives from the received signal S35 of a code element of delay of delay circuit 41 transmissions with by the conjugate CM of the last code element of received signal S35 is imported received signal S27 with this, extracts the code element S28 that receives from described received signal S27.Suppose that by this receiving symbol S28 that takes advantage of processing to obtain be the code element information that QPSK modulates.This code element information S28 presents to fifo buffer 42 and storage continuously.Fifo buffer 42 keeps this receiving symbol S28, up to time slot of its storage with as the receiving symbol S28 that stores a time slot, exports the multiplier 43 that described receiving symbol S28 gives the back.
And the receiving symbol S28 that is obtained by multiplier 40 presents to the temporary transient decision circuit 44 that comprises weight coefficient computing unit 141.This temporary transient decision circuit 44 is to be used for temporarily determining that under which phase condition receiving symbol S28 is circuit and the output complex signal S36 in the form of four phase conditions of QPSK, and the amplitude of the phase condition that expression is temporarily determined is " 1 " for multiplier 45 and multiplier 142.
The received signal S35 that postpones a code element and send from delay circuit 41 presents to multiplier 45, and this multiplier 45 will multiply by the received signal S35 that postpones a code element from the complex signal S36 of temporary transient decision circuit 44, form the DQPSK modulation signal, promptly, the received signal S27 of regeneration duplicates received signal S37 and exports it to substrate 46.
And the signal S27 of primary reception presents to subtracter 46 and described subtracter 46 and gives the first square law circuit 47 from the signal component S38 that the signal S27 of primary reception deducts the result that the received signal S37 that duplicates and output expression subtract.Under this situation, if the result of determination of temporary transient decision circuit 44 is correct, this signal component S38 becomes the noise component(s) that is included among the received signal S27 and is included in the signal of the noise component(s) combination among the signal S27 that receives before the code element when temporarily judging.
Power and output noise power S39 that the amplitude of the first square law circuit 47 by the signal component S38 of square each code element obtains the noise component(s) of each code element give first add circuit 48.First add circuit 48 obtains the noise power S40 of a time slot and exports to 1/2 circuit 143 by adding noise power S39.As mentioned above and since this S40 be by the noise power S39 of two code elements with constitute, 1/2 circuit 143 is given subtracter 144 and divider 145 with the noise power S110 that this noise power S40 dimidiation and output obtain.
Received signal S27 also presents to the second square law circuit 50.This second square law circuit 50 obtains the received signal S27 of each code element by square amplitude of this received signal S27 power and output signal power S41 give second add circuit 51.Second add circuit 51 obtains the signal power S42 of a time slot and exports it to subtracter 144 by adding that signal power S41.About this, this signal power is represented the signal power of received signal S27 and is the signal power of the power combination of the actual power of signal component and noise component(s).
Subtracter 144 obtains pure signal power S111 and exports to divider 145 by deduct noise power S110 from signal power S42, from this pure signal power S111 estimating noise power.Divider 145 is by calculating this signal power S111 the signal-noise power ratio S/N of this time slot and export to selector switch 147 and comparator 148 divided by noise power S110 then, and they are narrated as weight coefficient S112 below.
In selector switch 147, this weight coefficient S112 presents to first input terminal, and the weight coefficient S130 that has value " 0 " simultaneously presents to second input terminal.Selector switch 147 is general to be selected weight coefficient S112 and exports to multiplier 43, still, when control signal S128 when comparator 148 sends, it select weight coefficient S130 and output it, to replace weight coefficient S112.Multiplier 43 is taken advantage of weight coefficient S112 or is taken advantage of S130 that selector switch 147 sends to the receiving symbol S28 that produces from fifo buffer 42.Therefore, can constitute the receiving symbol S29 of reflection time slot reliability.
About this, the signal power S42 that is made of second add circuit 51 also presents to 1/N circuit 146.This 1/N circuit 146 is by calculating signal power S42 the signal power S113 of a code element and export to counting circuit 149 reciprocal divided by the code element number of a time slot.Counting circuit 149 reciprocal calculates the reciprocal value S114 of this signal power S113 and exports to multiplier 150.This multiplier 150 multiply by the standardize power of each code element of described receiving symbol S29 of this reciprocal value S114 by each code element with receiving symbol S29.Therefore, even in receiving circuit 31, can not produce fully under the situation of power of each time slot, even can produce the power of each time slot and can cancel the demarcation of the power of each time slot by this standardization.About this, the reason of the power of balanced each time slot is: if this power is demarcated on time slot ground one by one, that then whether cause or be unclear by the low-signal levels that low electric power causes by the poor reliability of time slot, and in the Veterbi decoding circuit 16 of back level, can not correctly recover to receive data 32.
On the other hand, in the added multiplier 142 of complex signal S36, also import receiving symbol S28.The conjugate CM of the complex signal S36 of the phase place of this multiplier 142 by will representing receiving symbol S28 constitutes receiving symbol S115 with described receiving symbol S28, and the phase place of described receiving symbol S28 is shifted.If the influence of the interference-free ripple of receiving symbol S28, as shown in figure 24, it is zero position that each code element of this receiving symbol S115 is present in phase place on the complex number plane, and promptly on X-axis, Q component becomes " 0 " and I component becomes fixed value on this position.On the other hand, the influence of ripple if this receiving symbol S28 is interfered, as shown in figure 25, then each code element of receiving symbol S115 needn't be on the I axle, and still being dispersed in around the I axle randomly is in π/4 zones at center.Therefore, the dispersion level that can detect the phase value of representing with receiving symbol S115 is a dispersion, can find signal-disturbing wave power ratio S/I.Therefore, after this receiving symbol S115 was divided into I component and Q component, this receiving symbol S115 was fed to the circuit of back, was used for signal calculated-disturbing wave power ratio S/I.
At first, the component of the I of receiving symbol S115 is presented to the 3rd square law circuit 151 and the 3rd add circuit 152.The signal component S116 of power that the amplitude of the 3rd square law circuit 151 by the I component of square each code element obtains the I component of the power of I component of each code element and each code element of output expression gives the 4th add circuit 153.The 4th add circuit 153 calculates the I component of the power of I component of a time slot and a time slot of output expression by the signal component S116 that adds a time slot the signal component S117 of power gives subtracter 154.
On the other hand, the amplitude of the I component of the 3rd add circuit 152 by adding a time slot obtains the value of increase of amplitude of I component and the signal component S118 of this added value of output expression gives the 4th square law circuit 155.155 squares of these signal components of the 4th square law circuit S118 obtains the square value of amplitude of I component and the signal component S119 of this square value of output expression gives 1/N circuit 156.1/N circuit 156 is given subtracter 154 with the result's that this signal component S119 removes divided by the code element number of a time slot and output expression signal component S120.Then, in subtracter 154,, can obtain the centrifugal pump of I component from signal component S117 subtraction signal component S120.The signal component S121 that represents the centrifugal pump of this I component increases progressively 5 times and present to comparator 148 by 5 doubling circuits 157 in succession.
On the other hand, the Q component of receiving symbol S115 offers the 5th square law circuit 158 and slender acanthopanax method circuit 159.The signal component S122 of power that the amplitude that logical of the 5th square law circuit 158 produces the Q component of each code element square obtains the Q component of the power of Q component of each code element and each code element of output expression gives the 6th add circuit 160.The 6th add circuit 160 calculates the Q component of the power of Q component of a time slot and output expression one time slot by this signal component S122 that adds a time slot the signal component S123 of power gives subtracter 161.
The amplitude of the Q component of each code element of slender acanthopanax method circuit 159 by adding a time slot obtains the added value of Q component amplitude and the signal component S124 of this added value of output expression gives the 6th square law circuit 162.The 6th square law circuit 162 obtains the square value of amplitude of Q component by square this signal component S124 and the signal component S125 of this square value of output expression gives 1/N circuit 163.1/N circuit 163 is with the code element number and the signal component S126 that represent its result of subtracter 161 of this signal component S125 divided by a time slot.Therefore, in subtracter 161, obtain the centrifugal pump of Q component from signal component S123 subtraction signal component S126.The signal component S127 of the centrifugal pump of expression Q component sends to comparator 148.
Whether the centrifugal pump that comparator 148 is judged Q components is greater than the centrifugal pump of 5 times I component or be not according to signal component S121 and signal component S127.If the centrifugal pump of Q component become greater than or surpass 1 component, its decision signal-disturbing wave power ratio S/I is lower than 10[dB] and output control signal S128 give selector switch 147.Therefore, when received signal S27 was subjected to the strong jamming wave action, the weight coefficient S130 that it has a value " 0 " by output reduced the reliability of receiving symbol S28, and the fact that received signal S27 is subjected to the influence of strong jamming ripple can reflect to receiving symbol S28.
About this, whether the centrifugal pump whether centrifugal pump of generation Q component exceeds five times I component is subjected to the fact of the criterion of strong jamming wave action to be based on actual measurement as this received signal.More particularly, the centrifugal pump of Q component is removed the centrifugal pump of I component, the value that obtains be centrifugal pump than RQ/I, and calculate this centrifugal pump by experiment than the relation between RQ/I and the signal-disturbing wave power ratio S/I, exist relation as shown in figure 26.Clear from this Figure 26, when centrifugal pump exceeded value " 5 " than RQ/I, signal-disturbing wave power ratio S/I became and is lower than-10[dB], and clearly, it is subjected to the influence of strong jamming ripple.
The weight coefficient S112 of expression signal-noise power ratio S/N presents to comparator 148, and exceed weight coefficient S112 10[dB at decision signal-noise power ratio S/N] situation, described comparator 148 is not exported control signal, and is bigger even the centrifugal pump of Q component becomes.Therefore, can prevent that the weight coefficient S130 with value " 0 " from being selected mistakenly, even signal-noise power ratio S/N is greater than 10[dB] and communication quality be satisfied, and can prevent the reduction of the reliability of receiving symbol S28.
According to aforesaid structure, under the situation according to this 7th embodiment, receiving symbol S28 temporarily determined, the received signal S27 according to before this temporary transient determination result S36 and the code element constitutes the received signal S37 that duplicates, the received signal S27 that promptly duplicates.And, obtain the noise component(s) S38 of each code element and obtain the noise power S110 of a time slot in view of the above by getting poor between this received signal S37 that duplicates and the original received signal S27.And, obtain the signal power S42 of the received signal S27 of a time slot, by deducting noise power S110, obtain pure signal power S111 from signal power S42.Then, this signal power S111 obtains the signal-noise power ratio S/N of this time slot and export to multiplier 43 as weight coefficient S112 through selector switch 147, and described weight coefficient S112 is multiplied by receiving symbol S28 divided by noise power S110.Therefore, the signal-noise power ratio S/N of this time slot reflects to receiving symbol S28.
In addition, cooperate therewith, receiving symbol S28 multiply by the conjugate of the temporary transient result of determination S36 of receiving symbol S28, has formed near the receiving symbol S115 that symbol phases is shifted the I axle and the centrifugal pump S121 of the I component that obtains time slot from described receiving symbol S115 and the centrifugal pump S127 of Q component.Then, comparator 148 judges whether the centrifugal pump of Q component exceeds the centrifugal pump of 5 times I component, the result, if the centrifugal pump of Q component exceeds I component, it judges that this time slot is subjected to the influence and the output control signal S128 of strong jamming ripple, and displacement weight coefficient S112 is to the weight coefficient S130 with value " 0 ".Therefore, be subjected at this time slot under the situation of strong jamming wave action, the reliability of described receiving symbol S28 has reduced receiving symbol S28 and multiply by the have value weight coefficient S130 of " 0 ", and the fact that it is subjected to the influence of strong jamming ripple reflects to receiving symbol S28.
Therefore, under the situation of this modulation circuit 140, noise component(s) and disturbing wave component that consideration comprises in received signal S27, according to this noise component(s) and disturbing wave component, this reliability reflects to receiving symbol S28.Therefore, to present Veterbi decoding circuit 16 if reflect the receiving symbol S29 of such reliability to back level, described Veterbi decoding circuit 16 can carry out maximum likelihood and estimate when adding this reliability, if and it is subjected to the influence of strong jamming ripple suddenly, can recover to receive data S32 exactly, and not recover this disturbing wave mistakenly.
According to aforesaid structure, owing to obtain the signal-noise power ratio S/N of this time slot and reflect it to described receiving symbol S28 from receiving symbol S28, finding under the situation of interference effect according to the centrifugal pump of I that obtains from receiving symbol S28 and Q component, the influence of described interference is reflected to receiving symbol S28, has considered that the reliability of noise component(s) and disturbing wave component can reflect to receiving symbol S28.
(8) the 8th embodiment
In Figure 27, the respective component of Figure 23 is specified identical label, and 170 general expressions are according to the demodulator circuit of the 8th embodiment.Under the situation of this embodiment, the parts that obtain signal-noise power ratio S/N are different for the demodulator circuit of representing in the 7th embodiment 40, and the weight coefficient computational methods are also different.
In this demodulator circuit 170, expression is input to the first square law circuit 47 by the signal component S38 of the noise component(s) that subtracter 46 calculates.The first square law circuit 47 obtains the power of the noise component(s) of each code element by the amplitude of the signal component S38 of square each code element, and output noise power S39 gives first add circuit 48.First add circuit 48 obtains the noise power S40 of a time slot and exports to 1/N circuit 178 by adding noise power S39.Noise power S40 is obtained the noise power S149 of each code element divided by code element number N, and export to 1/2 circuit 143 and subtracter 144.As mentioned above and since noise power S40 be two code elements noise power S39's and, 1/2 circuit 143 is given divider 145 with the noise power S110 that this noise power S149 dimidiation and output obtain.
On the other hand, the signal S27 of reception presents to absolute value circuit 172.Absolute value circuit 172 is given add circuit by amplitude that thoroughly deserves described received signal S27 that obtains received signal S27 and the signal component S140 that exports this amplitude of expression.The 7th subtraction circuit 173 calculate by this signal component S140 that adds a time slot time slot amplitude and and this amplitude of output expression and signal component S141 give 1/N circuit 174.1/N circuit 174 passes through average amplitude and the output signal component S142 of code element number calculating divided by a time slot with signal component S141, so that give the 7th square law circuit 175 these average amplitudes of expression.The 7th square law circuit 175 is by square average power S143 of each code element of this signal component S142 calculating received signal S27 and export to subtracter 144.
Subtracter 144 deducts noise power S149 from the average power S143 of received signal S27 and calculates and eliminated the pure signal power S144 of noise component(s) and exported to divider 145.Utilize this arrangement, signal power S144 is obtained the signal-noise power ratio S/N of time slot divided by noise power S110 to divider 145 and the signal component S145 of this signal-noise power ratio S/N of output expression gives weight coefficient computational chart 176.
In weight coefficient computational chart 176, storage is based on the table of the signal component S145 that measures and corresponding signal-noise power ratio S/N, and, read corresponding signal-noise power ratio S/N and export as weight coefficient S146 in the time that signal component S145 is provided from divider 145.This weight coefficient S146 presents to multiplier 43 through selector switch 147, as in the situation of the 7th embodiment, and multiply by receiving symbol S28.Therefore, still under the situation of this embodiment, can reflect to receiving symbol S28 based on the reliability of the signal-noise power ratio S/N of this time slot.About this, the value of signal component S145 can offer selector switch 147 as weight coefficient S146, and does not use weight coefficient computational chart 176 to tabulate.
According to aforementioned structure, under the situation of this 8th embodiment, as the 7th embodiment, the noise power S40 that deducts half from the power S42 of received signal S27 can not obtain pure signal power.But, obtain pure signal power S144 from the power noise power S149 of each code element of received signal S27.Therefore, under the situation of this embodiment, when noise power became big, signal power S144 became than littler in the situation of the 7th embodiment, the result, and the signal-noise power ratio S/N that is obtained by divider 145 becomes less.At this moment, the signal-noise power ratio S/N that is obtained by divider 145 can not increase equably, and is big more but noise power S149 becomes, and it might become littler.Therefore, as shown in FIG. 8, be under the condition of satisfaction at the signal-noise power ratio S/N shown in solid line, do not express tangible difference by the signal-noise power ratio S/N that normally calculates, still, according to this embodiment, this difference has become obviously, and is shown in dotted line.Therefore, it may be different becoming this CALCULATION OF PARAMETERS value in tabulation, is that weight coefficient S146 may be different with the signal-noise power ratio S/N that tabulates, the result, and reliability reflects to receiving symbol S28 with further improved precision.
According to aforementioned structure, because signal calculated power S144 has eliminated from the average power S143 of received signal S27 and has deducted the hot-tempered sound component that noise power S149 obtains, with according to this signal power S144 and noise power S149, signal-noise power ratio S/N of being used to tabulate, the tabulation that can easily calculate weight coefficient S146 have been obtained.
(9) other embodiment
First embodiment that narrates has above related to the situation that weight coefficient computational chart 49A is provided, computational chart 49A is included in noise-signal power in the computing unit 49 than the table of N/ (S+N) and corresponding signal-noise power ratio S/N, according to being obtained noise-signal power by noise power S40 and signal power S42 than tabulate corresponding signal-noise power ratio S/N and use this value as weight coefficient S43 of N/ (S+N).But, the invention is not restricted to this, and weight coefficient can obtain according to other method in the computing unit.For example, the value of supposing noise power S40 is A, and the value of signal power S42 is B, and the value C that is calculated by following formula is used as signal-noise power ratio S/N.
C＝2-K×A/B …(1)
The table of the relation between expression value A/B and the value C is stored among the weight coefficient computational chart 49A.Then, value A/B calculates according to noise power S40 and signal power S42, and according to the value of A/B, from weight coefficient computational chart 49A tabulation analog value C.Like this, obtain signal-noise power ratio S/N and this and can be used as weight coefficient S43 output.About this, here the value of the constant k of Shi Yonging is the value from " 5 " to " 10 ", is preferred value such as " 6 ".
In addition, the invention is not restricted to above-mentioned situation.Here the value of noise power S40 is that the value of A and signal power S42 is B, and the table of expression A/B value and corresponding noise-signal power are tabulated than the table of N/ (S+N) and be stored among the weight coefficient computational chart 49A.Then, calculate the value of A/B, and, obtain corresponding noise-signal power than N/ (S+N) from weight coefficient computational chart 49A according to the value of A/B according to noise power S40 and signal power S42.Then, this noise-signal power is more on duty with value B than N/'s (S+N), obtain the value of noise component(s) N, by from value B, deducting the value of this noise component(s) N, get signal component value S, with the value that obtains signal-noise power ratio S/N from these noise component(s)s N and signal component S, and this can be used as weight coefficient S43 and sends.
In addition, the invention is not restricted to this.Here the value of noise power S40 is that the value of A and signal power S42 is B, and the table of expression A/B value and corresponding noise-signal power are tabulated than the table of N/ (S+N) and be stored among the weight coefficient computational chart 49A.Then, calculate the value of A/B, and, obtain corresponding noise-signal power than N/ (S+N) from weight coefficient computational chart 49A according to the value of A/B according to noise power S40 and signal power S42.Then, this noise-signal power is more on duty with value B than N/'s (S+N), obtain the value of noise component(s) N, by from value B, deducting the value of this noise component(s) N, get signal component value S, with the value that obtains signal-noise power ratio S/N from these noise component(s)s N and signal component S, and this can be used as weight coefficient S43 and sends.
And, the invention is not restricted to this.Here the value of noise power S40 is A, with the value of signal power S42 be B, with list in A/B value and corresponding signal-noise power ratio S/N in the table and be stored among the weight coefficient computational chart 49A, and, can obtain signal-noise power ratio S/N and output as weight coefficient S43 according to the value list of A/B.In addition, the invention is not restricted to this, utilization value B-A obtains signal component value S, list in the table with the value D that the value of this signal component S is obtained divided by the value of A and signal-noise power ratio S/N and be stored among the weight coefficient computational chart 49A, by value list according to D, can obtain signal-noise power ratio S/N, and this can be used as weight coefficient S43 transmission.
In addition, and as shown in Figure 29, computing unit 180 can be made of subtracter 181 and divider 182, and the value of signal component S can be obtained by the value B-A that subtracter 181 obtains, signal element S can be used as original signal-noise power ratio S/N divided by the value D that the value of A obtains, and this in fact can be used as signal-noise power ratio S/N and this and can be used as weight coefficient S43 and send.About this, in fact be worth D as under the situation of weight coefficient S43, this system has the advantage of the structure of simplifying computing unit 49, though compare with the tabulation of using this table, this precision has become difference to a certain extent according to weight coefficient.
In addition, the 4th embodiment that narrates has above related to the situation of signal-disturbing wave power ratio S/I as weight coefficient S81 of utilizing.In this 4th embodiment, prepared the weight coefficient computational chart 109 that concerns between the deviant of expression I component and Q component and the signal-noise power ratio S/I, with this weight coefficient computational chart 109 of tabulating according to the deviant of I component and Q component, read output signal-noise power ratio S/I and as weight coefficient S81.But, the invention is not restricted to above-mentioned situation, and this weight coefficient can be calculated by predetermined calculating.For example, here the deviant of I component is A, and the deviant of Q component is the amplitude of B and the signal S27 by square reception and is C at the received signal S27 that a time slot obtains its addition, from the following formula value of obtaining D:
D＝k1×A/C2+k2×A/B …(2)
Use value D, by the following formula value of obtaining " a ":
a＝k3×2-D …(3)
This value " a " can be used as weight coefficient and sends.Suppose k1, k2, k3 be respectively constant and value k1 used herein approximately be " 2 " to " 5 ", particularly as " 3 " be the optimum value of k1.It is " 0.5 " that the value of k2 is about " 0.1 " to " 1.0 " and optimum value, and the value of k3 approximately " 1 " to " 8 " and optimum value is " 3 ".
In addition, value b is obtained by following formula and this value can be used as weight coefficient and sends.
b＝k3×2D/C …(4)
But, becoming under the situation of constant by receiving circuit 31 amplifications at the power of each time slot, value D can be defined as follows:
D＝k1×A+k2×A/B …(5)
Can obtain by following formula with value D.
D＝k2×A/B …(6)
Perhaps, it can be obtained by following formula.
In addition, here the deviant of I component is A, and the deviant of Q component is B and the average amplitude that obtains Q component and makes this value be E that the code element number of a time slot is N and uses following formula calculated value F:
F＝k4×(A-k5×B)/(E×N) …(7)
With this value of use F value of obtaining d.
d＝k6×2-F …(8)
This value d can be used as weight coefficient and sends.Suppose that working as the value F that obtains in formula (7) is less than " 0 ", then formula (8) is calculated with F=0.And k4, k5, k6 are constants, and the value of k4 is about " 3 " to " 10 " and about " 6 " are optimum values, and the value of k5 approximately is that " 1 " to " 3 " and optimum value for example are " 2 ", and the value of k6 is a selected value.
And when the power of each time slot became constant by receiving circuit 31 amplifications, value F can be expressed from the next:
F＝k4×(A-k5×B) …(9)
And value F can be obtained by the formula shown in top.
In addition, it is that the phase place of the receiving symbol S70 of right upper quadrant is shifted in this complex number plane or in the situation of axial each element position of this plane Q at the complex number plane up conversion that the 4th embodiment that narrates has above related to by pi/4 shift.But, the invention is not restricted to this, but be transformed to the phase place of the receiving symbol S70 of right upper quadrant by pi/4 shift, each element position can be displaced to this complex number plane I axle.But in this case, I component and Q component should be handled reversedly with the 4th embodiment.
In addition, the 6th embodiment that narrates has above related to the situation of calculating weight coefficient S100, wherein is combined as a table by the first weight coefficient computing unit, 52 calculated weighting coefficient S43 with by the second weight coefficient computing unit, 89 calculated weighting coefficient S81 by tabulation.But, the invention is not restricted to this, and can use with weight coefficient S43 on duty with weight coefficient S81 value and this coefficient as weight coefficient S100, wherein these result of calculations are combined.
In addition, the 7th and the 8th embodiment that narrates has above related to by providing 1/2 circuit 143 to have the situation of noise power S40 or S149.But, the invention is not restricted to this, by removing 1/2 circuit 143 and using noise power S40 or S149 can obtain signal-noise power ratio S/N, as original.
And, the 7th embodiment that narrates has above related to by deduct noise power S110 from the signal power S42 that comprises noise component(s) and signal component and has obtained the signal power S111 that only is made of signal component, and uses described signal power S111 to obtain signal-noise power ratio S/N.But, the invention is not restricted to this, also can obtain signal-noise power ratio S/N according to the structure shown in Figure 30.
Specifically, in Figure 30, wherein the corresponding component of Figure 23 gives identical label, 190 general expression demodulator circuits, and under the situation of this demodulator circuit 190, and the noise power of a time slot that is calculated by first add circuit 48 is presented to 1/N circuit 191.1/N circuit 191 is by obtaining noise power S40 the noise power S190 of each code element and export to 1/2 circuit S192 divided by code element number N.1/2 circuit 192 with this noise power S190 in two and the noise power S191 that obtains of output give counting circuit 193 reciprocal.Counting circuit 193 reciprocal obtains the reciprocal value of this noise power S191 and exports to subtracter 194.Clear from top narration, reciprocal value S192 represents the reciprocal value of noise component(s) N, i.e. 1/N.
On the other hand, the signal power S42 of a time slot that is calculated by second add circuit 51 presents to 1/N circuit 195.1/N circuit 195 is by obtaining signal power S42 the signal power S193 of each code element and export to counting circuit 196 reciprocal divided by code element number N.Counting circuit 196 reciprocal obtains the reciprocal value S194 of this signal power S193 and exports to described subtracter 194.About this, because signal power S42 is made of pure signal component S and noise component(s) N, this reciprocal value S194 represents 1/ (S+N).
Subtracter 194 obtain difference between reciprocal value S194 and the reciprocal value S192 and output as a result S195 give selector switch 147 as the signal-noise power ratio S/N that gives selector switch 147.Therefore, in multiplier 43, receiving symbol S28 be multiply by this result of calculation S195 as weight coefficient, the reliability of time slot reflects to described receiving symbol S28.Utilize this arrangement, if make difference between the reciprocal value S192 of the reciprocal value S194 of signal power S193 and noise power S190 as this signal-noise power ratio, then the reliability of time slot can reflect to receiving symbol S28 and can obtain the similar effect of situation with the 7th embodiment.About this, according to structure shown in Figure 30, by cancellation 1/N circuit 191 and 195 and use noise power S40 and signal power S42 can obtain signal-noise power ratio S/N.In addition, according to structure shown in Figure 30, as in the situation of the 7th embodiment, the signal-noise power ratio S/N that obtains does not offer comparator 148.But as in the situation of the 7th embodiment, the switching manipulation that signal-noise power ratio S/N can present the selector switch 147 that carries out to comparator 148 and comparator 148 can be under an embargo according to the value of signal-noise power ratio S/N.
And the foregoing description has related to the present invention has been applied to situation in the wireless communication system that utilizes tdma system communication.But, the invention is not restricted to this, and for example,, can obtain the effect identical with above-mentioned situation if it is applied in the wireless communication system shown in Figure 31 and 32.
Wireless communication system shown in Figure 31 and 32 is described below.At first, in Figure 31, the corresponding component of Fig. 4 gives identical label, the transmitting apparatus of 200 general expression wireless communication systems.In this transmitting apparatus 200, the transmission signal S5 that is produced by DQPSK modulation circuit 5 offers the anti-fourier transform circuit of high speed (IFFT) 201.The anti-fourier transform circuit of high speed (IFFT) 201 is to pile up (pile) on the phase difference of a plurality of carrier waves of separating of fixed range to send the code element information of signal S5 and import transmission signal S200 that a plurality of carrier waves constitute to random phase shift circuit 21 in its frequency.Random phase shift circuit 21 is by adding the random phase value of utilizing predetermined rule to produce according to the initial phase place value of a plurality of carrier phases that constitute to send signal S200, the phase value of a plurality of carrier waves of randomization and provide the transmission signal S201 that obtains to transtation mission circuit 6.This is sent signal S201 fix handle after, 6 pairs of these transmission signals of transtation mission circuit S201 carries out frequency conversion process, is transformed to the transmission signal of the frequency channels with regulation, and pass through antenna transmission it.Under the situation of this wireless communication system, the frequency channels of each fixing transmission signal S202 regularly of transtation mission circuit 6 randomizations promptly carries out frequency hopping.
On the other hand, in Figure 32, wherein the corresponding component of Fig. 5 gives identical label, the receiving equipment of 210 general these wireless communication systems of expression, and in this receiving equipment, present to receiving circuit 31 because of antenna connects 11 received signals of receiving.The received signal S205 of 31 pairs of these fixed frequency channels of receiving circuit carries out frequency conversion process, extracts baseband signal S206 and exports to high speed fourier transform circuit (FFT) 211.High speed fourier transform circuit (FFT) 211 handles the code element information of taking out a plurality of carrier waves accumulations phase information formation thereon and exports to random phase backward shift position circuit 32 as the code element S207 that receives by fourier transform.Random phase backward shift position circuit 32 use phase condition that the phase value identical with transmitter side recover received signal S207 to before condition and the received signal S27 that obtains of output to demodulator circuit 33.After this explanation will be omitted, because it is identical with the receiving equipment of narrating above 30.Therefore, if the present invention is applied to wireless communication system, this system piles up the information that will send on the phase difference of a plurality of carrier waves but also randomization loads the frequency channels of a plurality of carrier waves, can obtain the effect identical with above-mentioned situation.
In addition, the foregoing description has related to the situation of the wireless communication system that applies the present invention to the TDMA scheme.But, the invention is not restricted to this, but also be widely used in wireless communication system, suppose in such system, send signal and after being transformed to time slot, send.In this case, as a receiving equipment, if this equipment receiving system, weighting device and decoding device may be just enough, this receiving system is used for receiving transmission signal and this received signal of output, this weighting device multiply by described weight coefficient and exports it according to the weight coefficient of the time slot reliability of calculating expression transmission received signal from the described received signal of this receiving system transmission with this received signal, and this decoding device is used to decode from this weighting device received signal that sends and the data of recovering this transmission.
According to aforesaid the present invention, owing to calculate the weight coefficient of expression time slot reliability and the received signal that decoding is multiplied by described weight coefficient, when in this decoding device, adding the reliability of time slot, can obtain the maximum likelihood sequencal estimation, therefore, even under the situation that communication quality changes with time slot, when having high-precision maximum likelihood sequencal estimation, the data of transmission can be recovered accurately.
Though here narrate in conjunction with the preferred embodiments of the present invention, but purpose is in appending claims to cover the institute that falls in true spirit of the present invention and the scope and changes and revise, this various changes and to revise for those skilled in the art be conspicuous.
Claims (23)
1. be used to receive the method for reseptance of the signal that constitutes by one group of predetermined information unit, comprise step:
Receive described signal;
Calculate one group of weight coefficient, this group each coefficient in weight coefficient corresponding to shown in the reliability of each information unit in one group of predetermined information unit;
Utilize the weight coefficient of described correspondence to come each information unit in the described one group of predetermined information unit of weighting; With
Decode each information unit that is weighted in described one group of predetermined information unit.
2. according to the method for reseptance of claim 1, wherein:
The described signal that is made of one group of predetermined information unit is the signal of TDMA method, and described predetermined information unit is a time slot.
3. according to the method for reseptance of claim 1, wherein:
The described signal that is made of one group of predetermined information unit is the signal of multicarrier method, and described predetermined information unit is a subcarrier or a plurality of subcarrier.
4. according to the method for reseptance of claim 3, wherein:
The signal of described multicarrier method also is divided at time orientation, and described predetermined information unit is a scheduled time part of a subcarrier or a plurality of subcarriers.
5. according to the method for reseptance of claim 1, wherein:
Described weighting is multiplied each other by described weight coefficient and described received signal and is carried out, and described decoding is a soft decision decoding.
6. according to the method for reseptance of claim 1, wherein:
Described weight coefficient utilizes the ratio of the value of relevant signal power and noise power to calculate.
7. according to the method for reseptance of claim 6, wherein:
Described ratio utilizes the degree of the phase deviation of this received signal to calculate.
8. be used to receive the receiving equipment of the signal that constitutes by one group of predetermined information unit, comprise:
Be used to receive the receiving system of described signal;
The weight coefficient calculation element is used to calculate one group of weight coefficient, and this group each coefficient in weight coefficient is corresponding to the reliability of each information unit from one group of predetermined information unit shown in the described receiving system output;
Weighting device utilizes corresponding weight coefficient to come weighting each information unit from the described predetermined information unit of described receiving system output; With
Decoding device is used for decoding from each information unit of described one group of predetermined information unit of described weighting device output.
9. receiving equipment according to Claim 8, wherein:
The signal that is made of one group of predetermined information unit is the signal of TDMA method, and described predetermined information unit is a time slot.
10. receiving equipment according to Claim 8, wherein:
The described signal that is made of one group of predetermined information unit is the signal of multicarrier method, and described predetermined information unit is a subcarrier or a plurality of subcarrier.
11 receiving equipments according to claim 10, wherein:
The signal of described multicarrier method also is divided at time orientation, and described predetermined information unit is a scheduled time part of a predetermined subcarrier or a plurality of subcarriers.
12. receiving equipment according to Claim 8, wherein:
Described weighting is multiplied each other by described weight coefficient and described received signal and is carried out, and described decoding is a soft decision decoding.
13. receiving equipment according to Claim 8, wherein:
Described weight coefficient utilizes the ratio of the value of relevant signal power and noise power to calculate.
14. according to the receiving equipment of claim 13, wherein:
Described ratio utilizes the degree of the phase deviation of this received signal to calculate.
15. receiving equipment according to Claim 8, wherein:
Described receiving system comprise execution will be when sending randomly the phase signal of displacement be displaced to a part of the processing of opposite phase.
16. according to the receiving equipment of claim 12, wherein:
Described soft decision decoding is a Veterbi decoding.
17. according to the receiving equipment of claim 13, wherein:
About the described calculating of the ratio of the value of signal power and noise power is carried out as a signal component about the difference between undelayed signal and the signal that postponed.
18. according to the receiving equipment of claim 13, wherein:
About the described calculating of the ratio of the value of described signal power and noise power about average level and at present the difference between the level carry out as a signal component.
19. according to the receiving equipment of claim 14, wherein:
Described phase deviation degree is to utilize according to the range weight of first component of the quadrature component of this restituted signal and second component and power component calculates that this departs from calculating.
20. according to the receiving equipment of claim 19, wherein:
Described quadrature component is an i/q signal.
21. according to the receiving equipment of claim 19, wherein:
Described quadrature component is polar r/ θ component signal.
22. according to the receiving equipment of claim 19, wherein:
Described phase deviation degree utilizes the comparison of the deviation value of described first component and second component to calculate.
23. according to the receiving equipment of claim 22, wherein:
In the calculating of described weight coefficient, the noise power of each code element deducts from the power of the received signal of each code element, so that obtain pure signal power.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6706297 | 1997-03-19 | ||
| JP67062/97 | 1997-03-19 | ||
| JP144289/97 | 1997-06-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1204189A CN1204189A (en) | 1999-01-06 |
| CN1242568C true CN1242568C (en) | 2006-02-15 |
Family
ID=5220058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 98109758 Expired - Fee Related CN1242568C (en) | 1997-03-19 | 1998-03-19 | Receiving device and signal receiving method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1242568C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8656243B2 (en) | 2010-01-13 | 2014-02-18 | Intel Mobile Communications GmbH | Radio receiver and method for channel estimation |
| US8660167B2 (en) * | 2010-01-25 | 2014-02-25 | Intel Mobile Communications GmbH | Device and method for distortion-robust decoding |
| WO2018051622A1 (en) * | 2016-09-15 | 2018-03-22 | ソニーセミコンダクタソリューションズ株式会社 | Transmitting device, and system |
-
1998
- 1998-03-19 CN CN 98109758 patent/CN1242568C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1204189A (en) | 1999-01-06 |
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