CN1239981C - Electric power saving method for computer image system - Google Patents
Electric power saving method for computer image system Download PDFInfo
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- CN1239981C CN1239981C CN 02142711 CN02142711A CN1239981C CN 1239981 C CN1239981 C CN 1239981C CN 02142711 CN02142711 CN 02142711 CN 02142711 A CN02142711 A CN 02142711A CN 1239981 C CN1239981 C CN 1239981C
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Abstract
The present invention relates to a power saving method for computer image systems, which is applicable to computer image systems with specific operating frequencies. The present invention comprises the steps that a first period comprising the starting time to the end time of the current image is obtained; the first period is compared with the preset picture time of the computer image system; when the first period is shorter than the preset picture time of the computer image system, the operating frequency of the computer image system is reduced from the time when all the pictures are ended in the first period to the time when the preset picture time is ended.
Description
Technical field
The invention relates to a kind of electric energy saving method of computer video system, particularly relevant for the electric energy saving method of computer video system of a kind of use picture speed (frame rate) control technology.
Background technology
The CMOS technology is the advantage technology of high-effect digital circuit.Owing to grow up day by day in the market of portable device, the design of low power consumption is important in gradually to satisfy the operation usefulness of portable device.In the Synchronization Design of the most HDL of tradition, system's clock pulse is the clock pulse input end that is electrically connected to each flip-flop.And the consumption of electric power mainly is to occur in following three kinds of situations:
(1) about 85% power consumption is when switch switches, and this moment, electric power mainly consumed at the charge and discharge process to gate electric capacity, and represented gate effectively to move.
(2) about 15% power consumption is when short circuit, when the position of input current potential circle in the middle of high low level of gate punctual, but P type and the conducting of N type network, the short circuit paths between the formation Vdd to Vss.
(3) about power consumption below 1% betides the leakage current of transistor network when closed condition at leakage current, so this leakage current in traditional program generally be considered as insignificant.
Clock pulse gating technique (clock-gating) can effectively reduce tandem circuit power consumption.Use as the mode of sleep pattern and the minimum activation of the wafer of conducting can be avoided meaningless circuit clock pulse operation.As shown in Figure 1, clock pulse generator 10 is to be coupled to the quartz (controlled) oscillator 12 with an output enable pin, and the output enable pin can be used for avoiding circuit to be driven by clock pulse before output usefulness.Circuit among Fig. 1 comprises the frequency generator with an output enable signal, when output enable signal is low level " 0 ", can close the input clock pulse.
Clock pulse is fixed to be another known minimizing power consumption technology than technology (clock scaling).Dynamic clock pulse is surely than making clock pulse generator change the input clock pulse speed of a function circuit.Because energy consumption is and square being directly proportional of clock pulse frequency and operating voltage that circuit has low more consumed power under low more clock pulse speed.Generally speaking, clock pulse is fixed opportunity of using than technology when circuit does not require that at this moment clock pulse efficient or power consumption are main consideration.
Low consumption electric power and low-energy-consumption will be the demands of many real time operations.For example, the image frame of decoding must finish in the time that limits.If make decoded picture by chance when the time limit finishes, be played on the screen, can economize the consumption of saving electric power with lower speed display frame.Because user and can't differentiate the difference in 10ms to 20ms reaction time, therefore can manage frequency or voltage and the picture adopting lower speed or finish broadcast when the 20ms reaches the effect of power saving in conjunction with the lower.
It is complicated day by day that the image chip of computer system becomes because of the function that the 3D image quickens.This complicated structure need be used the clock pulse of more transistor and high frequency in integrated circuit.Therefore, the power consumption of wafer is higher.So, need a kind of image chip that can carry out electricity-saving function according to application demand.
Summary of the invention
In view of this, in order to address the above problem, fundamental purpose of the present invention is to provide a kind of method that reduces image chip power consumption, and utilization clock pulse gating technique is avoided extra power wastage with clock pulse is fixed than technology.
For obtaining above-mentioned purpose, the present invention proposes a kind of electric energy saving method of computer video system, comprises the following steps: at first to obtain the zero-time that comprises present picture first period to the concluding time; Next, the default image time of first period and a computer image system relatively, when be shorter than default image time first period, the computer image system was at each picture anergy when finish to default image time end first period.
In addition, the present invention proposes a kind of electric energy saving method of computer video system, is applicable to the computer image system with special operating frequency, comprises the following steps: at first to obtain the zero-time that comprises present picture first period to the concluding time; Next, the default image time of first period and computer image system relatively when be shorter than default image time first period, reduces the operating frequency of above-mentioned computer image system when finish to above-mentioned default image time end first period at each picture.
Description of drawings
Fig. 1 is the circuit diagram that shows traditional clock pulse gating circuit;
Fig. 2 is the calcspar that shows traditional 3D flow for displaying;
Fig. 3 is the simple view that shows traditional computer image system;
Fig. 4 is the operational flowchart that shows according to computer image of the present invention system electricity saving method;
Fig. 5 is the operational flowchart that shows the program of adjusting according to the described processing power of first embodiment of the invention;
Fig. 6 is the operational flowchart that shows the program of adjusting according to the described processing power of second embodiment of the invention.
The figure number explanation
The 10-clock pulse generator;
The 12-quartz (controlled) oscillator;
The 20-3D application program;
22-image processing storehouse;
The 24-pel;
26-display device drive software;
28-image accelerator;
The 30-screen;
The 32-controller;
The 34-shadow memory;
36-image accelerator;
361-hardware instruction table;
362-video conversion engine;
The 363-Memory Controller.
Embodiment
Fig. 2 is the calcspar that shows traditional 3D flow for displaying.In traditional 3D flow for displaying, 3D application program 20 is used specific 3D image processing storehouse (graphic libraries) 22, and for example Direct3D or Open GL etc. are with the display effect of design 3D image.Image processing storehouse 22 is converted to the 3D object pel 24 (primitive) of additional picture characteristics.The 3D object is to be converted to the screen coordinate that definition is projeced into the position of screen by the coordinate that defines object.Next, display device drive software 26 will have pel 24 outputs of the specific hardware instruction that drives image accelerator 28, to produce the image that desire shows in screen 30.
Fig. 3 is the simple view that shows traditional computer image system.The computer image system comprises a controller 32, a shadow memory 34 and an image accelerator 36.Image accelerator 36 couples controller 32 and shadow memory 34 via system bus and memory bus.Image accelerator 36 receives the instruction that controller 32 is exported, and the image data that is shown in display is controlled in it processing back.Image accelerator 36 comprises hardware instruction table (queue) 361, video conversion engine 3 62 and a Memory Controller 363.Hardware instruction table 361 is a cell fifo, in order to store the instruction data via controller that system bus is received from 32.Video conversion engine 3 62 receives and handles and is stored in the instruction of hardware instruction table 361 and Memory Controller 363 and via memory bus access Memory Controller 363.
Method provided by the present invention is to select the processing power of image chip according to the picture speed of expection.When circuit does not require that at this moment clock pulse efficient or power consumption are main consideration, can reduce the processing power of wafer in good time.For example, perhaps per second 30 frame numbers are applicable to does not need the application program of demonstration fast.In addition, if display frame and uncomplicated, need not handle the shown picture of Power Processing with height this moment.According to the above, Fig. 4 is the operational flowchart that shows according to computer image of the present invention system electricity saving method.At this, the picture speed of expection is default set value.For example, on behalf of each picture, per second 50 frame numbers need 20ms consuming time.
Consult Fig. 4, at first carry out and read the actual video conversion time S1 of detecting with the assessment picture.Can carry out the above-mentioned detecting of reading by the display device drive software.Generally speaking, the display device drive software reads the state of video conversion engine and judges whether the image in the shadow memory is complete, that is the video conversion engine is an armed state.If not, then display device drive software continuation detecting is an armed state up to the video conversion engine.Thus, the display device drive software is assessed the actual displayed time of present picture.Same, the video conversion engine also can be assessed the actual converted time of present picture by the execution accumulation conversion present picture required time of all pels.Next, carry out processing power and choose the time for reading S2 of flow process with relatively more default image time and present picture.At this, default image time is to set by the user or according to the restriction of hardware, and the time for reading of picture is the actual video conversion time of calculating gained in step S1 at present.If the time for reading of picture is lower than default image time at present, carries out processing power and adjust program to reduce the employed power S3 of video conversion engine.According to the embodiment of the invention, processing power adjustment program is that utilization clock pulse gating technique is reached than technology with clock pulse is fixed.
First embodiment:
Fig. 5 is the operational flowchart that shows the program of adjusting according to the described processing power of first embodiment of the invention.At first, obtain the zero-time S21 of present picture.Then, begin to change present picture S22.After picture conversion, can obtain the concluding time S23 of present picture.According to the concluding time with present picture deduct zero-time get final product the time for reading S24 of picture up till now.That is the difference between the concluding time of the zero-time of picture and present picture is the time for reading of present picture at present.Next, with the time for reading of present picture and the default image time S25 that makes comparisons, if the time for reading of picture is lower than default image time at present, then calculate gating time (gating time) and during gating time, close the input clock pulse S26 of video conversion engine, make it enter sleep state (sleepmode).At this, gating time is poor between the time for reading of present picture and the default image time.Next, whether the assessment gating time is greater than zero S27.If gating time is non-vanishing, then continue to reduce gating time S28, get back to step S27 then, rejudge the remaining time of gating time.At this, the gating time of minimizing is the clock pulse time of system.If gating time has been reduced to zero, then gets back to step S21 and check next picture.By above-mentioned gating technique, in the time of can exceeding the usefulness of needs at the processing power of video conversion engine, force the video conversion engine to enter sleep state to save electric power.
Second embodiment:
Fig. 6 is the operational flowchart that shows the program of adjusting according to the described processing power of second embodiment of the invention.At first, obtain the zero-time S31 of present picture.Then, begin to change present picture S32.After picture conversion, can obtain the concluding time S33 of present picture.According to the concluding time with present picture deduct zero-time get final product the time for reading S34 of picture up till now.That is the difference between the concluding time of the zero-time of picture and present picture is the time for reading of present picture at present.
Fig. 6 is the different of processing power adjustment program with the difference of Fig. 5.As described in Figure 6, utilize clock pulse fixed than technology with the time for reading of present picture divided by default image time S35 to obtain clock pulse ratio (clock-scale-factor).And making present input clock pulse frequency into, the clock pulse frequency of video conversion engine is multiplied by clock pulse ratio S36.If this moment last picture time for reading less than default image time, then the clock pulse ratio is the value less than, thus the video conversion engine when next picture, it is imported clock pulse frequency and reduces because being multiplied by the clock pulse ratio.If this moment, the time for reading of last picture was higher than default image time, then the input clock pulse frequency of video conversion engine when next picture will improve, till reaching maximum input clock pulse frequency.
Fixed by above-mentioned clock pulse than technology, but the operating frequency of dynamic translation video conversion engine is with when its processing power exceeds the usefulness of needs, by reducing operating frequency to reach the purpose of saving electric power.
Claims (10)
1. an electric energy saving method of computer video system comprises the following steps:
Obtain the zero-time that comprises a picture first period to the concluding time;
The default image time of more above-mentioned first period and a computer image system; And
If the time for reading of picture is lower than default image time, calculate gating time and during gating time, close the input clock pulse of video conversion engine, make it enter sleep state; Gating time is the poor of the time for reading of present picture and default image time; And whether the assessment gating time, then continues to select to reduce gating time, remaining time of the gating time of reappraising again if non-vanishing greater than zero; The gating time that reduces is the clock pulse time of system, if gating time is reduced to zero, then checks next picture.
2. electric energy saving method of computer video system according to claim 1 is characterized in that: above-mentioned default image time is to be set by the user.
3. electric energy saving method of computer video system according to claim 1 is characterized in that: above-mentioned default image time is that the hsrdware requirements by above-mentioned computer image system are determined.
4. electric energy saving method of computer video system according to claim 1 is characterized in that: above-mentioned computer image system is the video conversion engine.
5. electric energy saving method of computer video system according to claim 1 is characterized in that: above-mentioned computer image system utilizes clock pulse gating technique anergy.
6. an electric energy saving method of computer video system is applicable to that one has the computer image system of an operating frequency, comprises the following steps:
Obtain the zero-time that comprises a picture first period to the concluding time;
The default image time of more above-mentioned first period and above-mentioned computer image system; And
When be shorter than above-mentioned default image time above-mentioned first period, utilize clock pulse fixed than technology with the time for reading of present picture divided by default image time to obtain the clock pulse ratio; And making present input clock pulse frequency into, the clock pulse frequency of video conversion engine is multiplied by the clock pulse ratio; If the time for reading of last picture is less than default image time at this moment, then the clock pulse ratio is the value less than, reduces because being multiplied by the clock pulse ratio so the video conversion engine when next picture, is imported the clock pulse frequency; If this moment, the time for reading of last picture was higher than default image time, then the input clock pulse frequency of video conversion engine when next picture will improve, till reaching maximum input clock pulse frequency.
7. electric energy saving method of computer video system according to claim 6 is characterized in that: above-mentioned default image time is to be set by the user.
8. electric energy saving method of computer video system according to claim 6 is characterized in that: above-mentioned default image time is that the hsrdware requirements by above-mentioned computer image system are determined.
9. electric energy saving method of computer video system according to claim 6 is characterized in that: above-mentioned computer image system is the video conversion engine.
10. electric energy saving method of computer video system according to claim 6 is characterized in that: above-mentioned computer image system utilizes that clock pulse is fixed to reduce operating frequency than technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142711 CN1239981C (en) | 2002-09-18 | 2002-09-18 | Electric power saving method for computer image system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142711 CN1239981C (en) | 2002-09-18 | 2002-09-18 | Electric power saving method for computer image system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1484126A CN1484126A (en) | 2004-03-24 |
| CN1239981C true CN1239981C (en) | 2006-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02142711 Expired - Fee Related CN1239981C (en) | 2002-09-18 | 2002-09-18 | Electric power saving method for computer image system |
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| Country | Link |
|---|---|
| CN (1) | CN1239981C (en) |
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2002
- 2002-09-18 CN CN 02142711 patent/CN1239981C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1484126A (en) | 2004-03-24 |
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