CN1238897C - Semiconductor device and its mfg. method - Google Patents

Semiconductor device and its mfg. method Download PDF

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Publication number
CN1238897C
CN1238897C CN 98125104 CN98125104A CN1238897C CN 1238897 C CN1238897 C CN 1238897C CN 98125104 CN98125104 CN 98125104 CN 98125104 A CN98125104 A CN 98125104A CN 1238897 C CN1238897 C CN 1238897C
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CN
China
Prior art keywords
mentioned
semiconductor chip
semiconductor device
resin
wiring
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Expired - Fee Related
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CN 98125104
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Chinese (zh)
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CN1221982A (en
Inventor
宫田修
柴田和孝
上田茂幸
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Rohm Co Ltd
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Rohm Co Ltd
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Publication of CN1221982A publication Critical patent/CN1221982A/en
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Publication of CN1238897C publication Critical patent/CN1238897C/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

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  • Wire Bonding (AREA)
  • Micromachines (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device comprising a film substrate and a semiconductor chip bonded to an upper surface of the film substrate is provided. The semiconductor chip has a main surface formed with a plurality of terminal pads. The film substrate has a lower surface formed with a plurality of external terminal portions in a matrix pattern, and an upper surface formed with a plurality of wiring patterns for respectively connecting with the external terminal portions. The wiring patterns formed in the upper surface of the film substrate are respectively connected to the terminal pads formed on the main surface of the semiconductor chip.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, specifically, be a kind of have make the package dimension miniaturization, formed the semiconductor device and the manufacture methods thereof that are used for the form of the outside terminals that connect by rectangular side by side a plurality of in the bottom surface of this encapsulation.
Background technology
Have that BGA (Ball Grid Array) encapsulates or the semiconductor device that is called the packing forms of subregion array package is to have to form by rectangular side by side a plurality of to be used for outside terminal portions that connects and the essential structure of disposing semiconductor chip at the insulating base superimposed layer on the bottom surface.In the past, the common stiff baseplate of being made up of glass epoxy resin that adopts was as insulating base.This stiff baseplate is except being equipped with being used for the outside terminal portions that connects by rectangular side by side a plurality of of being made up of soldered ball in its bottom surface, in addition, also being formed with the pattern that is used for the outside terminal portions conducting that is connected with each and each terminal pad that makes semiconductor chip and each are used for the terminal portions conducting that the outside is connected in its surface connects up.Be used for the outside following formation of terminal portions that connects: on insulating base, be provided with by rectangular a plurality of holes side by side, make one of the wiring of each pattern position, bottom surface from base plate in the hole of correspondence, the part of scolder will be connected up with pattern be connected.Thus, formed and the pattern on insulating base surface wiring conducting, and protrude ormal weight from the bottom surface of insulating base flange shape be used for the outside terminal portions that connects.Because of as above formed a plurality of be used for the outside terminal portions that connects in the bottom surface of encapsulation by side by side rectangular, make package dimension diminish, therefore, this semiconductor device becomes applicable to the high-density installation to main printed circuit board.
, adopt the stiff baseplate formed by glass epoxy resin insulating base because of above-mentioned semiconductor device in the past, have the problem of following this solution as semiconductor chip stack.
1st, it is bigger than normal that the thickness of stiff baseplate accounts for the ratio of whole semiconductor device thickness, this semiconductor device is restricted in the miniaturization of thickness direction, and weight reduction also is restricted.
The 2nd, the stiff baseplate of glass epoxy resin system and the coefficient of thermal expansion of semiconductor chip differ bigger, therefore, and when on main printed circuit board, semiconductor device being installed, because of the influence of being heated, mechanical engagement may take place between semiconductor chip and insulating base come off or electrically connect interruption.
3rd,, be difficult to make the configuration density that is used for the outside terminal portions that connects that should dispose to be higher than the density of regulation in the bottom surface of this stiff baseplate because of stiff baseplate has suitable thickness.Specifically, as mentioned above, this be used for outside terminal portions that connects be by the hole of on insulating base, being opened pack into soldered ball, heat these soldered balls and make it to form with pattern wire-bonded above the hole.Therefore, be to form the outside terminal portions that connects that is used for of the shape of protruding ormal weight from the bottom surface of insulating base, the Kong Yaoda that this is opened on insulating base is a little, and the soldered ball that will adorn in this hole is also wanted greatly.Therefore, can't improve the configuration density that this is used for the outside terminal portions that connects, this can't fully satisfy the requirement of high-density installation with regard to meaning that the number of terminals for constituting the spendable semiconductor chip of this semiconductor device is limited.But also having increased the use amount of scolder, this can produce the problem that cost increases.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of semiconductor device, this device possesses the bottom surface that has in encapsulation and is used for the form of the outside terminal portions that connects by rectangular configuration, and can be so that in size miniaturization more, lightweight at thickness direction.
Another object of the present invention is to provide a kind of semiconductor device, and it possesses the form that is used for the outside terminal portions that connects in the bottom surface of encapsulation by rectangular configuration is arranged, and can the use side subnumber more semiconductor chip is as built-in semiconductor chip.
Another purpose that the present invention also has is to provide a kind of method of more effectively making semiconductor device, possess the form that is used for the outside terminal portions that connects in the bottom surface of encapsulation by rectangular configuration is arranged, and can be so that in size miniaturization more, lightweight at thickness direction, perhaps can the use side subnumber more semiconductor chip is as built-in semiconductor chip.
The invention provides a kind of semiconductor device with following formation.
Specifically, this semiconductor device comprises: the film base plate, it has the surface that has formed the wiring of a plurality of patterns and has formed a plurality of bottom surfaces that are used for the outside terminal portions that connects, these are a plurality of be used for outside terminal portions that connect be configured to rectangular and with above-mentioned pattern wiring conducting; Semiconductor chip, its have the interarea that is provided with a plurality of flange shape terminal pads and with this interarea opposite surfaces, above-mentioned flange shape terminal pad is to be carried on the above-mentioned film base plate with state that above-mentioned pattern wiring is faced mutually; And articulamentum, it is made of the heterogeneity electroconductive binder of having sneaked into conductive compositions in the insulative resin composition, be set between above-mentioned semiconductor chip and the above-mentioned film base plate, above-mentioned semiconductor chip mechanicalness is bonded on the above-mentioned film substrate, and allows above-mentioned flange shape terminal pad be electrically connected with above-mentioned pattern wiring.
The film base plate that be fit to use is such as being the pattern wiring with material systems such as copper that forms the paper tinsel shape on thickness is tens of microns the base material of polyimide film.This base plate is because of being membranaceous, so flexible.This semiconductor device is aforesaid membranaceous because of its insulating base, therefore, compares integral thickness with example in the past and has shortened quite a lot ofly, and weight has also alleviated.And the configuration that can be used in the outside terminal portions that connects is more intensive.Also have,,, when semiconductor device is installed, also can not make semiconductor chip come off because of the influence of suffered heat from base plate even if the coefficient of thermal expansion of this base plate and semiconductor chip has difference because of base plate is membranaceous.
For the film base plate, semiconductor chip engages in ventricumbent mode.In this case, each terminal pad of semiconductor chip interarea partly directly with the pattern of film base plate wiring conducting, thereby the semiconductor chip interarea is covered by the film base plate, therefore, there is no need with resin-encapsulated chip integral body to be sealed.So the plane sizes of the semiconductor device of this embodiment is big or small identical with semiconductor chip basically.
Film base plate and adding heterogeneity conductive plate or heterogeneity electroconductive binder on this base plate between the interarea semiconductor chip in opposite directions, just mutually extruding between the two under heated condition reasonably also makes in the conducting between the pattern wiring of terminal pad on making semiconductor chip and film base plate and finishes mechanical joint between the two.
In desirable embodiment, above-mentioned each is used for the outside following formation of terminal portions that connects: soldered ball is loaded into to allowing the part position of above-mentioned pattern wiring just before hole that the bottom surface of film base plate one side forms on the film base plate, the part of above-mentioned soldered ball is protruded from the bottom surface of film base plate, and above-mentioned soldered ball is connected with above-mentioned pattern wiring fusion.
Because of base plate is membranaceous, in the pattern wiring conducting on making this base plate, the soldered ball that is used for the outside terminal portions that connects that formation is protruded ormal weight from the bottom surface of base plate is diminished, and, the hole of this soldered ball of filling is diminished.Therefore, can dispose this thick and fast and be used for the outside terminal portions that connects.And this means can the more semiconductor chip of use side subnumber.
Also have, in desirable embodiment, can also be with the adhesive that contains porous resin as above-mentioned heterogeneity electroconductive binder.
Because of contain porous resin in above-mentioned heterogeneity electroconductive binder, self just has porousness the heterogeneity electroconductive binder, and gas permeability is very good.Therefore, even if contain in the inside of above-mentioned heterogeneity electroconductive binder under the state of moisture or bubble and heated the heterogeneity electroconductive binder, volumetric expansion moisture or the bubble that the swollen inside that also can not remain in the heterogeneity electroconductive binder, these can be discharged to the outside of heterogeneity electroconductive binder.That is to say, even if under to the semiconductor chip and the heated situation of film base plate that connect by above-mentioned heterogeneity electroconductive binder, also swelling of volumetric expansion that can be by moisture and bubble produces the stress that stress or generation make semiconductor chip separate with the film base plate to semiconductor chip.
Also have, in desirable embodiment, around the above-mentioned heterogeneity electroconductive binder and above-mentioned semiconductor chip around by the protection resin round.
In this embodiment, because of around the bonding part between semiconductor chip and membranaceous base plate (heterogeneity electroconductive binder) by the protection resin round, can avoid impurity to intrude into above-mentioned bonding part (heterogeneity electroconductive binder in).And, owing to be protected around, semiconductor chip by the protection resin around the semiconductor chip, make semiconductor chip strengthen to the resistance of external force.Certainly, can adopt the thing that contains porous resin as above-mentioned protection resin, in the case, can be because of the aeration that influences above-mentioned heterogeneity electroconductive binder on every side that is trapped among above-mentioned heterogeneity electroconductive binder by the protection resin.
Also have, in desirable embodiment, above-mentioned protection resin can enclose the surface of above-mentioned semiconductor chip.
If do like this, in the bight on semiconductor chip top just by the protection resin round and be protected.Therefore, even if under the state of bare chip semiconductor chip is being bonded on the above-mentioned film base plate, can when operation, not make semiconductor chip damaged because of the external force effect yet.
Also have, in desirable embodiment, above-mentioned porous resin can use the heat-curing resin of phenolic.And, contain phenolic resins in the heat-curing resin of said phenolic here or be the epoxy resin of raw material with the phenolic.
Also have, in desirable embodiment, the terminal pad that is used for outside terminal portions that connects and the semiconductor chip that is connected with the other end conduction of above-mentioned pattern wiring that is connected with the end conduction of above-mentioned pattern wiring is dislocation mutually at vertical view.
In desirable embodiment, each terminal pad of semiconductor chip is provided in the periphery of semiconductor chip outside, on the other hand, from overlooking, be to set by rectangular with each terminal portions that is used for outside connection that each terminal pad conduction is connected in zone than above-mentioned each terminal pad inside by the pattern wiring.
Also have, in desirable embodiment, above-mentioned membranaceous base plate lip-deep each pattern wiring in, except with each terminal pad of semiconductor chip in opposite directions and with zone that each terminal pad conduction is connected a part or whole zone formation alpha ray shielding dielectric film.Under the more satisfactory situation, above-mentioned alpha ray shielding dielectric film at least will each be used for the outside terminal portions that connects directly over the zone on form.Also have, this alpha ray shielding dielectric film is such as being formed by polyimide resin.
In this embodiment, forms by the scolder of leaded (Pb) even if be used for the outside terminal portions that connects, semiconductor chip also not can because of from the alpha ray of this external cabling end generation by exposure.
Also have, in desirable embodiment, above-mentioned semiconductor chip is the storage chip with memory cell areas.
Also have, in other desirable embodiment, allow the surface of above-mentioned semiconductor chip reveal the outside in fact, and, in part or all formation chamfering of this surperficial edge part.
Specifically, in this embodiment, remove in advance on the semiconductor chip because of the easy damaged part of external force effect.Therefore, even if there is what external force to act on the semiconductor chip, the possibility of semiconductor chip damaged is also low.Therefore, in the semiconductor device relevant, there is no need to seal semiconductor chip and form resin-encapsulated for the protection semiconductor chip with this embodiment, all favourable from operating efficiency and cost.
Also have, in other desirable embodiment, in fact allow the surface of above-mentioned semiconductor chip reveal the outside, simultaneously, form on the surface of this chip small concavo-convex, and, by enclosing sign on the surface that is printed on this chip.This is fine concavo-convex such as forming by the centre plane roughness about 2～5 μ m.
Also have, in desirable embodiment, the surface of above-mentioned semiconductor chip (face of interarea and opposition side) covers by resin molding, and, enclose mark printed on the surface of this resin molding.
Also have, in other desirable embodiment, allow the interarea of above-mentioned semiconductor chip upwards be bonded on above-mentioned membranaceous base plate above, simultaneously, each pattern wiring of above-mentioned membranaceous base plate has the wire bond pad of guiding this membranaceous bottom edge portion into, and each terminal pad of above-mentioned semiconductor chip is to be connected with above-mentioned pattern wiring conduction by the lead-in wire that connects this terminal pad and above-mentioned wire bond pad.
Also have, in this embodiment, the surface of above-mentioned membranaceous base plate, above-mentioned semiconductor chip and above-mentioned lead-in wire are all sealed by resin-encapsulated.
In the semiconductor device relevant with this embodiment, though semiconductor chip is sealed by resin-encapsulated, but semiconductor chip is to be bonded on the surface of membranaceous base plate, and, because of exposing the bottom surface of membranaceous base plate, the size of the thickness direction of encapsulation is littler than the semiconductor device of common resin-encapsulated type.And, on the bottom surface of the membranaceous base plate that exposes, be used for the outside terminal portions that connects by stem for stem rectangular, can the many semiconductor chips of use side subnumber, and the semiconductor device plane sizes is also much smaller than the semiconductor device of common resin-encapsulated type.
Also have, in the semiconductor device relevant, comprising the frame shape reinforcement material that surrounds above-mentioned semiconductor chip in the above-mentioned resin-encapsulated with this embodiment.
Thus, improved semiconductor chip so that to the protective value of the lead-in wire that connects semiconductor chip and membranaceous base plate.
The invention provides a kind of following method, can make efficiently have semiconductor chip be bonded on the structure on the membranaceous base plate semiconductor device and and above-mentioned relevant semiconductor device of the present invention.
Specifically, this method is characterised in that uses a kind of film circuit board, this film circuit board has surface and bottom surface, on a direction, form strip, the a plurality of wiring region that are separated from each other are set on the long axis direction of this circuit board, on each wiring region, form and be configured to rectangular a plurality of through holes, form a plurality of pattern wirings above the wiring region at each, the part of each pattern wiring is clogged corresponding in an above-mentioned a plurality of through hole through hole, and this manufacture method comprises: add the 1st operation that has towards the rigidity reinforcement material of a plurality of fenestras of above-mentioned a plurality of wiring region on the above-mentioned surface of above-mentioned film circuit board; In the bond semiconductor chip, conduction connects the 2nd operation of the above-mentioned pattern wiring of semiconductor chip and each wiring region on the surface of each wiring region; In above-mentioned each through hole from each wiring region of bottom surface direction of above-mentioned film circuit board, load in the soldered ball, by the part of this soldered ball is connected with above-mentioned pattern wiring fusion, on the bottom surface of each wiring region, form outstanding the 3rd operation that is used for the outside terminal portions that connects; With downcut the part corresponding from above-mentioned film circuit board, the 4th operation of acquisition unit semiconductor device with above-mentioned wiring region.
According to such method, guarantee to comprise this rigidity reinforcement material and reach desired rigidity by adding above-mentioned rigidity reinforcement material in interior circuit board integral body, and, because each wiring region of this processing in above-mentioned film base plate is exposed, can carry circuit board integral body on one side automatically, prevent the bending of circuit board on one side, each operation is undertaken by desirable sample.Therefore, with having added the circuit board of above-mentioned rigidity reinforcement material, having utilized the production line of existing manufacturing to make that manufacturing becomes possibility with the relevant semiconductor device of the invention described above efficiently again from the guiding frame to semiconductor device.
And this method can be made the relevant various forms of semiconductor devices with the invention described above.Specifically, have semiconductor chip is made its interarea be bonded on the form of the structure on the film base plate downwards, its interarea upwards is bonded on the film base plate and the pattern of the terminal pad that connects interarea by lead-in wire and film base plate connects up, and the form of the structure of the surface of membranaceous base plate to semiconductor chip all being sealed by resin-encapsulated.
In desirable embodiment, adopt resin-encapsulated that the above-mentioned surface of each wiring region is sealed with the above-mentioned semiconductor chip that is bonded on this surface.
In desirable embodiment, above-mentioned manufacture method further comprises: carry out the operation of installing frame shape reinforcement material on above-mentioned each wiring region between above-mentioned the 1st operation and above-mentioned the 2nd operation; And between above-mentioned the 2nd operation and above-mentioned the 3rd operation, carry out the operation that adopts resin-encapsulated that the above-mentioned surface of each wiring region, the above-mentioned semiconductor chip that is bonded on this surface and above-mentioned frame shape reinforcement material are sealed.
The reinforcement material of desirable above-mentioned frame shape is to be formed by the material resin identical with the resin that forms above-mentioned resin-encapsulated.
Like this, the face rigidity facing to the wiring region of the fenestra of rigidity reinforcement material is further enhanced in the film circuit board.Therefore, even if crooked stress in each wiring region of film circuit board, the reinforcement material by this frame shape can tackle bending stress.Therefore, when heating in the above-mentioned semiconductor chip of wire bond and in the resin-encapsulated operation, can avoid above-mentioned film circuit board to deform, can also avoid mechanical engagement between semiconductor chip and the film base plate and conductive bond are produced adverse influence.And, be to be enclosed on the semiconductor chip as the reinforcement material of the resin-encapsulated inside casing shape of the semiconductor device of goods, improved protective value to the semiconductor chip of resin-encapsulated.
The invention provides a kind of framework that is used to make semiconductor device, be used for relevant method with the invention described above with following formation.
Specifically, this framework that is used to make semiconductor device is characterized in that having:
The film circuit board, have surface and bottom surface, on a direction, form strip, the a plurality of wiring region that are separated from each other are set on the long axis direction of this circuit board, on each wiring region, form and be configured to rectangular a plurality of through holes, form a plurality of pattern wirings above the wiring region, the part of each pattern wiring is clogged corresponding in an above-mentioned a plurality of through hole through hole at each; With the rigidity reinforcement material, be added to the above-mentioned surface of above-mentioned film circuit board, and be formed with towards above-mentioned a plurality of wiring region and on the position a plurality of fenestras corresponding with these wiring region.
As described in the method for the invention, by using this to be used to make the framework of semiconductor device, can make semiconductor device efficiently, and avoid producing adverse factors with essential structure of bond semiconductor chip on the surface of film base plate.
Description of drawings
Fig. 1 is the exploded perspective view of the semiconductor device relevant with embodiments of the invention 1.
Fig. 2 is the amplification profile of the key component of Fig. 1.
Fig. 3 is illustrated in the amplification profile of loading onto the state behind the soldered ball in the hole of membranaceous base plate.
Fig. 4 is expression forms the state that is used for the outside terminal portions that connects of soldered ball shape through heating process from the state of Fig. 3 a amplification profile.
Fig. 5 is the stereogram of the semiconductor device relevant with embodiments of the invention 1.
Fig. 6 is the amplification profile of the key component of Fig. 5.
Fig. 7 is the overall perspective view of the semiconductor device relevant with embodiments of the invention 2.
Fig. 8 is the overall perspective view of seeing from the medial surface of above-mentioned semiconductor device.
Fig. 9 is the profile of Fig. 7 along the 9-9 line.
Figure 10 is the stereogram of key component of an example of the expression membranaceous circuit board that is used to make above-mentioned semiconductor device.
Figure 11 is the profile for the manufacture method that above-mentioned semiconductor device is described.
Figure 12 is the profile for the manufacture method that above-mentioned semiconductor device is described.
Figure 13 is the profile for the manufacture method that above-mentioned semiconductor device is described.
Figure 14 is the amplification profile for the key component of the manufacture method that above-mentioned semiconductor device is described.
Figure 15 is the amplification profile for the key component of the manufacture method that above-mentioned semiconductor device is described.
Figure 16 is the overall perspective view of the expression semiconductor device relevant with embodiments of the invention 3.
Figure 17 is the overall perspective view of seeing from the medial surface of above-mentioned semiconductor device.
Figure 18 is the profile of Figure 16 along the 18-18 line.
Figure 19 is the overall perspective view of the expression semiconductor device relevant with embodiments of the invention 4.
Figure 20 is the overall perspective view of seeing from the medial surface of above-mentioned semiconductor device.
Figure 21 is the profile of Figure 19 along the 21-21 line.
Figure 22 is for the profile of a part of manufacture method is described.
Figure 23 is the longitudinal sectional drawing of the expression semiconductor device relevant with embodiments of the invention 5.
Figure 24 is the overall perspective view of the expression semiconductor device relevant with embodiments of the invention 6.
Figure 25 is the profile of Figure 24 along the 25-25 line.
Figure 26 is the A portion enlarged drawing of Figure 25.
Figure 27 is the amplification profile of key component of the variation example of this embodiment of expression.
Figure 28 is the overall perspective view of the expression semiconductor device relevant with embodiments of the invention 7.
Figure 29 is the overall perspective view of seeing from the medial surface of above-mentioned semiconductor device.
Figure 30 is the profile of Figure 28 along the 30-30 line.
Figure 31 is the overall perspective view of an example of the expression membranaceous circuit board that is used to make above-mentioned semiconductor device.
Figure 32 is the amplification stereogram of seeing from the medial surface of above-mentioned circuit board.
Figure 33 is the key component stereogram that is illustrated in the state behind the semiconductor chip that engaged on the above-mentioned circuit board.
Figure 34 is that expression connects the pattern wiring of above-mentioned circuit board and the key component stereogram of the state behind the semiconductor chip by lead-in wire.
Figure 35 is illustrated in the key component stereogram after the further formation resin-encapsulated on the above-mentioned circuit board.
Figure 36 is the overall schematic of the expression semiconductor device relevant with embodiments of the invention 8.
Figure 37 is the amplification stereogram of seeing from the medial surface of above-mentioned circuit board.
Figure 38 is the profile of Figure 36 along the 38-38 line.
Figure 39 is the figure for the manufacture method that above-mentioned semiconductor device is described, represents the stereogram of tabular rigidity material and membranaceous circuit board.
Figure 40 is the key component enlarged drawing of the state after above-mentioned tabular rigidity material of expression and membranaceous circuit board adhere to mutually.
Figure 41 is the key diagram about the operation of installing frame shape reinforcement material.
Figure 42 is the key diagram in conjunction with operation about semiconductor chip.
Figure 43 is the key diagram about the wire bond operation.
Figure 44 is the key diagram about the resin-encapsulated operation.
Figure 45 is the key diagram about the resin-encapsulated operation.
Figure 46 is the key diagram about the operation that is formed for the outside terminal portions that connects.
Embodiment
Below, with reference to accompanying drawing on one side of the present invention desirable embodiment carried out specific description on one side.
At first, with reference to Fig. 1～Fig. 6, the embodiment 1 of the semiconductor device relevant with the present invention 1 is described.
This semiconductor device 1 has makes semiconductor chip 3 be bonded on the lip-deep essential structure of membranaceous base plate 2 with facing down.
Above-mentioned membranaceous base plate 2 is such as being to be that tens of microns polyimide resin film is the base plate of base material with thickness, except form a plurality of patterns wiring 21 in its surface by metal formings such as copper, also be formed with in its bottom surface is connected with above-mentioned pattern wiring 21 conductions in the vertical and transversely equidistant a plurality of terminal portions 4 that are used for outside connection by rectangular configuration.
Specifically, except on above-mentioned membranaceous base plate 2 by the hole 24 of a plurality of prescribed level of rectangular formation, an end 21a of the pattern wiring 21 that forms on the surface of this membranaceous base plate 2 from the inner face cloth of membranaceous base plate 2 in each hole 24.And another end 21b of each pattern wiring 21 is provided in the surrounding zone of membranaceous base plate 2 and corresponding with formed terminal pad around the interarea of semiconductor chip 3 30.Also have, on the surface of membranaceous base plate 2 except the other end 21b of staying each pattern wiring 21 promptly with the covering in the position that the terminal pad 30 of conductor chip 3 is connected on the diaphragm 25 formed by epoxy resin etc.
Also having, is to carry out photoetch by the metal formings such as copper that form on to the surface at polyimide resin film to form in the pattern wiring 21 that forms on the surface of above-mentioned membranaceous base plate 2.
Also have, though the hole 24 by rectangular formation on above-mentioned membranaceous base plate 2 is by film formed from bottom surface photoetch polyimides, but as shown in Figure 2, can form above-mentioned hole 24 by the method that adopts such photoetch to form hole 24, its internal diameter can arrive the radius of the inner face of membranaceous base plate 2 greatly.
Periphery at semiconductor chip 3 interareas is disposing a plurality of terminal pads 30.Under the ideal situation, this terminal pad 30 be the aluminium electrode superimposed layer that on the chip interarea, forms by not shown barrier metals gold-plated form flange shape.
Make the interarea of semiconductor chip 3 downward, and when the surface with respect to above-mentioned membranaceous base plate 2 positions, by the resin binder 5 extruding semiconductor chips 3 of regulation.Can adopt in epoxy resin heterogeneity conductive plate that the blending electrically conductive particles forms or with heterogeneity electric conducting materials such as heterogeneity electroconductive binders as this resin binder 5.At this moment, can under the temperature of regulation, heat as required.By such process, between the other end 21b that exposes shape of pattern wiring 21 on the surface of the flange shape terminal pad 30 of semiconductor chip 3 and membranaceous base plate 2, above-mentioned heterogeneity electric conducting material 5 is stressed, and makes above-mentioned terminal pad 30 finish conduction with pattern wiring 21 by electrically conductive particles and is connected.And because of electrically conductive particles is scattered here and there, except the above-mentioned position that is extruded, heterogeneity electric conducting material 5 has insulating properties and plays a part adhesive, and the interarea of membranaceous base plate 2 and semiconductor chip 3 mechanically is joined together.
Be used for the outside terminal portions 4 that connects by following formation at the inner face of membranaceous base plate 2 by rectangular configuration.
Specifically, as shown in Figure 3, soldered ball 40 and not shown solder flux together in the inner face direction of membranaceous base plate 2 is enclosed in each hole 24 the above-mentioned membranaceous base plate 2.The size of this soldered ball 40 will make that under the state in installing to hole 24, the part of soldered ball contact with the pattern wiring 21 of cloth 24 depths to the hole, perhaps at approaching state, sets for and makes soldered ball protrude the amount of stipulating towards the inner face direction of membranaceous base plate 2.Also have, the big I in hole 24 is suitably set according to the big or small corresponding of above-mentioned soldered ball 40.Then, be heated to the melt temperature of soldered ball, as shown in Figure 4, be connected with above-mentioned pattern wiring 21 by a part that makes soldered ball 40, as shown in Figure 5, on the inner face direction of membranaceous base plate 2, press rectangular configuration, and, the terminal portions 4 that is used for outside connection formed by the soldered ball that protrudes ormal weight from the bottom surface of membranaceous base plate.
To compare its thickness much smaller because of the membranaceous base plate 2 and the base plate of glass epoxy resin system, can make the internal diameter in formed hole 24 on this membranaceous base plate 2 and the size decreases that will be encased in the soldered ball 40 on this hole 24.Its result makes that the configurable number that is used for the outside terminal portions 4 that connects increases on the inner face of membranaceous base plate 2, this means can the use side subnumber many semiconductor chips and constitutes the high semiconductor device of integrated level.
Also have, among the embodiment shown on figure, hole 24 in the membranaceous base plate 2 is forms of making the internal diameter expansion shape of bottom surface direction, therefore, the laying state that installs to ball under the state on this hole 24 at soldered ball 40 is better, therefore, can select the size of soldered ball 40 to make the outside terminal portions 4 that connects that is used for of soldered ball shape protrude enough amounts from the bottom surface of membranaceous base plate 2.
Also have,, reduced the thickness and the weight of semiconductor device integral body because of using membranaceous base plate 2 as the base plate that engages with semiconductor chip 3.Also have, because membranaceous base plate 2 is flexible, even if the difference of expansion rate, the phenomenon that also can not take place to come off mutually during heating are arranged between semiconductor chip 3 and membranaceous base plate 2.
Below, with reference to Fig. 7～Figure 15, the embodiment 2 of the semiconductor device relevant with the present invention 1 is described.
As Fig. 7～shown in Figure 9, the semiconductor device 1 relevant with this embodiment also has and semiconductor chip 3 is bonded on the membranaceous base plate 2, makes semiconductor chip 3 mechanically and the formation that is connected with membranaceous base plate 2 of conductivity ground by heterogeneity electroconductive binder 5.Then, the lateral surface 3c of above-mentioned semiconductor chip 3 is fenced up, simultaneously, a plurality of terminal portions 4 that are used for outside connection of protruding from the inner face direction of membranaceous base plate 2 are formed by rectangular arrangement by protection resin 6.
Above-mentioned semiconductor chip 3 is meant bare chips such as IC chip or LSI chip, is formed with a plurality of electrode pads 30 at interarea 3a periphery.These electrode pads 30 also be on the interarea 3a with semiconductor chip 3 is made into the aluminium electrode of an integral body, carry out gold-plated grade and form from interarea 3a protrude flange shape.
Membranaceous base plate 2, is overlooked to rectangular-shaped as Fig. 8 and shown in Figure 9 such as being polyimide resin system, and simultaneously, it is more bigger than above-mentioned semiconductor chip 3 to overlook area.Therefore, semiconductor chip 3 is bonded under the state of membranaceous base plate 2, the periphery of membranaceous base plate 2 can be exposed to the outside of semiconductor chip 3.And, on above-mentioned membranaceous base plate 2, form a plurality of holes 24 by rectangular arrangement, simultaneously, also formed a plurality of pattern wirings 21 that are connected with each terminal pad 30 conduction of above-mentioned semiconductor chip 3 respectively thereon.An end 21b of each pattern wiring 21 and above-mentioned each terminal pad 30 in opposite directions, simultaneously, another end 21a extends on the corresponding hole 24 separately and seals the top opening in each hole 24.That is to say that an end 21a of above-mentioned pattern wiring 21 is from the inner face direction cloth of above-mentioned membranaceous base plate 2 to each hole 24.Like this, as shown in Figure 9, the terminal portions 4 that is used for outside connection that each self-forming is spherical makes it to bury above-mentioned each hole 24 and also makes it respectively to contact with each pattern wiring 21.
As shown in Figure 9, above-mentioned heterogeneity electroconductive binder 5 is electrically conductive particles 51 of blending goal shape in the resinous principle 50 of Thermocurable and constituting.Like this, above-mentioned semiconductor chip 3 and above-mentioned membranaceous base plate 2 form the connection of conductivity by above-mentioned electrically conductive particles 51 when forming mechanical connections by above-mentioned resinous principle 50.Above-mentioned resinous principle 50 can only be made of porous resin such as the phenolic resinoid that contains as porous resin, also can also comprise the resin of other class.Also have, in the said here phenolic resinoid, except phenolic resins, also including with the phenolic is the epoxy resin etc. of raw material.Above-mentioned electrically conductive particles 51 is situated between, and conduction connects each terminal pad 30 and each pattern wiring 21 between an end of each pattern wiring 21 of each terminal pad 30 of above-mentioned conductor chip 3 and above-mentioned membranaceous base plate 2.Proper such as the ball of the conduction that can adopt on resin balls nickel plating or back such as gold-plated to obtain as above-mentioned electrically conductive particles 51, but also be fine as conductive compositions 51 with Metal Ball.
Above-mentioned protection resin 6 in the surface of the periphery 23 of sealing above-mentioned membranaceous base plate 2, also covered above-mentioned semiconductor chip 3 around, and seal on the surperficial 3b (face opposite) of above-mentioned semiconductor chip 3 with interarea 3a.That is to say; surround above-mentioned semiconductor chip 3 and above-mentioned membranaceous base plate 2 coupling part (heterogeneity electroconductive binder 5) around and the lateral surface 3c of above-mentioned semiconductor chip 3, make the periphery 23 of above-mentioned membranaceous base plate 2 integrated by protection resin 6 with semiconductor chip 3.Also have, the same with the resinous principle 50 of above-mentioned heterogeneity electroconductive binder 5 as above-mentioned protection resin 6, employing is proper such as the thing that contains as the phenolic resinoid of porous resin.
Like this, in above-mentioned semiconductor device 1, the lateral surface 3c of semiconductor chip 3 and the periphery of surperficial 3b directly are protected by above-mentioned protection resin 6.Therefore, when above-mentioned semiconductor device 1 is operated,, also can reduce the damage of semiconductor chip 3 even if there is external force to act on the above-mentioned semiconductor chip 3.And integrated because of make the periphery 23 of above-mentioned membranaceous base plate 2 and above-mentioned semiconductor chip 3 by protection resin 6, external force is not easy directly to affact on the periphery 23 of membranaceous base plate 2.Thus, avoided effectively membranaceous base plate 2 being come off from semiconductor chip 3 because of external force acts on the periphery 23 of membranaceous base plate 2.
Below, with reference to Figure 10～Figure 15 the manufacture method of above-mentioned semiconductor device 1 is described, but for simplicity, with reference to Figure 10 the membranaceous circuit board 2A of the manufacturing that is used for above-mentioned semiconductor device 1 is described earlier.
As shown in figure 10, above-mentioned membranaceous its integral body of circuit board 2A be OBL, on long direction, establishing a plurality of rectangle regions 26 that engaging the semiconductor chip 3 that with dashed lines surrounds among this figure continuously.As this membranaceous circuit board 2A, use is proper by the base plate that insulating film materials such as polyimide resin form thin oblong-shaped or band shape.In each rectangle region 26,, also form a plurality of pattern wirings 21 in its surface except being formed with by rectangular a plurality of holes 24 side by side.These patterns wiring 21 perhaps forms by etch processes after sticking metal film such as can form metal film such as copper on the surface of above-mentioned membranaceous circuit board 2A again, can also be by sticking the metal forming formation that makes apperance in advance.Above-mentioned each pattern 21 one end thereof that connect up are sealed the top opening surface in each hole 24, and simultaneously, another end is corresponding with the terminal pad that forms on semiconductor chip 3 30 and form.Also have, on the both ends of the Width of above-mentioned membranaceous circuit board 2A, be formed for the hole 27 fixed continuously, utilize these holes that are used for fixing 27 that above-mentioned membranaceous circuit board 2A is contained in and be convenient on the suitable brace table carry by certain distance.Also have, an end of each pattern wiring 21 is exposed and the diaphragm (diagram slightly) by insulation covers above-mentioned each rectangle region 26.
As Figure 10 and shown in Figure 11, on the rectangle region 26 of above-mentioned membranaceous circuit board 2A, be mounted with roughly heterogeneity electroconductive binder 5 corresponding to the sheet of overlooking area of above-mentioned rectangle region 26, be mounted with the downward semiconductor chip of interarea 3 above the heterogeneity electroconductive binder 5 at this, and an end that makes terminal pad 30 and above-mentioned pattern wiring 21 in opposite directions.Also have, also can use muciform resinous principle 50 formed adhesives as heterogeneity electroconductive binder 5.
Like this, in the above-mentioned heterogeneity electroconductive binder 5 of heating, semiconductor chip 3 is engaged with on the membranaceous circuit board 2A become state shown in Figure 12 by semiconductor chip 3 being pressed to membranaceous circuit board 2A.Because of the resinous principle 50 of above-mentioned heterogeneity electroconductive binder 5 is heat-curing resins, if to this heating, resinous principle 50 can be softening.Under this state, if semiconductor chip 3 is pressed to membranaceous circuit board 2A, resinous principle 50 between each pattern wiring 21 of each terminal pad 30 of semiconductor chip 3 and membranaceous circuit board 2A can be pressed off, and conductive compositions 51 is situated between selectively between each terminal pad 30 and each pattern wiring 21.Thus, between each terminal pad 30 and each pattern wiring 21, realize that conduction is connected.Also have, when semiconductor chip 3 being pressed to membranaceous circuit board 2A, also can add ultrasonic wave.In the case, the electrically conductive particles 51 between each terminal pad 30 and each pattern wiring 21 of being situated between can be respectively and each terminal pad 30 and each pattern 21 alloyings that connect up, and can obtain firm mechanical connection and be connected with favorable conductive.If further heating, the resinous principle behind of short duration the softening can solidify, and realizes that thus the mechanicalness between semiconductor chip 3 and the membranaceous circuit board 2A connects.
Then, as shown in figure 13, by Thermocurable protection resin 6 the coupling part of semiconductor chip 3 and membranaceous circuit board 2A on every side and the lateral surface 3c of above-mentioned semiconductor chip 3 surround.As this protection resin 6, use aqueous resin proper, but also can be with above-mentioned heterogeneity electroconductive binder 5 as protecting resin, can also using other resin.Certainly, also can be before the resinous principle that makes above-mentioned heterogeneity electroconductive binder 5 solidifies surround by above-mentioned protection resin 6 semiconductor chip 3 around.In the case, the same with the operation of solidifying above-mentioned heterogeneity electroconductive binder 5 above-mentioned protection resin 6 is solidified.
Then, as shown in figure 14, the counter-rotating of the table of above-mentioned membranaceous circuit board 2A the inside, corresponding with formed each hole 24 on the rectangle region 26 of above-mentioned membranaceous circuit board 2A, form by rectangular a plurality of terminal portions 4 that are used for outside connection side by side in the inside of above-mentioned membranaceous circuit board 2A.Specifically, described in the explanation of embodiment 1, in soldered ball 40 and solder flux (diagram slightly) each hole 24 of packing into together, the heating soldered ball makes it after the fusion to be used for the outside terminal portions 4 that connects by as shown in figure 15 spherical of each self-forming of cooling curing as.
If after finishing processing like this, near the edge of above-mentioned protection resin 6, cut off, make this zone that becomes membranaceous base plate 2 separately from above-mentioned membranaceous circuit board 2A, obtain as Fig. 7～semiconductor device 1 shown in Figure 9.
Above-mentioned semiconductor device 1 is used such as being contained in together on the main printed circuit board (diagram slightly) that is formed with the regulation wiring with other electronic device.Install on the main printed circuit board put into after above-mentioned semiconductor device 1 is each of above-mentioned semiconductor device 1 to be used for the outside terminal portions 4 that connects and loading corresponding with the portion of terminal that is forming on the main printed circuit board heating furnace again fusion be used for the terminal portions 4 (spherical scolder) of outside connection and finish installation.At this moment, be used for the outside terminal portions 4 that connects and be heated to about 200 ℃ to 300 ℃, above-mentioned heterogeneity adhesive 5 also is heated to same temperature levels.At this moment, contained moisture generation volumetric expansion in the heterogeneity adhesive 5 can be worried to produce stress because of bubble swells in heterogeneity adhesive 5.
, in the semiconductor device relevant 1, adopt to contain the resinous principle 50 of the composition of porous resin as above-mentioned heterogeneity adhesive 5 with present embodiment, and, the composition that contains porous resin adopted as the protection resin 6 that surrounds heterogeneity adhesive 5.That is to say, adopt the extraordinary resin of gas permeability as heterogeneity adhesive 5 and protection resin 6.Therefore, even if by heating moisture generation volumetric expansion and bubble in the heterogeneity adhesive 5 of semiconductor device 1 are swollen, these can be discharged to the outside of above-mentioned heterogeneity adhesive 5, and then are discharged to the outside of protection resin 6.Therefore, in the above-mentioned semiconductor device 1 relevant with present embodiment, when being installed to above-mentioned semiconductor device 1 on the main printed circuit board, can not produce stress in heterogeneity adhesive 5 even if semiconductor device 1 (heterogeneity adhesive 5) heated also, more therefore stress sustains damage semiconductor chip 3.And, membranaceous base plate 2 is had an effect from the power that semiconductor chip 3 comes off.
Also have, in the present embodiment,, adopted blending electrically conductive particles 51 formed heterogeneity electroconductive binders in resinous principle 50, but adopted the adhesive that only constitutes also to be fine by resinous principle as adhesive.In this case, when semiconductor chip 3 is pressed to membranaceous base plate 2 with strength membranaceous base plate 2 is applied ultrasonic vibration, the conduction between the terminal pad 30 of semiconductor chip 3 and the pattern of membranaceous base plate 2 wiring 21 is connected the direct contact realization that is by both.
Below, with reference to Figure 16～Figure 18, the embodiment 3 of the semiconductor device relevant with the present invention 1 is described.
The relevant semiconductor device 1 of embodiment is similar with the relevant semiconductor device 1 with embodiment 2 as Fig. 7～shown in Figure 9 therewith.In the semiconductor device 1 relevant, do not use the protection resin to surround semiconductor chip 3 with embodiment 3.And, with respect to each terminal pad 30 of semiconductor chip 3, in each pattern wiring 21 that on the surface of membranaceous base plate 2, forms be used for outside terminal portions 4 corresponding end 21a that are connected and see and prolonged entirely to being partial to area inside from overlooking.For remaining formation, because of identical in essence with the foregoing description 2, corresponding parts or part are used identical symbol and are omitted explanation.Also have, this semiconductor device 1 relevant with embodiment 3 can be used in fact and in the identical manufacture method manufacturing described in the embodiment 2.
By such formation, when semiconductor chip 3 being bonded on the membranaceous base plate 2, when being pressed onto semiconductor chip 3 on the membranaceous base plate 2 by heterogeneity electroconductive binder 5, pattern wiring 21 pressure that bear effectively from the flange shape terminal pad 30 of semiconductor chip 3 of base plate, the extruding that is subjected to part because of heterogeneity electroconductive binder 5 makes the conduction between terminal pad 30 and the pattern wiring 21 connect realization reliably.When this can suppose to seal the position in the hole 24 on the membranaceous base plate in the position alignment pattern of the terminal pad 30 of semiconductor chip 3 wiring 21, since under exist hole 24, pattern wiring 21 pressure that can't bear fully from terminal pad 30 have just been understood after so considering.
Below, with reference to Figure 19～Figure 22, the embodiment 4 of the semiconductor device relevant with the present invention 1 is described.
In the relevant semiconductor device 1 of embodiment therewith, on the periphery of the surperficial 3b of semiconductor chip 3 (face opposite), be formed with chamfered section 33 with interarea 3a, the relevant semiconductor device 1 with embodiment 3 of this point and Figure 16～shown in Figure 180 is different.For remaining formation, because of identical in essence with the foregoing description 3, corresponding parts or part are used identical symbol and are omitted explanation.Also have, this semiconductor device 1 relevant with embodiment 4 can be used in fact and in the identical manufacture method manufacturing described in the embodiment 2.
The chamfered section 33 of such semiconductor chip 3 is to form in the liner plate stage before making each semiconductor chip 3.Specifically, shown in Figure 22 (a), utilize outer peripheral section shape to begin to cut, on liner plate 3A, form the leg-of-mutton chase 33a of section for the blade 71 of taper bottom surface 32a direction from liner plate 3A.Then, shown in Figure 22 (b), be that the blade 72 of straight line is gone up the part relative with chase 33a from the another side 30a of liner plate 3A and begun to carry out common cutting with section shape again, obtain each semiconductor chip 3.
In structure with ventricumbent mode mounted semiconductor chip 3, periphery in the surperficial 3b of semiconductor chip 3 side is pointed subject to damage, if but such part is carried out chamfered in advance, even if there is what external force to act on the semiconductor chip 3, the possibility of semiconductor chip 3 damaged is also low.
Below, with reference to Figure 23, the embodiment 5 of the semiconductor device relevant with the present invention 1 is described.
In the relevant semiconductor device 1 of embodiment therewith, in each pattern wiring 21 of membranaceous base plate 2 except with each terminal pad 30 of semiconductor chip 3 in opposite directions and formation alpha ray shielding dielectric film 25 on the part the regional 21b that is connected of conduction or the whole zone with it.Specifically, this alpha ray shielding dielectric film 25 at least will each be used for the outside terminal portions 4 that connects directly over the zone on form.Also have, this alpha ray shielding dielectric film 25 is such as forming by polyimide resin.Thus, can prevent effectively that the circuit element on the interarea 3a of semiconductor chip 3 is exposed to from the alpha ray of being made up of scolder that the outside terminal portions 4 that connects radiates that is used for.Also have,, particularly use under the situation of storage chip and adopt such structure proper as semiconductor chip 3.For remaining formation, because of identical in essence with the foregoing description 3, corresponding parts or part are used identical symbol and are omitted explanation.Also have, this semiconductor device 1 relevant with embodiment 5 can be used in fact and in the identical manufacture method manufacturing described in the embodiment 2.
In having loaded the semiconductor device in the past of storage chip, can produce electric charge when on the PN junction interface of storage chip, being subjected to alpha-irradiation, electric charge can may cause the destruction (soft error) to the information of memory cell thus.To this, in the semiconductor device relevant, can avoid semiconductor chip 3 to be exposed to from the alpha ray of forming by scolder that the outside terminal portions 4 that connects radiates that is used for by alpha ray shielding dielectric film 25 with present embodiment.Its result can avoid taking place the destruction (soft error) to the information of memory cell.
Below, with reference to Figure 24～Figure 26, the embodiment 6 of the semiconductor device relevant with the present invention 1 is described.
At first, in the semiconductor device 1 of Figure 24～shown in Figure 26, the surperficial 3b of above-mentioned semiconductor chip 3 (face opposite with interarea 3a) is actually and is exposed, simultaneously, form on the surface of this chip small concavo-convex 32, and, by enclosing sign M on the surface that is printed on this chip.This is fine concavo-convex 32 such as forming by the centre plane roughness about 2～5 μ m.For remaining formation, because of identical in essence with the foregoing description 2, corresponding parts or part are used identical symbol and are omitted explanation.
As form above-mentioned small concavo-convex 32 method have the liner plate stage with the regulation particle diameter smear material carry out spray treatment method, carry out abrasive method or with the method on metallic brush processing liner plate surface etc. with grinding stone with frosted of deciding particle diameter.If by so handling, the China ink of printing usefulness has strengthened the adhesive force on the surface (face opposite with interarea) of the semiconductor chip is made up of silicon, can form reliably and be not easy the sign of cancellation like this by printing.
Also have, in semiconductor device shown in Figure 27 1, the surperficial 3b of above-mentioned semiconductor chip 3 (face opposite with interarea) is covered with by resin molding 35, and, on the surface of this resin molding 35, enclose sign M by being printed on.The thickness of this resin molding 35 is at the most also with regard to tens of microns.
Wanting on silicon face to identify printing reliably with resinous China ink is the comparison difficulty, and sign may easily disappear, but if the surface of resin molding 35, even if also can identify printing reliably with resinous China ink.And also useful laser identifies printing, but in this case, is absorbed by resin molding 35 to a certain extent from the heat of laser, and heat can directly not be added on the semiconductor chip 3, therefore, can alleviate damage to semiconductor chip 3 by forming resin molding 35.
Also have, resin molding 35 can be selected suitable resin according to the kind of China ink, and is proper such as heat-curing resins such as employing epoxy resin.Under the situation that adopts heat-curing resin, such as muciform heat-curing resin is spin-coated on the liner plate, make it hot curing and behind holomorphism resin film on the liner plate, obtaining at interarea and form the semiconductor chip of above-mentioned resin molding 35 at its reverse side by cutting.Under the situation of use epoxy resin etc.,, can identify printing with existing equipment because of the condition with the enterprising line identifier printing of the resin-encapsulated in semiconductor device in the past has no difference.
Below, with reference to Figure 28～Figure 35, the embodiment 7 of the semiconductor device relevant with the present invention 1 is described.
As Figure 28～shown in Figure 30, this semiconductor device 1 its formation is to load semiconductor chip 3 on the surface of the membranaceous base plate 2 of the pattern wiring 21 that is formed with regulation, 8 make it and 21 conductings of connecting up of above-mentioned pattern by going between, simultaneously, the inner face at membranaceous base plate 2 forms by the rectangular a plurality of spherical terminal portions 4 that is used for outside connection side by side.
As Figure 28 and shown in Figure 29, above-mentioned membranaceous base plate 2 is to be formed by rectangular-shaped by the resin moldings such as polyimides with insulating properties, forms the pattern wiring 21 with a plurality of portion of terminal 21b in its surface.This membranaceous base plate 2 is connecting up to cut off after formed circuit board 2A carries out the predetermined process such as bonding of semiconductor chip 3 and separates above-mentioned circuit board 2A and form having the banded or thin OBL repeat pattern in the vertical of long film.
As Figure 29 and shown in Figure 30, middle part at above-mentioned membranaceous base plate 2, except forming by rectangular arrangement a plurality of holes 24, above-mentioned each portion of terminal 21b is arranged on the periphery of above-mentioned membranaceous base plate 2, from each portion of terminal 21b to the front end in each self-corresponding hole 24 till form above-mentioned pattern wiring 21 continuously.Above-mentioned each hole 24 its top opening are sealed by the leading section 21a of above-mentioned pattern wiring 21, also not forming under the above-mentioned state that is used for the outside terminal portions 4 that connects, guide the leading section 21a of above-mentioned pattern wiring 21 from the inner face of above-mentioned membranaceous base plate 2 by above-mentioned each hole 24.
As Figure 29 and shown in Figure 30,,, except the portion of terminal 21b that stays pattern wiring 21, all use diaphragm 25 to be covered with insulating properties promptly in 24 formed zones, hole by rectangular arrangement at the middle part of above-mentioned membranaceous base plate 2.Said protection film 25 is such as can improving the flexural rigidity (face rigidity) of above-mentioned base plate 2 thus with formation such as epoxy resin.
As shown in figure 30; on as the interarea 3a on above-mentioned semiconductor chip 3 surfaces, form a plurality of terminal pads (diagram slightly); and; by resinous adhesives such as epoxy resin 50 with insulating properties, above-mentioned semiconductor chip 3 is installed on the said protection film 25 up with interarea and mechanically is bonded on the above-mentioned membranaceous base plate 2.Also have, as above-mentioned semiconductor chip 3, can be with bare chips such as IC chip or LSI chips, as adhesive 50, can be normal temperature cure also can be the adhesive of Thermocurable.
As Figure 28 and shown in Figure 30, for above-mentioned semiconductor chip 3, make to form between above-mentioned terminal pad and above-mentioned each portion of terminal 21b by lead-in wires such as gold thread 8 to be connected, above-mentioned semiconductor chip 3 and above-mentioned each portion of terminal 21b are finished conduct electricity by this lead-in wire 8 to be connected.
As Figure 29 and shown in Figure 30, form a plurality of terminal portions 4 that are used for outside connection corresponding by rectangular arrangement with above-mentioned each hole 24 at the inner face of above-mentioned membranaceous base plate 2.The same with the various embodiments described above, be used for the outside terminal portions 4 that connects such as forming spherical these by solder flux.Can make each be used for the outside terminal portions 4 that connects like this and realize that with each terminal pad of above-mentioned semiconductor chip 3 conduction is connected.
Then, seal surface, the semiconductor chip 3 of above-mentioned membranaceous base plate 2 and go between 8, form resin-encapsulated 9 by being shaped with metal die as epoxy resin.
The semiconductor device 1 of Gou Chenging uses such as being installed on the circuit board like this, because the above-mentioned terminal portions 4 that is used for outside connection is made soldered ball, therefore, adopts the Reflow Soldering connection proper to above-mentioned semiconductor device 1.
Below, with reference to Figure 31～Figure 35 the manufacture method of above-mentioned semiconductor device 1 is described.
Above-mentioned semiconductor device 1 is to make by the membranaceous circuit board 2A that is added with as Figure 31 and tabular rigidity material 10 shown in Figure 32.This membranaceous circuit board 2A forms thin oblong-shaped with polyimide film and is formed by the regional 20A that repeats to form the pattern wiring 21 with a plurality of portion of terminal 21b on long direction continuously.These pattern wirings 21 are such as forming by etch processes after forming Copper Foil on the surface of above-mentioned membranaceous circuit board 2A again.
Around the 20A of the formation zone of above-mentioned each pattern wiring, form peristome 20c, make it to surround these each regional 20A and make the formation zone 20A of above-mentioned pattern wiring become rectangular-shaped, each regional 20A is supported that by four bights promptly it is shaped as island by connecting fine strain of millet 20b.On the surface of above-mentioned circuit board 2A the live wire 20d of formation pattern wiring 21 and conducting with it, in electrolyte, above-mentioned pattern wiring 21 energisings are carried out just forming above-mentioned peristome 20c after gold-plated etc. again.Above-mentioned peristome 20c forms by pressure such as the metal die with regulation, in this case, gets through the direct-connected live wire 20d of formation zone 20A that connects up with above-mentioned pattern and forms above-mentioned peristome 20c.That is to say that under the state that forms above-mentioned peristome 20c, the formation zone 20A of above-mentioned pattern wiring and the conduction connection between the above-mentioned live wire 20d are cut off.
Like this, on the 20A of the formation zone of supported island pattern wiring, form, seal the top opening in above-mentioned each hole 24 till above-mentioned each hole 24 with the leading section 21a cloth of the pattern wiring 21 of above-mentioned each portion of terminal 21b conducting by a plurality of holes 24 of rectangular arrangement.That is to say, guide from the inner face of the formation zone 20A of above-mentioned pattern wiring by each hole 24 above-mentioned pattern wiring 21 leading section 21a cloth to.Also have, at the middle part of the formation zone of above-mentioned pattern wiring 20A, the regional 20A that promptly forms above-mentioned each hole 24 goes up and forms rectangular-shaped diaphragm 25, is used to cover the end regions of above-mentioned each portion of terminal 21b.Certainly, this diaphragm 25 has insulating properties.
On the other hand, as shown in figure 31, above-mentioned tabular rigidity material 10 is such as being to be tabular material about 0.25mm by the thickness that copper etc. forms.Its shape is seen also than the big circle of above-mentioned circuit board 2A from overlooking.And, shown in figure 32, on above-mentioned tabular rigidity material 10, form and the corresponding a plurality of window of the formation zone 20A of the pattern wiring of above-mentioned circuit board 2A portion 18.Shown in figure 32, as the adhesive by epoxy resin system the inner face of above-mentioned circuit board 2A attached to above-mentioned tabular rigidity material 10, under the state that has adhered to above-mentioned circuit board 2A, can see the 24 formed zones, hole that the inner face of the formation zone 20A of the pattern wiring among above-mentioned circuit board 2A promptly forms by rectangular arrangement from above-mentioned window portion 18.Then, each fixed fixing hole 17 that is provided with continuously at interval in the both sides of the Width of above-mentioned tabular rigidity material 10.Specifically, when the claw of the rotary bodies such as wheel of band pawl is tangled by said fixing hole 17, above-mentioned tabular rigidity material 10 and above-mentioned circuit board 2A are transmitted together continuously or discontinuously by rotating above-mentioned rotary body.
In above-mentioned circuit board 2A, because of above-mentioned tabular rigidity material 10 is housed, this state and above-mentioned circuit board 2A are in independent state and compare its rigidity and significantly improve, and the formation zone 20A of above-mentioned pattern wiring still is exposed.On the 20A of the formation zone of above-mentioned pattern wiring 21, load onto semiconductor chip 3, bonding wire 8, form resin-encapsulated 9 again, because of making above-mentioned circuit board 2A, above-mentioned tabular rigidity material 10 can regard and guide the rigidity that frame has equal extent as, the utilization existing production line of guiding frame can be made semiconductor device 1 with above-mentioned circuit board 2A.
The operation that above-mentioned semiconductor chip 3 is installed is by earlier smearing or putting well the adhesive of the Thermocurables such as epoxy resin of liquid or solid, shaped on the 20A of the formation zone of above-mentioned pattern wiring, having with well-known chip mounter that loading semiconductor chip 3 carries out under the state of above-mentioned adhesive again.Then, make above-mentioned adhesive hot curing with heater etc., thereby above-mentioned semiconductor chip 3 is installed on the above-mentioned circuit board 2A, become state as shown in figure 33.
At this moment, above-mentioned circuit board 2A is heated and will expands, and the pattern wiring 21 that forms on above-mentioned circuit board 2A also will be expanded.Because of above-mentioned circuit board 2A is formed by the resin with insulating properties, above-mentioned pattern wiring 21 is formed by conductor metal, and expansion rate is difference separately, worries that warpage can take place above-mentioned circuit board 2A.If warpage takes place in the formation zone 20A of particularly above-mentioned pattern wiring, can be affected in the wire bond operation in conjunction with the precision or the formation precision of external cabling end that is used for the formation operation of the outside terminal portions that connects.
, under the ideal situation, above-mentioned circuit board 2A by polyimide resin film form, above-mentioned pattern wiring 21 forms by copper.Though its expansion rate separately of polyimide resin film and copper is different, but it is more approaching, so the swell increment of the swell increment of above-mentioned circuit board 2A and above-mentioned pattern wiring 21 differs and be less big, avoided when above-mentioned circuit board 2A is heated, taking place the phenomenon of warpage to a certain extent.And above-mentioned circuit board 2A is attached on the above-mentioned tabular rigidity material 10, and above-mentioned circuit board 2A is subjected to the constraint of above-mentioned tabular rigidity material 10, therefore also can avoid above-mentioned circuit board 2A because of the warpage of being heated.That is to say that at first, under the ideal situation, above-mentioned tabular rigidity material 10 is formed by copper, during heating, the expansion of equal extent takes place in above-mentioned circuit board 2A and above-mentioned tabular rigidity material 10, therefore can avoid above-mentioned circuit board 2A because of the warpage of being heated.Also have, the formation zone 20A of above-mentioned pattern wiring is formed the support island attitude thing that is subjected to four bights, simultaneously, because of above-mentioned circuit board 2A attached on the above-mentioned tabular rigidity material 10, the mobile meeting to all directions of the formation zone 20A of above-mentioned pattern wiring is restricted, and the warpage of the formation zone 20A of above-mentioned pattern wiring also can be restricted.Therefore, for the formation zone 20A of above-mentioned pattern wiring, even if above-mentioned circuit board 2A is heated, as long as the not short circuit of connection fine strain of millet 20b that island is supporting, warpage just can not take place in the formation zone 20A of above-mentioned pattern wiring.
When the installation procedure of above-mentioned semiconductor chip 3 is over, periphery each portion of terminal 21b that sets and the terminal pad that forms on above-mentioned semiconductor chip (diagram slightly) at the formation zone of above-mentioned pattern wiring 20A are connected by lead-in wire 8, become state as shown in figure 34.This operation can be carried out automatically with lead binding apparatus.In this operation, undertaken by so-called thermo-compressed under the situation of wire bond, though above-mentioned semiconductor chip 3 is so that above-mentioned circuit board 2A is heated, the same with the installation procedure of above-mentioned semiconductor chip 3, warpage can not take place in the formation zone 20A of above-mentioned pattern wiring.Therefore, the state of setting is not originally departed from the position (portion of terminal 21b) of the enterprising line lead combination of formation zone 20A that can make in above-mentioned pattern wiring because of the formation zone 20A warpage of pattern wiring, can carry out wire bond accurately as requested.
Secondly, above-mentioned semiconductor chip 3 and combined leads 8 are enclosed formation resin-encapsulated 9, become state as shown in figure 35.In this operation, adopt so-called transfer mo(u)lding method proper.Specifically, use forms the metal die up and down of void space under the state of closed mould, clip above-mentioned circuit board 2A and seal above-mentioned each metal die with the form of in above-mentioned void space, having put above-mentioned semiconductor chip 3 and combined leads 8, in above-mentioned void space, inject after the epoxy resin etc. of molten condition, by solidifying, only surface one side on the 20A of the formation zone of above-mentioned pattern wiring forms resin-encapsulated 9.In such resin-encapsulated operation, inject molten resin above-mentioned circuit board 2A is heated, but in this process, warpage can not take place in above-mentioned circuit board 2A yet.
Moreover, make above-mentioned circuit board 2A counter-rotating, in inner face one side of the formation zone of above-mentioned pattern wiring 20A, promptly on each hole in a plurality of holes 24 that form by rectangular arrangement, be formed for the terminal portions 4 of outside connection with the same procedure described in the various embodiments described above.On the inner face of above-mentioned circuit board 2A, pasting above-mentioned tabular rigidity material 10, but as mentioned above,, under the state that above-mentioned tabular rigidity material 10 is pasting, can form above-mentioned each and be used for the outside terminal portions 4 that connects towards above-mentioned each hole 24 from the window portion 18 of above-mentioned tabular rigidity material 10.As mentioned above, in installation procedure, wire bond operation or the resin-encapsulated operation of above-mentioned semiconductor chip, though above-mentioned circuit board 2A is heated, because of above-mentioned circuit board 2A (the formation zone 20A of pattern wiring) can avoid warpage when heating, each operation that is used for the outside terminal portions 4 that connects can not stay warpage to the regional 20A of the formation of pattern wiring in formation.Therefore, can not make the formation position in above-mentioned each hole 24 depart from the state of setting originally, can be formed for the outside terminal portions 4 that connects accurately as requested because of the formation zone 20A warpage of pattern wiring.
Finished under the situation of above-mentioned each operation etc., finally will go up and this position that becomes semiconductor device 1 be cut off dividing come obtain as Figure 28 to each semiconductor device 1 shown in Figure 30 from above-mentioned circuit board 2A.To the situation of above-mentioned circuit board 2A, because of form peristome 20c around the 20A of the formation zone of above-mentioned pattern wiring, the part of this cut-out is less.In above-mentioned circuit board 2A, the formation zone 20A that connects up because of above-mentioned pattern passes through to connect the form that fine strain of millet 20b forms the island support, as long as the above-mentioned connection fine strain of millet 20b of cut-out is just passable.And because of above-mentioned peristome 20c forms by the direct-connected live wire 20d of formation zone 20A that gets through with the wiring of above-mentioned pattern, not adding copper mold at above-mentioned connection fine strain of millet 20b does not have gold-plated etc. yet.Therefore, when cutting off above-mentioned connection fine strain of millet 20b and be partitioned into the position of semiconductor device 1, need not cut off, just can cut off by simple devices such as laser with metal die etc., very convenient.
Also have, above-mentioned manufacture method generally also goes for having with reference to the illustrated semiconductor device of Fig. 1～Figure 27 etc. the semiconductor device of the structure of bond semiconductor chip 3 on the surface of membranaceous base plate 2 except being used to make the semiconductor device as Figure 28～form shown in Figure 30.
Also have, in the form shown in the figure, on the bottom surface of membranaceous circuit board 2A, pasting above-mentioned tabular rigidity material 10, also be fine but be used in the formation of pasting above-mentioned tabular rigidity material 10 on the surface of membranaceous circuit board 2A.
Below, with reference to Figure 36～Figure 46, the embodiment 8 and the manufacture method thereof of the semiconductor device relevant with the present invention described.
Therewith the relevant semiconductor device 1 of embodiment with close as the relevant semiconductor device 1 of the embodiment 7 of Figure 28～shown in Figure 30.Difference is that the frame shape reinforcement material 95 that surrounds semiconductor chip 3 in resin-encapsulated 9 is loaded in the integral body and goes.Under the ideal situation, these frame shape reinforcement material 95 usefulness form with the resin material of the resin material that forms resin-encapsulated with quality.For remaining formation, because of identical in essence with the foregoing description 7, corresponding parts or part are used identical symbol and are omitted explanation.If constitute like this, can further improve the protective value of 9 pairs of semiconductor chips of resin-encapsulated.
Below, with reference to Figure 39～Figure 46, the manufacture method of semiconductor device 1 is described.Above-mentioned semiconductor device 1 is manufactured by the membranaceous circuit board 2A that has added tabular rigidity material 10.The formation of this membranaceous circuit board 2A basically with about illustrated basic identical of the manufacture method of embodiment 7.
In this embodiment, on the surface of membranaceous circuit board 2A, pasting the tabular rigidity material 10 that has towards the fenestra 18 of the formation zone 20A of each pattern wiring of membranaceous circuit board 2A.As shown in figure 40, under the state that has pasted above-mentioned membranaceous circuit board 2A, the formation zone 20A of the pattern wiring of above-mentioned window portion 18 on membranaceous circuit board 2A.Then, each fixed fixing hole 17 that is provided with continuously at interval in the both sides of the Width of above-mentioned tabular rigidity material 10.
Under the state that above-mentioned membranaceous circuit board 2A is bonded on the above-mentioned tabular rigidity material 10, the formation zone 20A of above-mentioned pattern wiring still is exposed, and therefore can load onto semiconductor chip 3, bonding wire 8 on the 20A of the formation zone of above-mentioned pattern wiring 21, form resin-encapsulated 9 again.And because of above-mentioned membranaceous circuit board 2A is bonded on the above-mentioned fid 10, this state and above-mentioned circuit board 2A are in independent state and compare its rigidity and significantly improve.Because of there being above-mentioned tabular rigidity material 10 to make above-mentioned circuit board 2A can regard and guide the rigidity that frame has equal extent as, used the existing production line of guiding frame, can make semiconductor device 1 with above-mentioned circuit board 2A.
In the present embodiment, at first, on the 20A of the formation zone of the pattern of membranaceous circuit board 2A wiring, frame shape reinforcement material 95 is loaded onto.As shown in figure 41, this frame shape reinforcement material 95 is gone up and is installed by it being embedded in gradually in above-mentioned tabular rigidity material 10 formed each window portion 18 and it being bonded on above-mentioned membranaceous circuit board 2A.Also have, under the ideal situation, this frame shape reinforcement material 95 adopts the resin of the same race with resin-encapsulated 9, this is because it will cover the suitable position of formation zone 20A of the pattern wiring of membranaceous circuit board 2A, must adopt material with insulating properties, and, also consider following and zygosity resin-encapsulated 9.
Secondly, semiconductor chip 3 is contained on the formation zone 20A of above-mentioned pattern wiring.This operation is earlier to smear or put well the adhesive of the Thermocurables such as epoxy resin of liquid or solid, shaped on the 20A of the formation zone of above-mentioned pattern wiring, having the following semiconductor chip 3 of state of above-mentioned adhesive to be loaded on the membranaceous circuit board 2A with existing chip erector etc. again.Then, make above-mentioned adhesive hot curing with heater etc., thereby above-mentioned semiconductor chip 3 is installed on the above-mentioned circuit board 2A, become state as shown in figure 42.
At this moment, above-mentioned membranaceous circuit board 2A is heated and will expands, and the pattern wiring 21 that forms on above-mentioned circuit board 2A also will be expanded.Because of above-mentioned membranaceous circuit board 2A is formed by the resin with insulating properties, above-mentioned pattern wiring 21 is formed by conductor metal, and expansion rate is difference separately, worries that warpage can take place above-mentioned membranaceous circuit board 2A.If warpage takes place the formation zone 20A of particularly above-mentioned pattern wiring, the formation precision in conjunction with the external cabling end in the formation operation of precision or following external cabling end in the wire bond operation can be affected.
, in above-mentioned membranaceous circuit board 2A,,, further improved the face rigidity of the formation zone 20A of pattern wiring with illustrated comparing in the manufacture method of embodiment 7 because of the periphery at the formation zone of pattern wiring 20A is provided with frame shape reinforcement material 95.Like this, with above-mentioned membranaceous circuit board 2A, be not easy to make the formation zone 20A warpage of pattern wiring because of the external force effect.
Under the situation that the installation procedure of above-mentioned semiconductor chip 3 is over, periphery each portion of terminal 21b that sets and the electrode pads that forms on above-mentioned semiconductor chip (diagram slightly) at the formation zone of pattern wiring 20A are connected by lead-in wire 8, become state as shown in figure 43.
Then, above-mentioned semiconductor chip 3, frame shape reinforcement material 95 and combined leads 8 are enclosed formation resin-encapsulated 9.Specifically, as shown in figure 44, at first, lower mold 9A, 9B on the form of in above-mentioned void space 90, having put above-mentioned semiconductor chip 3 and combined leads 8 above-mentioned membranaceous circuit board 2A being clamped and seals.Then, inject in above-mentioned void space 90 after the epoxy resin etc. of molten condition, by solidifying, as shown in figure 45, only surface one side on the 20A of the formation zone of above-mentioned pattern wiring forms resin-encapsulated 9.
Then, make the table the inside counter-rotating of above-mentioned membranaceous circuit board 2A,, promptly on each hole in a plurality of holes 24 that form by rectangular arrangement, be formed for the outside terminal portions 4 that connects in inner face one side of the formation zone of above-mentioned pattern wiring 20A.These methods that are formed for the outside terminal portions 4 that connects are identical with described in the above-described embodiment method.
As mentioned above, in installation procedure, wire bond operation or the resin-encapsulated operation of above-mentioned semiconductor chip, though above-mentioned membranaceous circuit board 2A is heated, but it is to carry out under the state that above-mentioned frame shape reinforcement material has been installed that above-mentioned each operation is handled, above-mentioned membranaceous circuit board 2A (the formation zone 20A of pattern wiring) can avoid warpage when heating, each operation that is used for the outside terminal portions 4 that connects can not stay warpage to the formation zone 20A of pattern wiring in formation.
At last, go up from above-mentioned membranaceous circuit board 2A and this position (the formation zone 20A of pattern wiring) that becomes semiconductor device 1 cut off dividing comes obtains as Figure 36 to each semiconductor device 1 shown in Figure 38.

Claims (24)

1. a semiconductor device is characterized in that, comprising:
The film base plate, it has the surface that has formed the wiring of a plurality of patterns and has formed a plurality of bottom surfaces that are used for the outside terminal portions that connects, these are a plurality of be used for outside terminal portions that connect be configured to rectangular and with above-mentioned pattern wiring conducting;
Semiconductor chip, its have the interarea that is provided with a plurality of flange shape terminal pads and with this interarea opposite surfaces, above-mentioned flange shape terminal pad is to be carried on the above-mentioned film base plate with state that above-mentioned pattern wiring is faced mutually; With
Articulamentum, it is made of the heterogeneity electroconductive binder of having sneaked into conductive compositions in the insulative resin composition, be set between above-mentioned semiconductor chip and the above-mentioned film base plate, above-mentioned semiconductor chip mechanicalness is bonded on the above-mentioned film substrate, and allows above-mentioned flange shape terminal pad be electrically connected with above-mentioned pattern wiring.
2. semiconductor device according to claim 1, it is characterized in that, above-mentioned each is used for the outside following formation of terminal portions that connects: soldered ball is loaded into to allowing the part position of above-mentioned pattern wiring just before hole that the bottom surface of film base plate one side forms on the film base plate, the part of above-mentioned soldered ball is protruded from the bottom surface of film base plate, and above-mentioned soldered ball is connected with above-mentioned pattern wiring fusion.
3. semiconductor device according to claim 1 is characterized in that, above-mentioned heterogeneity electroconductive binder contains porous resin.
4. semiconductor device according to claim 1 is characterized in that, above-mentioned heterogeneity electroconductive binder around and above-mentioned semiconductor chip around by the protection resin round.
5. semiconductor device according to claim 4 is characterized in that, above-mentioned protection resin contains porous resin.
6. according to claim 4 or 5 described semiconductor devices, it is characterized in that above-mentioned protection resin encloses on the surface of above-mentioned semiconductor chip.
7. according to claim 3 or 5 described semiconductor devices, it is characterized in that above-mentioned porous resin is the heat-curing resin of phenolic.
8. semiconductor device according to claim 1, it is characterized in that the terminal pad that is used for outside terminal portions that connects and the semiconductor chip that is connected with the other end conduction of above-mentioned pattern wiring that is connected with the end conduction of above-mentioned pattern wiring sees it is dislocation mutually from overlooking.
9. semiconductor device according to claim 8, it is characterized in that, each terminal pad of semiconductor chip is provided in the periphery of semiconductor chip interarea, on the other hand, from overlooking, be to set by rectangular with each terminal portions that is used for outside connection that each terminal pad conduction is connected in zone than above-mentioned each terminal pad inside by the pattern wiring.
10. semiconductor device according to claim 1, it is characterized in that, above-mentioned film base plate lip-deep each pattern wiring in, except with each terminal pad of semiconductor chip in opposite directions and with zone that each terminal pad conduction is connected a part or whole zone formation alpha ray shielding dielectric film.
11. semiconductor device according to claim 10 is characterized in that, above-mentioned alpha ray shielding dielectric film at least will each be used for the outside terminal portions that connects directly over the zone on form.
12. semiconductor device according to claim 10 is characterized in that, above-mentioned alpha ray shielding dielectric film is to be formed by polyimide resin.
13. semiconductor device according to claim 10 is characterized in that, above-mentioned semiconductor chip is the storage chip with memory cell areas.
14. semiconductor device according to claim 1 is characterized in that, forms chamfering in part or all of the edge part on the above-mentioned surface of above-mentioned semiconductor chip.
15. semiconductor device according to claim 1 is characterized in that, form on the above-mentioned surface of above-mentioned semiconductor chip small concavo-convex, and, by enclosing sign on the surface that is printed on this chip.
16. semiconductor device according to claim 1 is characterized in that the above-mentioned surface of above-mentioned semiconductor chip is covered with by resin molding, and, on the surface of this resin molding, enclose sign by being printed on.
17. the manufacture method of a semiconductor device, it is characterized in that, use the film circuit board, this film circuit board has surface and bottom surface, on a direction, form strip, the a plurality of wiring region that are separated from each other are set on the long axis direction of this circuit board, on each wiring region, form and be configured to rectangular a plurality of through holes, form a plurality of pattern wirings above the wiring region at each, the part of each pattern wiring is clogged corresponding in an above-mentioned a plurality of through hole through hole, and this manufacture method comprises:
Add the 1st operation that has towards the rigidity reinforcement material of a plurality of fenestras of above-mentioned a plurality of wiring region on the above-mentioned surface of above-mentioned film circuit board;
In the bond semiconductor chip, conduction connects the 2nd operation of the above-mentioned pattern wiring of semiconductor chip and each wiring region on the surface of each wiring region;
In above-mentioned each through hole from each wiring region of bottom surface direction of above-mentioned film circuit board, load in the soldered ball, by the part of this soldered ball is connected with above-mentioned pattern wiring fusion, on the bottom surface of each wiring region, form outstanding the 3rd operation that is used for the outside terminal portions that connects; With
Downcut the part corresponding from above-mentioned film circuit board, obtain the 4th operation of unit semiconductor device with above-mentioned wiring region.
18. the manufacture method of semiconductor device according to claim 17, it is characterized in that, each semiconductor chip have the interarea that is provided with a plurality of flange shape terminal pads and with this interarea opposite surfaces, each semiconductor chip is engaged with on the above-mentioned surface of each wiring region under its interarea and the situation that the above-mentioned surface of each wiring region is faced mutually allowing, and, the above-mentioned pattern wiring conducting in above-mentioned each flange shape terminal pad and corresponding wiring line district.
19. the manufacture method of semiconductor device according to claim 18, it is characterized in that, make corresponding semiconductor chip and corresponding each wiring region mechanically engage by between above-mentioned semiconductor chip and above-mentioned each wiring region, adding resin binder, simultaneously, the above-mentioned flange shape terminal pad of corresponding semiconductor chip and the above-mentioned pattern wiring conduction of corresponding each wiring region are connected.
20. the manufacture method of semiconductor device according to claim 17 is characterized in that, adopts resin-encapsulated that the above-mentioned surface of each wiring region is sealed with the above-mentioned semiconductor chip that is bonded on this surface.
21. the manufacture method of semiconductor device according to claim 17 is characterized in that, further comprises:
Between above-mentioned the 1st operation and above-mentioned the 2nd operation, carry out the operation of installing frame shape reinforcement material on above-mentioned each wiring region; With
Between above-mentioned the 2nd operation and above-mentioned the 3rd operation, carry out the operation that adopts resin-encapsulated that the above-mentioned surface of each wiring region, the above-mentioned semiconductor chip that is bonded on this surface and above-mentioned frame shape reinforcement material are sealed.
22. the manufacture method of a kind of semiconductor device according to claim 21 is characterized in that, above-mentioned frame shape reinforcement material is to be formed by the material resin identical with the resin that forms above-mentioned resin-encapsulated.
23. the manufacture method of semiconductor device according to claim 17, it is characterized in that, above-mentioned pattern wiring in each wiring region has the wire bond pad, the semiconductor chip that is bonded on each wiring region has the interarea that has formed a plurality of terminal pads, and above-mentioned terminal pad and above-mentioned wire bond pad adopt lead-in wire to interconnect.
24. the framework of a semiconductor device manufacturing usefulness is characterized in that possessing:
The film circuit board, have surface and bottom surface, on a direction, form strip, the a plurality of wiring region that are separated from each other are set on the long axis direction of this circuit board, on each wiring region, form and be configured to rectangular a plurality of through holes, form a plurality of pattern wirings above the wiring region, the part of each pattern wiring is clogged corresponding in an above-mentioned a plurality of through hole through hole at each; With
The rigidity reinforcement material is added to the above-mentioned surface of above-mentioned film circuit board, and be formed with towards above-mentioned a plurality of wiring region and on the position a plurality of fenestras corresponding with these wiring region.
CN 98125104 1997-11-21 1998-11-20 Semiconductor device and its mfg. method Expired - Fee Related CN1238897C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP32130397A JP3519924B2 (en) 1997-11-21 1997-11-21 Semiconductor device structure and method of manufacturing the same
JP321303/97 1997-11-21
JP028156/98 1998-02-10
JP230620/98 1998-08-17
JP232635/98 1998-08-19

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CN1238897C true CN1238897C (en) 2006-01-25

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JP4254006B2 (en) * 2000-04-21 2009-04-15 住友電装株式会社 Brake piece wear detection probe
JP2002080623A (en) * 2000-09-06 2002-03-19 Du Pont Toray Co Ltd Polyimide film and use thereof
JP4109839B2 (en) * 2001-06-01 2008-07-02 株式会社東芝 Semiconductor device
DE10344605B4 (en) * 2003-09-25 2008-09-18 Infineon Technologies Ag Interconnect connection structure and related manufacturing process
TWI462255B (en) * 2012-02-29 2014-11-21 矽品精密工業股份有限公司 Package structure, substrate structure and fabrication method thereof
CN103985645B (en) * 2014-05-27 2017-02-15 无锡必创传感科技有限公司 Semiconductor packaging piece and manufacturing method thereof

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