CN1237441C - Appts. and method of selectively controlling memory attribute - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective override of memory traits at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a memory trait for a memory reference prescribed by the extended instruction, where the memory trait for the memory reference cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and employs the memory trait to execute the memory reference.

Description

Apparatus and method for selectively controlling memory attributes

Comparison with Related Applications

(0001) This application claims priority to the following US application: Case No. 10/227527, filed August 22, 2002.

(0002) This invention is related to the following co-pending US patent applications, all having the same applicant and inventor. Taiwan application number filing date DOCKET NUMBER patent name 91116957 7/30/02 CNTR: 2176 Device and method for extending microprocessor instruction set 91116958 7/30/02 CNTR: 2186 Device and method for executing conditional instructions 91116956 7/30/02 CNTR: 2188 Device and method for selectively controlling condition code write-back 91116959 7/30/02 CNTR: 2189 Device for increasing the number of registers in a microprocessor 91124005 10/18/02 CNTR: 2190 Apparatus and method for extending microprocessor data schema 91124006 10/18/02 CNTR: 2191 Device and method for extending microprocessor address mode CNTR: 2192 Prohibition of storage inspection CNTR: 2193 Disabling of Selective Interrupts 91124007 10/18/02 CNTR: 2195 Non-scratch memory reference control device 91116672 7/26/02 CNTR: 2198 Apparatus and method for selectively controlling result write-back

technical field

(0003) The present invention relates to the field of microelectronics, especially a technology capable of incorporating extended address mode control into an existing microprocessor instruction set architecture.

Background technique

(0004) Since the early 1970s, the use of microprocessors has grown exponentially. From its earliest applications in the fields of science and technology, to the consumer field that has now been introduced into commerce from those specialized fields such as desktop and laptop computers, video game controllers, and many other common home and business devices and other products.

(0005) With the explosive growth in use, there has also been a corresponding improvement in technology, characterized by increasing requirements for the following items: faster speed, stronger addressability, faster memory access, larger operands, more general-purpose types of operations (such as floating-point operations, single instruction multiple data (SIMD), conditional moves, etc.), and additional special-purpose operations (such as digital signal processing functions and other multimedia computing). This has resulted in amazing technological advances in the field, and has been applied to the design of microprocessors, such as extended pipelining (extensive pipelining), super-scalar architecture (super-scalar architecture), cache structure, out-of-order processing ( out-of-order processing), burst access devices, branch prediction, and speculative execution. In short, today's microprocessors are astonishingly complex and powerful compared to when they first appeared 30 years ago.

(0006) But unlike many other products, another very important factor has limited and continues to limit the evolution of microprocessor architectures. Much of the complexity of today's microprocessors is due to this factor, legacy software compatibility. Under market considerations, many manufacturers choose to incorporate new architectural features into the latest microprocessor designs, but at the same time, in these latest products, they retain all the features required to ensure compatibility with older, so-called "legacy" microprocessors. "(legacy) capabilities required by the application.

(0007) Nowhere is this burden of legacy software compatibility more apparent than in the history of x86-compatible microprocessors. Everyone knows that today's 32/16-bit virtual-mode x86 microprocessors can still execute 8-bit real-mode applications written in the 1980s. Those skilled in the art also admit that there is a lot of related architectural "baggage" piled up in the x86 architecture just to support compatibility with legacy applications and operating modes. While in the past developers could add newly developed architectural features to existing instruction set architectures, today the tools to use these features, ie, programmable instructions, are relatively rare. More simply, he said, in some important instruction sets, there are no "redundant" instructions that allow designers to incorporate newer features into an existing architecture.

(0008) For example, in the x86 instruction set architecture, there is no undefined one-byte opcode state that is not yet used. In the main one-byte x86 opcode map, all 256 opcode states are already occupied by existing instructions. As a result, designers of x86 microprocessors must now choose between providing new features and preserving legacy software compatibility. To provide new programmable features, opcode states must be assigned to those features. If the existing ISA does not have redundant opcode states, some existing opcode states must be redefined to accommodate new features. Therefore, compatibility with older software has to be sacrificed in order to provide new features.

(0009) One area of concern to microprocessor designers today is how efficiently applications use cache structures. As caching technology has evolved, more and more features have been provided that allow system programmers to control when and how caches are used in a system. Early cache control features provided only on/off capability. By setting an internal register of the microprocessor, or by setting an external signal pin on its package (package) to true, the designer can enable the cache of the memory, or set the entire memory space to It is not cacheable (uncacheable). Non-cacheable memory references (ie, load/read and store/write) are sent to the system memory bus, resulting in the same latency as the external bus architecture. In contrast, memory references or accesses to a cache are sent to the system only when a cache miss occurs (i.e., the target of a memory reference is not valid in the internal cache) memory bus. The caching feature allows applications to run much faster, especially when the application repeatedly references the same data structures in memory.

(0010) Recent improvements in microprocessor architecture have given system designers more precise control over how cache features are used. These improvements allow the designer to define the properties of a range of addresses within the microprocessor's address space, where the definition is how references to those addresses by the microprocessor are performed according to its cache hierarchy way. In general, references to these addresses can be defined as non-cacheable, write combining, and write through. Write back or write protected. These properties are called memory attributes (attributes), or memory characteristics (traits). Therefore, the storage reference of the address with the write-back attribute will be sent to the cache, and speculatively assigned to the storage location therein. A storage reference to another address with the non-cacheable attribute is sent to the system bus without speculative allocation of storage locations.

(0011) However, it is outside the scope of this application to provide an in-depth description of memory attributes and how specific attributes are handled by a microprocessor with its caches. It is understood here that the art currently enables designers to assign a memory attribute to a memory region, and all subsequent memory references to addresses within the region will be based on the cache policy associated with the specified memory attribute deal with it, that's enough.

(0012) Although modern microprocessor designs allow different memory areas to be assigned different memory characteristics, the design is still limited in two important respects. First, the microprocessor instruction set architecture limits the ability to define/ Command execution that changes memory characteristics to a privilege level that is inaccessible to user-level applications. Thus, when a desktop/laptop microprocessor is activated, its operating system establishes the memory characteristics of the physical memory space before any user-level applications are started. Therefore, user-level applications cannot change the memory characteristics of the host system. Second, in modern microprocessors, the best processing level for establishing memory characteristics is the paging level. In common architectures that allow memory paging, the memory attributes of each memory page are further defined by the operating system in entries in the page directory/table. Thus, all references to addresses within a particular page will use the memory attribute assigned when the associated memory access operation was performed.

(0013) For many application programs, although the above-mentioned control features can significantly improve the execution speed of user-level application programs, the inventors of this case have noticed that there will still be some improvement in terms of other application programs. limitation, not only because modern memory property controls cannot be applied at the user level, but also because memory properties can only be established in page-level units. For example, if a user program that repeatedly accesses a first data structure makes an incidental reference to a second data structure, if the cache entry for the first data structure must be flushed to free up the cached If the space is used by the second data structure, the execution efficiency of the user program will be affected accordingly. Because the operating system does not predict the reference frequency of the user-level application program to the data structure, the data space of the application program is generally given a write-back feature, thus contributing to the aforementioned conflict. Programmers do not have tools for changing data space properties to force the incidental reference to be forwarded to the memory bus (eg, assigning non-cacheable properties to the second data structure) to eliminate the conflict.

(0014) What is needed, therefore, is an apparatus and method for incorporating selective memory attribute control features into an existing microprocessor instruction set architecture, wherein the microprocessor instruction set is a defined opcode Full occupancy, and the incorporation of this attribute control feature, in addition to not affecting the ability of a microprocessor conforming to legacy specifications to execute legacy applications, also provides programmers with the ability to modify memory attributes.

Contents of the invention

(0015) The present invention, like other aforementioned applications, is to overcome the problems and shortcomings of the above-mentioned and other known technologies. The present invention provides a better technique for extending the instruction set of a microprocessor beyond its current capabilities. Provides instruction-level memory feature control features. In one embodiment, an apparatus for instruction-level control of memory attributes within a microprocessor is provided. The device includes a translation logic and an extended execution logic. The translator translates an extended instruction into a micro instruction sequence. The extended command has an extended prefix and an extended prefix tag. The extension prefix specifies a memory property for a memory reference specified by the extended instruction, wherein the memory reference has a memory property that cannot be specified by an existing instruction of an existing instruction set. The extended prefix includes an attribute field for specifying the memory characteristic, wherein the memory characteristic includes one of several memory attributes. The extended preamble tag indicates the extended preamble, wherein the extended preamble tag is an operation code originally specified according to another architecture in the existing instruction set. The extended executor is coupled to the translator for receiving the microinstruction sequence and using the memory property to execute the memory reference. Wherein the translator includes: an escaped instruction detector for detecting the extended preamble tag; an instruction decoder for determining an operation to be performed, wherein the operation includes the memory reference; and an extended translation An encoder, coupled to the escaped instruction detector and the instruction decoder, is used to determine the memory characteristic and specify the memory characteristic in the microinstruction sequence.

(0016) It is an object of the present invention to propose a microprocessor device that extends the existing instruction set to provide selective control of memory characteristics. The microprocessor device has a translator configured to receive extended instructions. The extended instruction specifies memory attributes for a memory access, wherein the extended instruction includes a selected opcode in the existing microprocessor instruction set, followed by an n-bit extended preamble. The selected opcode specifies the extended instruction, and the n-bit extended preamble specifies the memory attribute. The memory attribute of the memory access cannot otherwise be specified by an instruction of the existing instruction set. Wherein the n-bit extended preamble includes a memory attribute field configured to specify the memory attribute, wherein the memory attribute includes one of several memory access attributes. The translator receives the extended instruction and generates a microinstruction sequence to instruct the microprocessor to perform the memory access, wherein the memory access will be performed according to the memory attribute. The translator includes: an escaped instruction detector for detecting the selected opcode within the extended instruction; an instruction decoder for decoding the remainder of the extended instruction to determine the memory access ; and an extended decoder, coupled to the escaped instruction detector and the instruction decoder, for decoding the n-bit extended preamble and specifying the memory attribute within the microinstruction sequence.

(0017) Another object of the present invention is to provide an apparatus for adding an instruction-level memory characteristic control feature to an existing instruction set. The apparatus includes a translator that receives and translates an instruction including an escape flag and a set of accompanying parts, wherein the escape flag is an opcode within the existing instruction set; the The accompanying part includes a memory property specifier for specifying one of several memory properties for the memory access; and an extension executor coupled to the translator for performing the memory access using the specified memory property , wherein the legacy instruction set only specifies a default memory property for the memory access, and wherein the extended executor applies the specified memory property instead of the default memory property. Wherein, the translator includes: an escape flag detector, used to detect the escape flag, and indicate that the translation action of the accompanying part needs to be based on the extended translation agreement; and a decoder, coupled to the escape flag detector The device is used for executing the translation of the instruction according to the agreement of the existing instruction set, and performing the translation of the instruction according to the extended translation agreement, so as to enable the execution of the memory access according to the specified memory characteristic.

(0018) Another object of the present invention is to provide a method for extending an existing ISA to enable selective memory attribute control at the instruction level. The method includes: providing an extended instruction, the extended instruction including an extended instruction tag, an extended preamble and other parts, wherein the extended instruction tag is a first opcode item of the existing instruction set architecture; through the extending the preamble specifies a memory attribute to be applied to a corresponding memory access specified by the remainder of the extended instruction; the extended preamble includes an attribute field specifying the memory attribute, Wherein the memory property includes one of several memory properties; and applying the memory property to perform the memory access, wherein the apply action replaces a default memory property of the memory access with the memory property.

Description of drawings

(0019) The aforementioned and other purposes, features and advantages of the present invention will be better understood after coordinating the following descriptions and the accompanying icons:

(0020) Fig. 1 is a block diagram of the microprocessor instruction format of a related art;

(0021) Fig. 2 is a table, which describes the instructions in an instruction set architecture, how to correspond to the bit register state of an 8-bit operation code byte in the instruction format of Fig. 1;

(0022) Fig. 3 is a block diagram of the extended instruction format of the present invention;

(0023) FIG. 4 is a table showing how extended architecture features map to bit register states in an 8-bit extended preamble embodiment in accordance with the present invention;

(0024) FIG. 5 is a block diagram illustrating a pipelined microprocessor employing selective memory attribute control of the present invention;

(0025) FIG. 6 is a block diagram of an embodiment of an extended preamble for specifying extended memory characteristics in a microprocessor according to the present invention;

(0026) FIG. 7 is a block diagram of another embodiment of an extended preamble for specifying extended memory characteristics in a microprocessor according to the present invention;

(0027) FIG. 8 is a table illustrating an encoding example of typical memory characteristics in the extended preamble of FIG. 7;

(0028) Fig. 9 is the concrete block diagram of translation stage device in Fig. 5 microprocessor;

(0029) FIG. 10 is a block diagram of the extended actuator in the microprocessor of FIG. 5; and

(0030) FIG. 11 is a flowchart describing the operation of the method of the present invention for replacing memory features of a microprocessor.

Icon Description

100 Command Format 101 Preamble

102 Operation code 103 Address specifying element

200 8-bit opcode map 201 Opcode value

202 operation code F1H

300 Extended instruction format 301 Preamble

302 Operation code 303 Address specifying element

304 Extended Command Mark 305 Extended Preamble

400 8-bit preamble map 401 Architecture features

500 pipelined microprocessors 501 extractors

502 instruction cache/external memory

503 instruction queue 504 translator

505 Extended Translator 506 Microinstruction Queue

507 Actuator 508 Extended Actuator

600 Extended Preamble 601 Source Characteristic Field

602 Purpose field

700 Storage attribute prefix 701 Attribute field

702 source bit 703 destination bit

704 Spare field

Form 800

900 translation stager 901 activation status signal

902 Machine Specific Register 903 Extended Feature Field

904 instruction buffer 905 translator

906 Translation controller 907 Disable signal

908 Escape instruction detector 909 Extended decoder

910 Instruction Decoder 911 Control ROM

912 Microinstruction buffer 913 Operation code extension field

914 Micro operation code field 915 Purpose field

916 source field 917 displacement field

1000 Extended execution stager 1001 Extended micro-instruction buffer

1002 address buffer 1003 address buffer

1004 Destination operand buffer 1005 Extended accessor

1006 Memory Characteristic Descriptor 1007 Cache

1008 Bus Unit 1009 Access Controller

1010 store buffer 1011 cache

1012 Bus 1013 Bus

1014 store buffer 1015 source operand buffer

1100-1128 The operation flow of the method for replacing the memory characteristic of a microprocessor

Detailed ways

(0031) The following description is provided in the context of a specific embodiment and its prerequisites to enable those of ordinary skill in the art to utilize the present invention. However, various modifications to this preferred embodiment will be readily apparent to those skilled in the art, and the general principles discussed herein can be applied to other embodiments as well. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

(0032) The previous article has discussed the background of how to expand its architectural features in today's microprocessors to exceed the capabilities of related instruction sets. In view of this, in FIG. 1 and FIG. 2 , an example of related technology will be discussed. The discussion here highlights the constant dilemma that microprocessor designers face when, on the one hand, they want to incorporate newly developed architectural features into their microprocessor designs, but on the other hand, they want to retain the implementation of application capabilities. In the example of Figures 1-2, a fully occupied opcode map has precluded the possibility of adding new opcodes to the example architecture, thereby forcing the designer to either choose to incorporate new features at the expense of some degree of Legacy software compatibility, or abandon the latest developments in the architecture, in order to maintain the compatibility of the microprocessor with legacy applications. Following the discussion of the related art, in Figures 3 through 11, a discussion of the present invention will be provided. By utilizing an existing but unused opcode as a preamble tag for an extended instruction, the present invention allows microprocessor designers to overcome the limitations of fully utilized instruction set architectures, while allowing them to provide programmers with an instruction-level The ability to assign memory characteristics to a particular memory reference while maintaining compatibility with legacy applications.

(0033) Please refer to FIG. 1 , which is a block diagram of a related art microprocessor instruction format 100 . The instruction 100 of the related art has a variable number of data items 101-103, each of which is set to a specific value, and together constitutes a specific instruction 100 of the microprocessor. The specific instruction 100 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to an internal register, or from the internal register to memory. In general, the operation code item 102 in the instruction 100 specifies the specific operation to be performed, and the optional (optional) address designation meta-item 103 is located after the operation code 102 to specify additional information about the specific operation, such as how to The operation is performed, where are the operands located, etc. The instruction format 100 also allows the programmer to add a preamble item 101 before an opcode 102 . When the specific operation specified by the operation code 102 is executed, the preamble 101 is used to indicate whether to use a specific architectural feature. In general, these architectural features apply to most of the operations specified by any opcode 102 in the instruction set. For example, preamble 101 exists today in some microprocessors that can perform operations using virtual addresses of different sizes (eg, 8-bit, 16-bit, 32-bit). And when many of these processors are programmed to a preset address size (such as 32 bits), the precode 101 provided in their individual instruction sets still enables programmers to selectively replace (override) the preset address size (for example, to generate a 16-bit virtual address). The selectable address size is just one example of an architectural feature that can be applied to numerous operations (eg, add, subtract, multiply, Boolean, etc.) that can be specified by opcodes 102 in many modern microprocessors.

(0034) The instruction format 100 shown in FIG. 1 has a well-known example in the industry, the x86 instruction format 100, which is used by all modern x86-compatible microprocessors. More specifically, he said that the x86 instruction format 100 (also known as the x86 instruction set architecture 100 ) uses an 8-bit preamble 101 , an 8-bit operation code 102 and an 8-bit address designator 103 . The x86 architecture 100 also has several preambles 101, two of which replace the default address/data size of the x86 microprocessor (ie opcode states 66H and 67H), and the other instructs the microprocessor to follow a different translation rules to interpret the following operation code byte 102 (that is, the preamble value 0FH, which makes the translation action be performed according to the so-called two-byte operation code rule), and other preamble codes 101 make the special operation repeated , until the repetition condition is satisfied (that is, the REP operation code: F0H, F2H and F3H).

(0035) Please refer to FIG. 2, which shows a table 200 for describing how an instruction 201 of an instruction set architecture corresponds to a bit value of an 8-bit opcode byte 102 in the instruction format of FIG. 1 . Table 200 presents an example of an 8-bit opcode map 200 that associates up to 256 values of an 8-bit opcode entry 102 to corresponding microprocessor opcode instructions 201 . The table 200 maps a specific value of the operation code item 102, such as 02H, to a corresponding operation code instruction 201 (ie, instruction I02 201). In the example of the x86 opcode diagram, as is well known to those skilled in the art, the opcode value 14H is mapped to the x86 Add with Carry (ADC) instruction, which converts an 8-bit immediate The operand is added to the contained value of the architectural register AL. Those skilled in the art will also find that the x86 preamble 101 mentioned above (ie, 66H, 67H, 0FH, F0H, F2H, and F3H) is the actual opcode value 201, which, in a different context, specifies the desired The particular architectural extension is applied to the operation specified by the opcode entry 102 that follows. For example, adding the preamble 0FH before the operation code 14H (normally, it is the aforementioned ADC operation code) will cause the x86 processor to perform an "unpack and insert low-compression single-precision floating-point value" (Unpack and Interleave Low PackedSingle-Precision Floating-Point Values) operation, not the original ADC operation. Features such as those described for the x86 example are partially enabled in modern microprocessors because the instruction translator/decoder within the microprocessor interprets the items 101-103 of an instruction 100 in sequence. So in the past, using a specific opcode value as the preamble 101 in the instruction set architecture allowed microprocessor designers to incorporate many advanced architectural features into the design of a microprocessor compatible with legacy software without A negative impact on the execution of legacy programs that do not use those particular opcode states. For example, an old program that never used the x86 opcode 0FH can still execute on today's x86 microprocessors. And a newer application, by using the x86 opcode 0FH as the prefix 101, can use many newly incorporated x86 architecture features, such as single instruction multiple data (SIMD) operations, conditional move operations, and so on.

(0036) Although architectural features have been provided in the past by designating available/redundant opcode values 201 as preambles 101 (also known as architectural signatures/pointers 101 or escaped instructions 101), many instruction set architectures 100 in Providing functional enhancements is still hindered for a very straightforward reason: all available/redundant opcode values have been used up, i.e. all opcode values in opcode map 200 have been constructed specified. When all available values are assigned as opcode entry 102 or preamble entry 101, there are no remaining opcode values available for incorporating new features. This serious problem exists in many microprocessor architectures today, forcing designers to choose between adding architectural features and retaining compatibility with legacy programs.

(0037) It is worth noting that the instruction 201 shown in FIG. 2 is expressed in a general way (ie I24, I86), rather than specifically referring to actual operations (such as carry accumulation, subtraction, XOR). This is because, in several different microprocessor architectures, the fully occupied opcode map 200 has architecturally precluded the possibility of incorporating newer advances. Although the example of FIG. 2 refers to an 8-bit opcode entry 102, those skilled in the art will recognize that the particular size of the opcode 102 results from the fully occupied opcode structure 200 being discussed as a special case. Apart from the problem, other aspects are irrelevant to the problem itself. Thus, a fully occupied 6-bit opcode map would have 64 architecturally assignable opcodes/preambles 201 and would not provide usable/redundant opcode values for expansion.

(0038) Another alternative method is not to completely abolish the original instruction set and replace it with a new format 100 and operation code map 200, but only for a part of the existing operation code 201, with new instructions Means substitution, as shown in operation codes 40H to 4FH in Figure 2 . With this hybrid technique, the microprocessor can operate independently in one of two modes: the old mode, using opcodes 40H-4FH, which still have rules to interpret, or in another modified mode ( enhanced mode), at this time, the operation codes 40H-4FH are interpreted according to the enhanced architectural rules. This technology does allow designers to incorporate new features into their designs, however, when a microprocessor conforming to the legacy specification is run in enhanced mode, the disadvantage still exists because the microprocessor cannot execute any application using opcodes 40H-4FH program. Therefore, from the standpoint of retaining the compatibility of old software, it is still unacceptable to be compatible with old software/enhanced technology.

(0039) However, for the instruction set 200 where the opcode space has been fully occupied, and this space covers all applications executed on microprocessors conforming to the old specifications, the inventors of the present case have noticed that the opcode 201 usage, and they also observed that, although some instructions 202 are architecturally specified, they are not used in applications that can be executed by the microprocessor. The instruction IF1 202 described in FIG. 2 is an example of this phenomenon. In fact, the same opcode value 202 (ie, F1H) is mapped to an effective instruction 202 that is not used in the x86 instruction set architecture. Although the unused x86 instruction 202 is a valid x86 instruction 202 that instructs an architecturally specified operation to be performed on an x86 microprocessor, it is not used in any operation that can be performed on a modern x86 microprocessor. application. This special x86 instruction 202 is called In Circuit Emulation Breakpoint (In Circuit Emulation Breakpoint) (also known as ICEBKPT, opcode value is F1H), and was previously used exclusively for a now defunct microprocessor emulation device. middle. The ICE BKPT 202 has never been used in applications other than in-circuit simulators, and previous in-circuit simulation devices using the ICE BKPT 202 no longer exist. Thus, in the case of x86, the present inventors have discovered a tool within a fully occupied instruction set architecture 200 to allow the design of microprocessors to incorporate advanced architectural features without sacrificing legacy software compatibility. In a fully occupied instruction set architecture 200, the present invention utilizes an architecturally specified but unused opcode 202 as a pointer marker to indicate an n-bit preamble to follow, thus allowing microprocessor design One can incorporate up to 2n of the most recently developed architectural features into a microprocessor design while retaining full compatibility with all legacy software.

(0040) The present invention provides an n-bit extended memory characteristic specifier preamble to use the preamble mark/extend the concept of the preamble, thereby allowing the programmer to, in a microprocessor, according to each instruction Assign a memory attribute to a corresponding memory access operation. When the corresponding memory access operation is performed, the memory attribute is used in place of a default attribute specified by the memory property descriptor table/device previously created by the operating system program. The present invention will now be discussed with reference to FIGS. 3 to 11 .

(0041) Please refer to FIG. 3 , which is a block diagram of the extended instruction format 300 of the present invention. Very similar to the format 100 discussed in FIG. 1 , the extended instruction format 300 has a variable number of instruction items 301 - 305 , each of which is set to a specific value and collectively constitutes a specific instruction 300 for the microprocessor. The specific instruction 300 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to a register of the microprocessor. Generally speaking, the operation code item 302 of the instruction 300 specifies a specific operation to be performed, and the optional address designation meta-item 303 is placed after the operation code 302 to specify additional information related to the specific operation, such as how to perform the operation , the register where the operand is located, the direct and indirect data used to calculate the memory address of the source/result operand, and so on. The instruction format 300 also allows the programmer to prefix an opcode 302 with a prefix item 301 . When the specific operation specified by the opcode 302 is executed, the preamble item 301 is used to indicate whether to use the existing architectural features.

(0042) However, the extended instruction 300 of the present invention is a superset (superset) of the aforementioned instruction format 100 of FIG. before all remaining items 301-303 in extension instruction 300. These two additional items 304 and 305 allow the programmer to specify a memory property for the memory reference specified by the extended instruction 300, wherein the memory property corresponding to the memory reference cannot otherwise be determined by an existing microprocessor conforming to the legacy specifications. There are instruction sets to specify. Optional items 304 and 305 are an extended preamble flag 304 and an extended memory characteristic specifier preamble 305 . The extended prefix flag 304 is another architecture-specific opcode in a microprocessor instruction set. In an x86 embodiment, the extended preamble flag 304, or escape flag 304, is in opcode state F1H, which was used earlier for the ICEBKPT instruction. The escape flag 304 indicates to the microprocessor that the extended preamble 305, or extended feature specifier 305, which specifies a memory corresponding to a specified memory access, is to follow Attributes. In one embodiment, the escape flag 304 indicates that the accompanying parts 301-303 and 305 of a corresponding extended instruction 300 specify memory accesses to be performed by the microprocessor. A memory property specifier 305, or extended preamble 305, specifies one of several memory properties for the memory to access. An extended actuator within the microprocessor executes the memory access according to the specified memory properties, thus superseding the default memory properties previously specified by other means, including using the controls available in modern microprocessor architectures Register bits, memory type registers, page tables, and other types of memory attribute descriptors.

(0043) The selective memory attribute control technique of the present invention is summarized here. An extended instruction is configured to specify a memory attribute for a memory access of an existing microprocessor instruction set, wherein the memory attribute of the memory access cannot otherwise be specified by instructions of the existing microprocessor instruction set. The extended instruction includes one of the opcodes/instructions 304 of the legacy instruction set and an n-bit extended preamble 305 . The selected opcode pair instruction acts as a pointer 304 to indicate that the instruction 300 is an extended feature instruction 300 (i.e., it specifies an extension of the microprocessor architecture), and the n-bit feature prefix 305 indicates the storage properties. In one embodiment, the extended preamble 305 has a size of eight bits and can specify up to 256 different attributes or combinations of memory attributes and other extended features. For an n-bit preamble embodiment, up to 2n different memory characteristics can be specified.

(0044) Referring now to FIG. 4, a table 400 shows how the memory attributes of a given memory reference map to the bit register states of an 8-bit extended preamble embodiment in accordance with the present invention. Similar to the opcode map 200 discussed in FIG. 2 , the table 400 of FIG. 4 presents an example of an 8-bit extended preamble map 400 that correlates up to 256 values of an 8-bit extended preamble entry 305 to A corresponding memory characteristic 401 of a microprocessor conforming to an old specification (such as E34, E4D, etc.). In an x86 embodiment, the 8-bit extended feature preamble 305 of the present invention is provided for instruction level control of memory features 401 (ie, E00-EFF) that are part of the current x86 instruction set The architecture is not specified at the instruction level.

(0045) The extended features 401 shown in FIG. 4 are expressed in a general manner, rather than specifically referring to actual features, so the technology of the present invention can be applied to various architectural extensions 401 and specific instruction sets architecture. Those skilled in the art will recognize that many different architectural features 401, some of which were mentioned above, can be incorporated into an existing instruction according to the escape tag 304/extended preamble 305 technique described herein. set. The 8-bit preamble embodiment of FIG. 4 provides a maximum of 256 different signatures 401 , while an n-bit preamble embodiment has a programmed selection of up to 2n different signatures 401 .

(0046) Referring now to FIG. 5, it is a block diagram illustrating a pipelined microprocessor 500 for performing selective memory attribute control operations according to the present invention. Microprocessor 500 has three distinct types of stages: fetch, translate, and execute. The fetch stage has a fetcher 501 that fetches instructions from an instruction cache 502 or external memory 502 . The fetched instructions are sent to the translation stage via the instruction queue 503 . The translation stage has a translator 504 coupled to a microinstruction queue 506 . Translator 504 includes extended translator 505 . The execution phase has an actuator 507 with an extension actuator 508 inside.

(0047) According to the present invention, during operation, the fetcher 501 fetches formatted instructions from the instruction cache/external memory 502 and puts these instructions into the instruction queue 503 according to their execution order. These instructions are then extracted from the instruction queue 503 and sent to the translator 504 . The translator 504 translates/decodes each incoming instruction into a corresponding sequence of microinstructions to instruct the microprocessor 500 to perform operations specified by these instructions. According to the present invention, the extended translator 505 detects those instructions marked with the extended preamble to perform translation/decoding corresponding to the extended memory property specifier preamble. In an x86 embodiment, the extended translator 505 is configured to detect an extended preamble flag whose value is F1H, which is an x86 ICE BKPT opcode. An extended microinstruction field is provided in microinstruction queue 506 to allow specification of the memory characteristics of the associated memory reference specified by the accompanying portion of the instruction.

(0048) the microinstruction is sent from the microinstruction queue 506 to the executor 507, wherein the extended executor 508 is configured to execute a specified memory reference according to a preset memory characteristic (defined by an existing memory characteristic descriptor tool), or Configured to utilize a memory characteristic programmed by the extended preamble of the present invention at the user level, as specified by the extended microinstruction field, to replace the default memory characteristic. In a specific embodiment, the memory characteristics are assigned in units of cache lines.

(0049) Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of a modern pipelined microprocessor 50. In fact, a modern pipelined microprocessor 500 may include up to to 30 different pipeline stages. However, these stages can be broadly categorized into three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to point out the necessary components required by the foregoing embodiments of the present invention. For the sake of clarity, unrelated components of microprocessor 500 are not shown.

(0050) Please refer to FIG. 6 , which is a block diagram of an embodiment of an extended preamble 600 for specifying memory attributes of a programmed memory access in a microprocessor according to the present invention. The memory trait specifier preamble 600 has a size of 8 bits and includes a source trait field 601 and a destination trait field 602 . The source attribute field 601 specifies a memory attribute for the source operand memory access (i.e., load, read) specified by the rest of an associated extended instruction, and the destination attribute field 602 specifies the destination operand memory for the remainder Access (ie store, write) specifies a memory attribute. Thus, an example of an 8-bit preamble 600 may specify one of 16 different memory characteristics, both the source and destination operands, that may be used in place of the predetermined values specified by the associated address range or memory page. set characteristics. The embodiment shown in FIG. 6 specifies a single source memory identity for all source operand addresses associated with corresponding instructions, and a single (possibly different from the foregoing) destination memory identity for all destination operands. Those skilled in the art will find that the source and destination attributes can be specified separately, which is particularly useful in conjunction with repeating string instructions such as REP MOVS of the x86 architecture. A modification of the above embodiment provides a corresponding destination property field 602 and source property field 601 for each destination/source operand referenced by the corresponding instruction, thereby increasing/decreasing the bits of the preamble 600 by an equal amount.

(0051) Please refer to FIG. 7 , which is a block diagram of another embodiment of an extended preamble 600 for specifying memory attributes of a programmed memory access in a microprocessor according to the present invention. The memory attribute preamble 700 has a size of 8 bits and includes an attribute field 701, a source bit 702, a destination bit 703 and a spare field 704. The 3-bit attribute field 701 is a memory access operation specified by a corresponding instruction Specifies one of 8 different memory characteristics. The source bit 702 enables the attribute specified by the attribute field 701 for all source operand memory accesses, and the destination bit 703 enables the specified attribute for all destination operand memory accesses. Thus, an embodiment of the 8-bit preamble 700 may designate one of eight different memory characteristics that may be used to replace the associated Preset characteristics to which address ranges or memory pages are specified.

(0052) Please refer now to FIG. 8, which is a table illustrating an encoding example of typical memory characteristics of the fields of the extended preamble 700 of FIG. Table 800 has an attribute row ATTR and a property row TRAIT. The value of attribute field 701 in the ATTR row is mapped to a corresponding memory characteristic in the TRAIT row. In this coding example, common memory characteristics such as non-cacheable (value 000) and write-back (value 011) are provided, however those skilled in the art will find that other memory features are suitable for a particular microprocessor architecture. Properties, can also be coded through the attribute fields 601, 602, 701 of FIGS. 6 and 7.

(0053) Please refer to FIG. 9 , which is a specific block diagram of the translation stager 900 in the microprocessor of FIG. 5 . The translation stager 900 has an instruction buffer 904 which provides extended instructions to the translator 905 according to the present invention. The translator 905 is coupled to a machine specific register 902 having an extended feature field 903 . Translator 905 has a translation controller 906 that provides a disable signal 907 to an escaped instruction detector 908 and an extended decoder 909 . The escaped instruction detector 908 is coupled to the extended decoder 909 and an instruction decoder 910 . The extension decoder 909 and the instruction decoder 910 access a control read-only memory (ROM) 911 in which template microinstruction sequences corresponding to certain extension instructions are stored. Translator 905 also includes a micro-op buffer 912 having an opcode extension field 913 , a micro-opcode field 914 , a destination field 915 , a source field 916 and a displacement field 917 .

(0054) In operation, during power-up of the microprocessor, the state of the extension field 903 in the machine-specific register 902 is determined by the signal power-up state 901 to indicate whether the particular microprocessor can Translating and executing the extended instructions of the present invention to replace the default memory attributes of the microprocessor. In one embodiment, signal 901 is derived from a feature control register (not shown) that reads a fuse array (fuse array) (not shown) configured at manufacture . The machine specific register 902 sends the state of the extended features field 903 to the translation controller 906 . The translation controller 906 controls the instructions fetched from the instruction buffer 904 to be interpreted according to the extended translation rules or common translation rules. Providing such a control feature may allow a supervisory application (eg, BIOS) to enable/disable extended execution features of the microprocessor. If extended features are disabled, instructions with opcode states selected as extended feature flags are translated according to the usual translation rules. In a specific embodiment of x86, the operation code state F1H is selected as a flag, and under common translation rules, encountering F1H will cause an illegal instruction exception (exception). If extended translation is disabled, the instruction decoder 910 will translate/decode all incoming instructions and configure all fields 913 to 917 of the microinstruction 912 . However, under the extended translation rule, if a token is encountered, it will be detected by the escaped instruction detector 908 . The escaped instruction detector 908 will instruct the extended decoder 909 to translate/decode the extended preamble portion of the extended instruction according to the extended translation rules, and configure the opcode extension field 913 to indicate the Memory accesses the memory characteristics to be applied. The instruction decoder 910 will translate/decode the rest of the extended instruction and configure the micro-opcode field 914 , source field 916 , destination field 915 and displacement field 917 of the microinstruction 912 . Certain specific instructions will result in access to the control ROM 911 to obtain the corresponding microinstruction sequence template. The configured microinstructions 912 are sent to a microinstruction queue (not shown in the figure) for subsequent execution by the processor.

(0055) Please refer to FIG. 10 , which is a block diagram of the extended execution stage 1000 in the microprocessor of FIG. 5 . The extended execution stage 1000 has an extended access logic 1005, which is coupled to a cache 1007 and a bus unit 1008 via buses 1012 and 1013, respectively. The bus unit 1008 is used to guide the memory access operation (memory transaction) on the memory bus (not shown). According to the present invention, the extended accessor 1005 receives microinstructions from an extended microinstruction buffer 1001 in the previous stage of the microprocessor, receives two address operands from address buffers 1002 and 1003, and receives two address operands from the destination operand buffer 1004. Receives a destination operand. Extended accessor 1005 is also coupled to a number of memory descriptors 1006 configured according to the architecture conventions of the host microprocessor. Extended accessor 1005 includes an access controller 1009, a store buffer 1010 and a load buffer device 1011. The load buffer 1011 sends a source operand output to a source operand buffer 1015 .

(0056) Operationally, the extended executor 1000 is used to perform memory accesses, read operands from memory, and write operands to memory, as indicated by the microinstructions in the extended microinstruction buffer 1001 . When performing a load/load operation, access controller 1009 receives one or more memory addresses from address buffers 1002 and 1003 and reads memory property descriptor 1006 to determine memory properties associated with the load operation. In an x86 embodiment, the memory property descriptor 1006 includes x86 cache and paging control registers, paging directory and paging table entries, memory type range registers (memory type range register, MTTR), paging attribute table (paging attribute table, PAT) and external signal pins KEN#, wB/WT#, PCT and PWT. The access controller 1009 uses the information obtained from these sources 1006 to determine the default memory attributes for the load operation according to x86 hierarchical memory attribute conventions. For non-x86 embodiments, the access controller 1009 uses information obtained from the memory property descriptor 1006 to determine the default memory for the load operation according to the hierarchy memory attribute conventions corresponding to the particular architecture of the host microprocessor. Attributes. The memory address, along with its corresponding accessed attributes, is sent to the load buffer 1011. Load buffer 1011 obtains source operands from cache memory via bus 1012 or directly from system memory (not shown) via bus unit 1008, depending on the provided property attributes. The obtained source operands are sent to the source operand buffer 1015 synchronously with a pipeline clock signal (not shown). The extended microinstructions are also sent into the pipeline to the extended microinstruction register 1014 synchronously with the pipeline clock signal. In this way the source operand is sent to the next stage of the microprocessor.

(0057) When executing the write/store operation indicated by the extended microinstruction, the access controller 1009 receives the address data of the operation from the address buffers 1002 and 1003, and receives the operand to be stored from the buffer 1004. The access controller 1009 accesses the memory property descriptor 1006 as described above to determine the memory property corresponding to the store operation. The memory characteristics, address information and the destination operand are sent to the storage buffer 1010 . Depending on the particular attributes provided, store buffer 1010 writes the destination operand into cache 1007 via bus 1012 , or directly into system memory via bus unit 1008 .

(0058) The store buffer 1010 and the load buffer 1011 of the present invention are configured to perform store and load access operations according to the relevant processing requirements of the memory attribute model of the host processor, wherein the processing requirements include strong/weak Sorting conventions (such as hypothetical execution rules) and cache access principles. In one embodiment, the load and store operations are performed in separate pipeline stages of the host microprocessor.

(0059) For extended instructions that use optional memory attributes instead of preambles, the replaced memory characteristics of the associated memory access (i.e., load, store, or both load and store) are extended by the extended microinstruction buffer 1001 The opcode extension field (not shown) of the microinstruction is sent to the access controller 1009 . The access controller 1009, as previously described, uses the information obtained from the memory property descriptor 1006 to determine the default memory characteristics for the specified memory access. If the designated replacement characteristic is stronger than the corresponding default characteristic, the access controller 1009 sends the replacement characteristic together with the aforementioned address and/or destination operand to the store buffer 1010/load buffer 1011. If the specified replacement property is weaker than the corresponding default property, the access controller 1009 sends the default property together with the address and/or destination operand to the store buffer 1010/load buffer 1011. Thus, selective memory replacement is only performed according to the specific architecture used to enhance a memory characteristic. For example, in the x86 architecture, the non-cacheable nature of a memory access cannot be weakened to write-back. Conversely, the write-back feature cannot be enhanced to be non-cacheable. The characteristics to be used for memory accesses are given in units of lines, and in many modern desktop/laptop microprocessor architectures, the size of a cache line is 32 bytes.

(0060) Please refer to FIG. 11 , which is a flow chart describing the operation of the method for translating and executing the instruction that enables the programmer to replace the preset memory attribute in the microprocessor at the instruction level of the present invention. The flow begins at block 1102, where a program configured with extended feature instructions is sent to the microprocessor. The flow then proceeds to block 1104 .

(0061) In block 1104, the next instruction is fetched from cache/external memory. The flow then proceeds to decision block 1106 .

(0062) In decision block 1106, the next command extracted in block 1104 is checked to determine whether it includes an extended escape code of the present invention. In an x86 embodiment, the check is to detect opcode value F1(ICE BKPT). If the extended escape code is detected, the flow proceeds to block 1108 . If the extended escape code is not detected, the flow proceeds to block 1112 .

(0063) In block 1108, the extended preamble portion of the extended instruction is decoded/translated to determine a memory attribute that is designated as a default in place of the associated memory access specified by the next instruction storage properties. Flow then proceeds to block 1110 .

(0064) In block 1110, the memory attribute of the associated memory access is configured in an extension field of a corresponding microinstruction sequence. The flow then proceeds to block 1112 .

(0065) In block 1112, all remaining parts of the instruction are decoded/translated to determine the location of the specified memory access, register operand. The use of memory address specifiers and legacy architectural features specified by preambles according to the legacy microprocessor instruction set. The flow then proceeds to block 1114 .

(0066) In block 1114, a sequence of microinstructions is configured to specify the specified memory reference and its corresponding opcode extension. Flow then proceeds to block 1116 .

(0067) In block 1116, the microinstruction sequence is sent to a microinstruction queue for execution by the microprocessor. Flow then proceeds to block 1118 .

(0068) In block 1118, the microinstruction sequence is fetched by an address device of the present invention. The addresser generates an address for the memory access and sends the address to the extended executive. The flow then proceeds to block 1120 .

(0069) In block 1120, the extended executor uses the microprocessor architecture's memory characterization tool to determine a predetermined memory characteristic. The flow then proceeds to decision block 1122 .

(0070) An evaluation is performed at decision block 1122 to determine whether the cache/memory model of the microprocessor architecture allows the specified memory attribute to override the default attribute. If override is allowed, flow proceeds to block 1124 . If the override is not allowed, the flow proceeds to block 1126 .

(0071) In block 1124, perform the memory access by using the replaced memory attribute specified by the extended preamble field used in block 1108. Flow then proceeds to block 1128 .

(0072) In block 1126, the memory access is performed using the default memory attributes determined in block 1120. Flow then proceeds to block 1128 .

(0073) In block 1128, the method is complete.

(0074) Although the present invention and its objects. The features and advantages have been described in detail, and other embodiments may also be included within the scope of the invention. For example, the present invention has been described with respect to the technique of using a single, unused opcode state within a fully occupied ISA as a flag to indicate the extended feature prefix that follows. However, the scope of the present invention is not limited in any respect to a fully occupied ISA, or unused instructions, or a single flag. Rather, the invention covers instruction sets that are not fully mapped. Embodiments that have used opcodes and embodiments that have used more than one instruction flag. For example, consider an ISA without unused opcode states. An embodiment of the present invention includes selecting an opcode state as an escape flag, wherein the selection criteria are determined by market factors. Another embodiment includes using a particular combination of opcodes as a marker, such as successive occurrences of opcode state 7FH. Therefore, the essence of the present invention is that the use of a tag sequence followed by an n-bit extended preamble allows the programmer to specify at the instruction level memory attributes for memory accesses that cannot otherwise be determined by the microprocessor. Existing instructions in the instruction set of the processor are provided.

(0075) In addition, although the above uses a microprocessor as an example to illustrate the present invention and its purpose. The features and advantages are still apparent to those skilled in the art, and the scope of the present invention is not limited to the architecture of microprocessors, but covers all forms of programmable devices, such as signal processors. Industrial controllers, array processors, and other similar devices.

In a word, the above descriptions are only preferred embodiments of the present invention, and should not limit the implementation scope of the present invention. All equivalent changes and modifications made according to the claims of the present invention should still fall within the scope covered by the patent of the present invention.

Claims (19)

1. A device for providing instruction-level control of memory attributes in a microprocessor, characterized in that it comprises: A translator for translating an extended instruction into a sequence of microinstructions, wherein the extended instruction includes: an extended preamble and an extended preamble tag; wherein the extended preamble is used for the extended instruction specifying a memory reference specifying a memory property, wherein the memory reference's memory property cannot be specified by a legacy instruction of a legacy instruction set, the extended preamble including an attribute field specifying the memory property, wherein The memory attribute includes one of a plurality of memory attributes; and the extended preamble flag is used to mark the extended preamble, wherein the extended preamble flag is another specified opcode in the existing instruction set; an extended executor, coupled to the translator, for receiving the microinstruction sequence, and applying the memory property to execute the memory reference; Wherein the translator includes: an escaped instruction detector for detecting the extended preamble tag; an instruction decoder for determining an operation to be performed, wherein the operation includes the memory reference; and an extended translation An encoder, coupled to the escaped instruction detector and the instruction decoder, is used to determine the memory characteristic and specify the memory characteristic in the microinstruction sequence. 2. The device as claimed in claim 1, wherein the extended command further comprises command items of the existing command set. 3. The apparatus of claim 2, wherein the instruction item specifies an operation to be performed by the microprocessor, and wherein the operation includes the memory reference. 4. The apparatus of claim 1, wherein the memory reference comprises an operand load operation, an operand store operation or both. 5. The apparatus of claim 1, wherein the memory properties specify how a cache is used when the memory reference is executed. 6. The apparatus of claim 1, wherein the memory property specifies how the memory reference is ordered relative to other memory references. 7. The device of claim 1, wherein the extended preamble instructs the microprocessor to override a default memory characteristic when performing the memory reference. 8. The device of claim 1, wherein the plurality of memory attributes include non-cacheable, compound write, write through, write back and write protect. 9. A microprocessor device extending an existing instruction set to provide selective control of memory characteristics, comprising: A translator configured to receive an extended instruction and generate a sequence of microinstructions to instruct a microprocessor to perform a memory access, the extended instruction configured to specify a memory attribute of a memory access, wherein the extended instruction includes the There is a selected opcode in the instruction set followed by an n-bit extended preamble, the selected opcode identifies the extended instruction, and the n-bit extended preamble indicates the memory attribute, wherein the A memory attribute of a memory access that cannot otherwise be specified by an instruction of the existing instruction set; wherein the n-bit extended preamble includes a memory attribute field configured to specify the memory attribute, wherein the memory attribute includes a number of memory One of the fetch properties, wherein the memory access is to be performed according to the memory property; wherein the translator includes: an escape instruction detector for detecting the selected opcode in the extended instruction; an instruction decode a device for decoding the remainder of the extended instruction to determine the memory access; and an extended decoder coupled to the escaped instruction detector and the instruction decoder for decoding the n bits and specify the memory attribute within the microinstruction sequence. 10. The microprocessor device as claimed in claim 9, wherein said extended instruction further comprises: The remaining command items are configured to specify the memory access, wherein the memory attribute is used to replace a default memory attribute when the memory access is executed. 11. The microprocessor device of claim 9, wherein the memory access characteristics include non-cacheable, compound write, write through, write back and write protect. 12. A device for adding instruction-level memory characteristic control features to an existing instruction set, characterized in that it comprises: A translator that receives and translates an instruction that includes an escape flag and a set of accompanying parts, wherein the escape flag is an opcode within the existing instruction set; the accompanying parts include a memory attribute specifier, used to designate one of several memory attributes for memory access; and an extension implementer, coupled to the translator, executes the memory access using specified memory characteristics, wherein the legacy instruction set only specifies a default memory characteristic for the memory access, and wherein the extension The actuator uses the specified memory characteristics instead of the default memory characteristics; Wherein, the translator includes: an escape flag detector, used to detect the escape flag, and indicate that the translation action of the accompanying part needs to be based on the extended translation agreement; and a decoder, coupled to the escape flag detector The device is used for executing the translation of the instruction according to the agreement of the existing instruction set, and performing the translation of the instruction according to the extended translation agreement, so as to enable the execution of the memory access according to the specified memory characteristic. 13. The apparatus of claim 12, wherein the translator translates the escape flag and the accompanying part into corresponding microinstructions, and the corresponding microinstructions instruct the extended executor according to the specified The memory access is performed for the memory characteristics. 14. The device according to claim 12, wherein the memory characteristics include non-cacheable, compound write, write through, write back and write protection. 15. A method for extending an existing instruction set architecture to provide instruction-level selective memory attribute control, characterized in that the method comprises: providing an extended instruction, the extended instruction includes an extended instruction flag, an extended prefix and other parts, wherein the extended instruction flag is a first opcode item of the existing instruction set architecture; A memory attribute to be applied to a corresponding memory access specified by the extended preamble, wherein the memory access is specified by the rest of the extended instruction; the extended preamble includes an attribute field for specifying the memory characteristics, wherein the memory characteristics include one of several memory attributes; and Applying the memory attribute to perform the memory access, wherein the apply action replaces a default memory attribute of the memory access with the memory attribute. 16. The method of claim 15, wherein the act of specifying a memory attribute to be applied to a corresponding memory access comprises: The memory access is first specified in the remainder of the extended instruction, wherein the first specification includes using a second opcode entry in the existing instruction set architecture. 17. The method of claim 15, wherein after said act of specifying a memory attribute to be applied to a corresponding memory access and before said act of performing the memory access, Also includes: The extended instruction is translated into a sequence of microinstructions instructing an extended executor to perform the memory access according to memory attributes. 18. The method according to claim 17, wherein the action of translating the extended instruction comprises: within a translator, detecting the extension directive flag; and The extended preamble and the rest of the extended instruction are decoded according to extended translation rules to generate the microinstruction sequence. 19. The method of claim 15, wherein the act of specifying a memory attribute to be applied to a corresponding memory access comprises: Specify one of the following storage attributes as the storage attribute to override this default storage attribute: non-cacheable, write-composite, write-through, write-back, and write-protect.

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