CN1236381C - Coprocessor for realizing IC card RSA enciphered algorithm - Google Patents
Coprocessor for realizing IC card RSA enciphered algorithm Download PDFInfo
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- CN1236381C CN1236381C CN 02160499 CN02160499A CN1236381C CN 1236381 C CN1236381 C CN 1236381C CN 02160499 CN02160499 CN 02160499 CN 02160499 A CN02160499 A CN 02160499A CN 1236381 C CN1236381 C CN 1236381C
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Abstract
The present invention relates to coprocessor for realizing an IC card RSA enciphering algorithm, which comprises a main controlling module of a microprocessor, a data processing controlling module, a memory and a data processing unit, wherein the main controlling module of a microprocessor controls the initialization of the memory and the indirect control of the data processing and controlling module to the data processing unit; the data processing and controlling module directly controls the data processing unit to work; the memory reads and saves a user's various kinds of setting and initializing information from the main controlling module of a microprocessor, receives control signals of the data processing and controlling module, and saves the calculation results of the data processing unit; the data processing unit which processes inputted data in the memory under the control of the data processing and controlling module to complete the whole enciphering calculation saves processed resultes into the memory. In the present invention, when the secrecy of a system is raised, the area of a chip is reduced, the flexibility of application is enhanced, and the user cost is reduced.
Description
Technical field
The present invention relates to a kind of cryptographic algorithm coprocessor that is used for IC-card, especially refer to realize the coprocessor of RSA cryptographic algorithms.
Background technology
Along with improving constantly of expanding economy and e-finance level, intelligent IC (integrated circuit) card has become an indispensable part in the life gradually.It is widely used in identification, electronic transaction, fields such as personal information preservation.With respect to traditional magnetic stripe card or memory card, intellective IC card is because inside has CPU, and not only processing power is strengthened greatly, and has improved the secret ability of system.The smart card that wherein has rsa encryption coprocessor (chip) not only can provide strong data encryption ability, and supports authentication, and services such as signature have obtained to use widely.But similar products on the market, its performance is often not fully up to expectations.The most crucial computing of RSA Algorithm is a Montgomery Algorithm, takes advantage of and computing module-square and this computing can convert a series of moulds to, and the difference of the two is only different with the source of multiplier.Mould take advantage of square operation normally adopt Montgomery algorithm.At present a lot of chips adopt structure based on the fixed length multiplier to the realization of this algorithm, and chip area is bigger, in addition, is difficult to provide One Chip Solutions at different demands for security, lacks dirigibility and versatility, thereby causes user cost to rise.
Summary of the invention
The object of the present invention is to provide a kind of coprocessor of realizing the IC-card RSA cryptographic algorithms, it not only satisfies the demand of security of system, and reduces chip area, strengthens application flexibility, thereby reduces user's cost.
A kind of coprocessor of realizing the IC-card RSA cryptographic algorithms provided by the present invention, it is characterized in that: it comprises microprocessor main control module, data processing and control module, storer and data processing unit, wherein: microprocessor main control module, it links to each other respectively with data processing and control module with storer, the initialization of control store and control data processing and control module are controlled the data processing unit indirectly by this data processing and control module; Data processing and control module, it links to each other respectively with storer with microprocessor main control module, data processing unit, directly control data processing unit work, control store simultaneously, and communicate with microprocessor main control module; Storer, it links to each other respectively with data processing unit with microprocessor main control module, data processing and control module, read and store user's various settings and initialization information from microprocessor main control module, receive the control signal of data processing and control module, preserve the data processing unit operation result; Data processing unit, it links to each other respectively with storer with data processing and control module, under the control of data processing and control module, the input data in the storer is handled, and finishes whole cryptographic calculation, and the result after will handling is saved in the storer and goes.
The coprocessor of above-mentioned realization IC-card RSA cryptographic algorithms, wherein: data processing unit comprises first shift register group, second shift register group, totalizer, first selector, second selector, delivery logical block, multiplier data register and addition data generator, first shift register group, receive the input data of totalizer or external memory storage, finish the displacement accumulation function together with totalizer, and output in external memory storage and delivery logical block by second selector the result; Second shift register group is accepted the data input of the external memory storage and first shift register group, data is carried out shifting function, and output in storer and delivery logical block by second selector output data, as the control signal of delivery; The multiplier data register uses preserving for internal arithmetic from the multiplier data of external memory storage input, and output data is to the addition data generator; The delivery logical block is accepted the input of first shift register group and second shift register group, and the signal during with delivery becomes the input signal of displacement addition by the logical conversion equivalence, and outputs to first selector; First selector is accepted the input signal of second shift register or delivery logical block, selects one of them to output in the addition data generator; The addition data generator, under the control of first selector input signal, select to allow the multiplier data register data by or close; Totalizer is with the data addition generation carry of first shift register and addition data generator; Second selector selects a conduct to output to the data of external memory storage from the data input of first shift register group and second shift register group.
Adopted above-mentioned technical solution, the present invention not only provides strong data encryption ability for IC-card, satisfy the demand of security, and on the chip of small size very, just can realize whole RSA cryptographic algorithms, can go towards different user's requests by the programming of software simultaneously.Therefore, the present invention has reduced chip area when improving the system secrecy ability, strengthened application flexibility, has reduced user cost.
Description of drawings
Fig. 1 is the functional block diagram of coprocessor of the present invention;
Fig. 2 is the functional block diagram of the data processing unit in the coprocessor of the present invention.
Embodiment
As shown in Figure 1, a kind of coprocessor of realizing the IC-card RSA cryptographic algorithms provided by the present invention, it comprises microprocessor main control module 1, data processing and control module 2, storer 3 and data processing unit 4, wherein:
Microprocessor main control module 1, it links to each other respectively with data processing and control module 2 with storer 3, the initialization of control store 3 and control data processing and control module 2, by the indirect control of 2 pairs of data processing units 4 of this data processing and control module, this module can adopt common embedded 8051 controllers to realize;
Data processing and control module 2, it links to each other respectively with microprocessor main control module 1, data processing unit 4 and storer 3, directly control data processing unit 4 work, while control store 3, and communicate with microprocessor main control module 1, this module adopts microprogram implementation, by simple programming, control data processing unit 4 round-robin number of times have been realized application flexibility;
Data processing unit 4, it links to each other respectively with storer 3 with data processing and control module 2, under the control of data processing and control module 2, the input data in the storer 3 is handled, finish whole cryptographic calculation, and the result after will handling is saved in the storer 3 and goes.
As shown in Figure 2, above-mentioned data processing unit 4 comprises first shift register group 41, second shift register group 42, totalizer 47, first selector 45, second selector 48, delivery logical block 44, multiplier data register 43 and addition data generator 46, wherein
First shift register group 41, the input data and the totalizer 47 that receive totalizer 47 or external memory storage 3 are finished the displacement accumulation function together, and output in external memory storage 3 and delivery logical block 44 by second selector 48 result;
Second shift register group 42, accept the data input of the external memory storage 3 and first shift register group 41, data are carried out shifting function, and output in storer 3 and delivery logical block 44 by second selector 48 output data, as the control signal of delivery;
Multiplier data register 43 uses preserving for internal arithmetic from the multiplier data of external memory storage 3 inputs, and output data is to addition data generator 46.
Delivery logical block 44 is accepted the input of first shift register group 41 and second shift register group 42, and the signal during with delivery becomes the input signal of displacement addition by the logical conversion equivalence, and outputs to first selector 45;
First selector 45 is accepted the input signal of second shift register 42 or delivery logical block 44, selects one of them to output in the addition data generator 46;
Addition data generator 46, under the control of first selector 45 input signals, select to allow multiplier data register 43 data by or close;
Totalizer 47 is with the data addition generation carry of first shift register 41 with addition data generator 46;
Second selector 48 selects a conduct to output to the data of external memory storage 3 from the data input of first shift register group 41 and second shift register group 42.
From above system architecture, processor of the present invention has certain innovation on design concept.The characteristics of maximum of the present invention are to use the structure of displacement totalizer to realize long multiplication and the modulo operation that the Montgomery computing is required, with respect to the former structure based on multiplier, have relative less area like this; Simultaneously algorithm is realized being divided into data processing unit 4 and data processing and control module 2, and data processing and control module 2 adopts the method for designing of microprogram, can circulate to the data processing unit by simple programming, the figure place of expansion cryptographic calculation makes total system have very strong dirigibility.These all mean the lower production cost and the powerful market competitiveness.
Claims (1)
1. coprocessor of realizing the IC-card RSA cryptographic algorithms, it is characterized in that: it comprises microprocessor main control module (1), data processing and control module (2), storer (3) and data processing unit (4), wherein:
Microprocessor main control module (1), it links to each other respectively with data processing and control module (2) with storer (3), the initialization of control store (3) and control data processing and control module (2) are controlled data processing unit (4) indirectly by this data processing and control module (2);
Data processing and control module (2), it links to each other respectively with microprocessor main control module (1), data processing unit (4) and storer (3), directly control data processing unit (4) work, control store (3) simultaneously, and communicate with microprocessor main control module (1);
Storer (3), it links to each other respectively with microprocessor main control module (1), data processing and control module (2) and data processing unit (4), read and store user's various settings and initialization information from microprocessor main control module (1), receive the control signal of data processing and control module (2), preserve data processing unit (4) operation result;
Data processing unit (4), it links to each other respectively with storer (3) with data processing and control module (2), under the control of data processing and control module (2), input data in the storer (3) are handled, finish whole cryptographic calculation, and the result after will handling is saved in the storer (3) and goes;
Described data processing unit (4) comprises first shift register group (41), second shift register group (42), totalizer (47), first selector (45), second selector (48), delivery logical block (44), multiplier data register (43) and addition data generator (46)
First shift register group (41), receive the input data of totalizer (47) or external memory storage (3), and totalizer (47) finishes the displacement accumulation function together, and outputs in external memory storage (3) and delivery logical block (44) by second selector (48) result;
Second shift register group (42), accept the data input of external memory storage (3) and first shift register group (41), data are carried out shifting function, and output in storer (3) and delivery logical block (44) by second selector (48) output data, as the control signal of delivery;
Multiplier data register (43) uses preserving for internal arithmetic from the multiplier data of external memory storage (3) input, and output data is to addition data generator (46);
Delivery logical block (44) is accepted the input of first shift register group (41) and second shift register group (42), and the signal during with delivery becomes the input signal of displacement addition by the logical conversion equivalence, and outputs to first selector (45);
First selector (45) is accepted the input signal of second shift register (42) or delivery logical block (44), selects one of them to output in the addition data generator (46);
Addition data generator (46), under the control of first selector (45) input signal, select to allow multiplier data register (43) data by or close;
Totalizer (47) is with the data addition generation carry of first shift register (41) with addition data generator (46);
Second selector (48) selects a conduct to output to the data of external memory storage (3) from the data input of first shift register group (41) and second shift register group (42).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02160499 CN1236381C (en) | 2002-12-27 | 2002-12-27 | Coprocessor for realizing IC card RSA enciphered algorithm |
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| CN 02160499 CN1236381C (en) | 2002-12-27 | 2002-12-27 | Coprocessor for realizing IC card RSA enciphered algorithm |
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| CN1512322A CN1512322A (en) | 2004-07-14 |
| CN1236381C true CN1236381C (en) | 2006-01-11 |
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| CN 02160499 Expired - Fee Related CN1236381C (en) | 2002-12-27 | 2002-12-27 | Coprocessor for realizing IC card RSA enciphered algorithm |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103034893B (en) * | 2011-09-29 | 2017-02-08 | 航天信息股份有限公司 | Radio frequency card safety coprocessor and radio frequency identification reader-writer |
| CN104899522B (en) * | 2015-06-09 | 2018-01-30 | 网易（杭州）网络有限公司 | A kind of data processing method and device |
| CN107483178B (en) * | 2017-07-25 | 2020-08-28 | 深圳华视微电子有限公司 | Device for realizing secure Hash Algorithm SHA3 and smart card |
| CN113721840A (en) * | 2019-10-18 | 2021-11-30 | 华为技术有限公司 | Data access method and device and first computing equipment |
| CN112436941A (en) * | 2020-11-03 | 2021-03-02 | 海光信息技术股份有限公司 | Coprocessor, method, chip and electronic equipment supporting identification cipher algorithm |
| CN113031920B (en) * | 2021-05-20 | 2021-08-31 | 华控清交信息科技(北京)有限公司 | Chip and batch modulo operation method for chip |
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