CN1231846C - Cipher protection circuit to protect data in ROM - Google Patents
Cipher protection circuit to protect data in ROM Download PDFInfo
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- CN1231846C CN1231846C CN 01109545 CN01109545A CN1231846C CN 1231846 C CN1231846 C CN 1231846C CN 01109545 CN01109545 CN 01109545 CN 01109545 A CN01109545 A CN 01109545A CN 1231846 C CN1231846 C CN 1231846C
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Abstract
The present invention relates to a cipher protection circuit for protecting data in a read only memory, which is provided with an initial value generator, a shifting buffer, an operation circuit, an adder and a latch circuit, wherein the initial value generator generates two initial values with mutually repellent value domains; the shifting buffer stores the initial values temporarily and selectively loads the data in the read only memory and alters the contents in the data; the operation circuit processes the contents of the shifting buffer, and sends back the results to the shifting buffer for shift motion; the adder adds the data in the read only memory and the data with the same length in the shifting buffer to obtain ciphered data. The latch circuit latches the adder in the particular case to make the output of the adder maintained at a high potential or a low potential.
Description
Technical field
The present invention relates to cipher protection circuit, and particularly relate to a kind of cipher protection circuit of protecting ROM data.It can be applied to have in the device of ROM (read-only memory) in microprocessor and the microcontroller etc., it is stored data avoid illegal copies or use.
Background technology
At present, in 8 single chip microcontrollers, cipher protection circuit normally is made up of the password table of 64 bytes or 32 bytes.These password tables very big area that accounts in chip makes chip area become big and production cost improves.In addition, in case the password off-balancesheet of microcontroller is let out, then the program code that stores in the chip also has stolen danger.
Summary of the invention
In order to overcome the deficiencies in the prior art, fundamental purpose of the present invention is to provide a kind of cipher protection circuit of protecting the ROM (read-only memory) data, and it only needs the password table of 2 bytes, therefore can significantly dwindle chip area, and production cost is reduced effectively.
Another object of the present invention is to provide a kind of cipher protection circuit of protecting ROM data; it has more a calculation logical circuit (pseudorandom generator); its output content can be simultaneously with reference to initial value and ROM (read-only memory) data to upset, so the complicacy of encryption acts can further improve.And because this cipher protection circuit does not have decoding scheme to provide, so encrypted result can't crack, have splendid secret ability.
Purpose of the present invention can reach by following measure:
A kind of cipher protection circuit of protecting ROM data comprises:
One ROM (read-only memory) is in order to store data;
One pseudorandom generator according to an initial value, is encrypted this ROM (read-only memory) data; And
One totalizer, with the encrypted result of this pseudorandom generator, and this ROM (read-only memory) data addition, use the upset data that obtains.
A kind of cipher protection circuit of protecting ROM data comprises:
One initial value generator is in order to produce the initial value of first codomain or second codomain;
One offset buffer in order to keep in this initial value, also optionally to load this ROM (read-only memory) data, is used its data content of change;
One computing circuit calculates the data of this offset buffer and sends the result back to this offset buffer to carry out shift motion;
One totalizer, the data of equal length in this ROM (read-only memory) data of addition and this offset buffer is used the upset data that obtains; And
One latch circuit, the output of this totalizer of breech lock.
The present invention has following advantage compared to existing technology:
According to above-mentioned and other purpose, the present invention simultaneously carries out an additive operation with the source book and the initial value of ROM (read-only memory) as the input variable of pseudorandom generator and with the output of pseudorandom generator and the source book of ROM (read-only memory) again, use the upset source book, encrypted result can't be cracked.
In the present invention, can protect the cipher protection circuit of ROM data mainly to be formed by initial value generation device, offset buffer, computing circuit, totalizer and latch circuit.In this cipher protection circuit, the initial value generation device is the initial value that is used for producing two kinds of codomain mutual exclusions.Offset buffer be used for temporary above-mentioned codomain, and optionally load the ROM (read-only memory) data to change wherein content.Computing circuit is to be used for calculating the data of offset buffer and to send the result back to offset buffer to carry out shift motion.Totalizer is to be used for the data of equal length in addition ROM (read-only memory) data and the offset buffer, uses obtaining an encrypted result.Latch circuit then is a breech lock totalizer under specific circumstances, makes its output maintain fixing high voltage or low-voltage.
In this cipher protection circuit; because pseudorandom generator is not simultaneously to have the initial value of the source book of systematicness and initial value generation device as input variable; therefore encryption acts is very complicated; they are can be with the change of source book different and do not have decoding scheme to provide, and use and avoid the danger that is cracked.
In addition, in this cipher protection circuit, when offset buffer and initial value were 16, computing circuit can be according to f (x)=x
16+ x
12+ x
7The content of+x+1 arithmetic shift buffer is also sent result the lowest order of offset buffer back to, and simultaneously, other content of offset buffer is then towards the translation of most significant digit direction.Under this structure, when initial value was the codomain of FFFFH, the stored content of offset buffer can remain unchanged (because f (x)=1), and when initial value is the codomain of 0000H ~ FFFEH, the content of offset buffer then can make wherein content changing according to above-mentioned encryption.
Moreover in this cipher protection circuit, when the content of offset buffer storage satisfied a certain specified conditions, offset buffer can load the ROM (read-only memory) data to change wherein content, used the complicacy that improves encryption acts.Totalizer and latch circuit then respectively in order to the content of equal length in addition ROM (read-only memory) data and the offset buffer, reach the output in order to the breech lock totalizer, use further upset encrypted result.
For the aforesaid purpose of the present invention, feature and advantage De Gengyi are understood, be to enumerate preferred embodiment, and in conjunction with the accompanying drawings, further be described as follows.
Description of drawings
Fig. 1 is the calcspar that the present invention can protect the cipher protection circuit of ROM data; And
Fig. 2 is the circuit diagram that the present invention can protect the cipher protection circuit of ROM data.
Embodiment
For guaranteeing that original program code or other data that the inner ROM (read-only memory) of microcontroller is stored are not illegal copies and use and the intellecture property that ensures former book-maker; microcontroller can have cipher protection circuit (Scramble circuit) in indoor design usually; in order to the program code that encryption is read, make that they are different with the original program code, can't duplicate use.
Please refer to Fig. 1, this can protect the calcspar of the cipher protection circuit of ROM data for the present invention.
In this embodiment, deposit the ROM (read-only memory) data (ROM DATA) of desire protection in the inside ROM (read-only memory) 2 of microcontroller, as original program code or other data.Reference clock generator 3 is in order to the system clock that whole microcontroller is provided (CLOCK).Cipher protection circuit 1 is then in order to the ROM data (ROM DATA) of encrypting the desire protection and have: initial value generator 10, pseudorandom generator 20, totalizer 30 and latch circuit 40.
20 different initial values of foundation of pseudorandom generator (being provided by initial value generator 10) produce not homotactic numerical value, in order to carry out encryption acts and to obtain an encrypted result (Encryption pattern) with ROM (read-only memory) data (original program code or other data).For improving the complicacy of pseudorandom generator 20 when the encryption acts, making it that decoding scheme can't be provided, pseudorandom generator 20 is another variable with ROM (read-only memory) data (original program code or other data) more.The content of ROM (read-only memory) data (original program code or other data) is unpredictable; after therefore this cipher protection circuit 1 also can't provide decrypt circuit and encrypt ROM (read-only memory) data (original program code or other data), encrypted result also must be used in order to checking in the future by back-up.
40 of latch circuits make its output be fixed in high voltage or low-voltage according to a breech lock control signal (LOCK), breech lock totalizer 30 under specific circumstances.
Then, cooperate the careful explanation of Fig. 2 preferred embodiment of the present invention.Please refer to Fig. 2, this can protect the circuit diagram of the cipher protection circuit of ROM data for the present invention.
Identical with Fig. 1, in this embodiment, the inside ROM (read-only memory) (not shown) of microcontroller is the ROM (read-only memory) data that is used for storing the desire protection, as original program code or other data.Cipher protection circuit then according to different initial values with encrypt the ROM (read-only memory) data, it has: initial value generator 10, pseudorandom generator 20, totalizer 30 and latch circuit 40.
20 of pseudorandom generators are by two 8 bit shift buffer R1, the R2 of polyphone each other, two impact damper B1, B2, and multiplexer M1, or door O1 and reverser I1 constitute.As shown in FIG., initial value two input block Seed1/Seed2 producing circuit 10 are connected to 8 bit shift buffer R1, and are connected to 8 bit shift buffer R2 via impact damper B2 via impact damper B1 and multiplexer M1 respectively.In addition, or the loaded circuit S1 that constitutes of door O1 and reverser I1 then design between impact damper B1 and offset buffer R1, R2.When encryption acts began, initial gating pulse P (Init Load) can make the content of input initial value generator 10 input block Seed1/Seed2 be sent to offset buffer R1 and be sent to offset buffer R2 via impact damper B2 via multiplexer M1, impact damper B1.Subsequently, impact damper B1, B2 just close, make computing circuit L1 be able to handle and send the result lowest order of offset buffer R1, R2 back to according to the content of two offset buffer R1, R2, simultaneously, other location conten of two offset buffer R1, R2 is then towards the translation of most significant digit direction.In this embodiment, the relation of the content of computing circuit L1 and two offset buffer R1, R2 can be f (x)=x
15+ x
12+ x
7+ x+1.That is when initial value was FFFFH, the content of two offset buffer R1, R2 still remained unchanged after displacement, because f (x)=1; And when initial value was 0000H ~ FFFFEH, the content of two offset buffer R1, R2 then can and load the change of ROM (read-only memory) data and change according to initial value.
In addition, for improving the complicacy of encryption acts, pseudorandom generator 20 can design a loaded circuit S1 in addition, in order under specific circumstances the ROM (read-only memory) data is loaded offset buffer R1, R2.In this embodiment, if the content of offset buffer R1, R2 satisfies: the 6th equals 0, then loaded circuit S1 may command multiplexer M1 and impact damper B1, make 8 ROM (read-only memory) data transmission to offset buffer R1.Because the order of ROM (read-only memory) data is unpredictable, therefore, in this embodiment offset buffer R1, R2 content can change brokenly, make decoding scheme be difficult to provide.
In addition, 30 of totalizers be 8 ROM (read-only memory) data of addition OD and the equal length data in offset buffer R1, R2, chosen arbitrarily 0..5,7,8}ED also exports an encrypted result.
In sum, the present invention can protect the cipher protection circuit of ROM (read-only memory) data only to need the password table collocation one calculation logical circuit of 2 bytes, therefore can significantly dwindle chip area, and production cost is reduced effectively.In addition, the data of reading can be simultaneously with reference to initial value and ROM (read-only memory) data to upset encryption, therefore, the complicacy of encryption acts can further improve and is difficult to provide decoding scheme, has splendid secret ability.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when the change that can do a little and retouching, so protection scope of the present invention is when looking accompanying Claim and being as the criterion in conjunction with instructions and the accompanying drawing person of defining.
Claims (6)
1. the cipher protection circuit that can protect ROM data is characterized in that: comprising:
One ROM (read-only memory) is in order to store data;
One pseudorandom generator according to an initial value, is encrypted this ROM (read-only memory) data; This pseudorandom generator also comprises:
One offset buffer is deposited this initial value and this ROM (read-only memory) data; And
One computing circuit, the data that this offset buffer of computing is deposited is also sent result back to this offset buffer to carry out shift motion.
One totalizer, with the encrypted result of this pseudorandom generator, and this ROM (read-only memory) data addition, use the upset data that obtains.
2. the cipher protection circuit of protecting ROM data as claimed in claim 1 is characterized in that: wherein, when this offset buffer and this initial value were 16, this computing circuit can be according to f (x)=x
15+ x
12+ x
7The data of this offset buffer of+x+1 computing is also sent result back to the lowest order of this offset buffer, so, when this initial value is FFFFH, the data that this offset buffer is deposited can remain unchanged, and when this initial value was OOOOH ~ FFFEH, the data of this offset buffer then can be encrypted and be changed.
3. the cipher protection circuit of protecting ROM data as claimed in claim 2 is characterized in that: wherein, when the data of depositing when this offset buffer satisfied specified conditions, this ROM (read-only memory) data was to load this offset buffer to change its content.
4. the cipher protection circuit of protecting ROM data as claimed in claim 1 is characterized in that: wherein, this totalizer is the data of equal length in this ROM (read-only memory) data of addition and this offset buffer, uses this upset data that obtains.
5. the cipher protection circuit of protecting ROM data as claimed in claim 1 is characterized in that: more comprise a latch circuit, in order to the output of this totalizer of breech lock.
6. the cipher protection circuit that can protect ROM data is characterized in that: comprising:
One initial value generator is in order to produce the initial value of first codomain or second codomain;
One offset buffer in order to keep in this initial value, also optionally to load this ROM (read-only memory) data, is used its data content of change;
One computing circuit calculates the data of this offset buffer and sends the result back to this offset buffer to carry out shift motion;
One totalizer, the data of equal length in this ROM (read-only memory) data of addition and this offset buffer is used the upset data that obtains; And
One latch circuit, the output of this totalizer of breech lock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109545 CN1231846C (en) | 2001-03-30 | 2001-03-30 | Cipher protection circuit to protect data in ROM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109545 CN1231846C (en) | 2001-03-30 | 2001-03-30 | Cipher protection circuit to protect data in ROM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1378144A CN1378144A (en) | 2002-11-06 |
| CN1231846C true CN1231846C (en) | 2005-12-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01109545 Expired - Fee Related CN1231846C (en) | 2001-03-30 | 2001-03-30 | Cipher protection circuit to protect data in ROM |
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|---|---|
| CN (1) | CN1231846C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1293485C (en) * | 2003-07-23 | 2007-01-03 | 凌阳科技股份有限公司 | Processor unit and method for protecting data by data block confounding processing |
| IL234956A (en) * | 2014-10-02 | 2017-10-31 | Kaluzhny Uri | Bus protection with improved key entropy |
-
2001
- 2001-03-30 CN CN 01109545 patent/CN1231846C/en not_active Expired - Fee Related
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| CN1378144A (en) | 2002-11-06 |
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Granted publication date: 20051214 |