CN1230021A - Method of making memory unit array - Google Patents
Method of making memory unit array Download PDFInfo
- Publication number
- CN1230021A CN1230021A CN98105762A CN98105762A CN1230021A CN 1230021 A CN1230021 A CN 1230021A CN 98105762 A CN98105762 A CN 98105762A CN 98105762 A CN98105762 A CN 98105762A CN 1230021 A CN1230021 A CN 1230021A
- Authority
- CN
- China
- Prior art keywords
- dusts
- insulating barrier
- layer
- trench
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
A technology for manufacturing memory cell array includes forming multiple channels and one transistor on semiconductor substrate, depositing the first insulating layer to fill the channel and form multiple insulating blocks, depositing the second insulating layer, opening a window to expose semiconductor substrate and a corner of insulating block, etching the corner to form slot, depositing a doped polysilicon layer in slot, depositing electric conducting layer to fill the slot, etching to form conducting plug, forming the third insulating layer on conducting plug and its periphery to form buried bit line, and tampering to duffuse the dipping chemical in source/drain area and doped polysilicon layer for contacing.
Description
The present invention relates to the manufacture method of a kind of memory cell array (Memory Cell Array), particularly relate to a kind of manufacture method with memory cell array of buried bit lines (Buried Bit Line).This bit line that buries can be aimed at the transfering transistor (TransferTransistor) in (Self-Aligned) memory cell array automatically, and can not occupy additional space, can be applied to make the memory cell array of high density (High Density).
Improving the usefulness (Performance) of element and lowering the manufacture craft cost is the developing direction of semiconductor fabrication process.These targets successfully reach in the sub-micron (Sub-Micron) or the manufacture craft of microminaturization (Micro-Miniaturization).Toward the manufacture craft development of (Features) more on a small scale, the electric capacity quality in the element can be destroyed if desired, and electricresistance effect can become obviously, makes the usefulness reduction of element.And because the reducing of scale, the size of wafer (Chip) also can diminish, and makes integrated level increase and the cost of manufacture of individual wafer can reduce.
The dynamic random access memory that reduces of scale (Dynamic Random Access Memory; DRAM) extremely important in the manufacture craft of element.In the DRAM memory cell, all have the structure of stack capacitor (Stacked Capacitor) usually, and the position of stack capacitor is on the source electrode (Source) at transfering transistor or (Drain) district that drains.Then comprise a metal wire as for the bit line in the DRAM memory cell, extend out that insulating barrier can see through a contact hole (Contact Hole) and communicate with source electrode or drain region along an insulating barrier.Existing a kind of DRAM memory cell neutrality line Method for Area of dwindling is an idea of utilizing the bit line bury, and United States Patent (USP) 5250457 and 5364808 for example all can propose a kind of method of the bit line that buries in the transfering transistor manufacturing.Yet the buried bit lines in above-mentioned these inventions can make the bit line on the silicon base connect (Bit Line Coupling) increase, if by source/drain regions and silicon base insulation, then cannot defectiveness (Defect), and make and go up the difficult control of its rate of finished products (Yield).
In view of this, main purpose of the present invention is the manufacture method that proposes a kind of memory cell array, and particularly relevant for a kind of manufacture method with memory cell array of the bit line that buries.Bit line is buried in insulating oxide, or in shallow trench (Shallow Trench), or also can be among field oxide (FieldOxide Region).Therefore bit line can not occupy additional space, can improve the density of element, and bit line connects and reduce, and between the silicon base by the field oxide isolation of can insulating automatically.
For achieving the above object, the present invention proposes a kind of manufacture method of memory cell array, and its step is included at least and forms a plurality of Liang Gou in the semiconductor substrate.Deposit one first insulating barrier then,, form a plurality of insulating plugs in order to fill up a plurality of trench.Deposition one second insulating barrier forms one first opening thereon on the semiconductor-based end, exposes the semiconductor-based end, and the corner of exposing the insulating plug in a plurality of insulating plugs.Etching insulating plug corner forms a groove then, first polysilicon layer that deposition one is mixed in groove.Deposit a conductive layer afterwards again, in order to fill up groove, the step that caves in again forms a conductive plug.On conductive plug, reach periphery and form one the 3rd insulating barrier, form a bit line that buries.On the semiconductor-based end, form a transfering transistor, comprise a grid and source/drain regions.Carry out a tempering step, make impurity in first polysilicon layer of source/drain regions and doping to spread and contact.Deposition one the 4th insulating barrier on above-mentioned each layer, and form one second opening thereon, expose source/drain regions.Form one second polysilicon layer at the second opening periphery,, form a bottom electrode, on bottom electrode, form a dielectric layer, and on dielectric layer, deposit one the 3rd polysilicon layer, in order to form a top electrode in order to fill up second opening.So bottom electrode, dielectric layer and top electrode form a structure of piling up electric capacity.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 illustrate for according to a preferred embodiment of the invention, look schematic diagram on a kind of memory cell array;
Fig. 2 to Fig. 7 a illustrate for according to a preferred embodiment of the invention, a kind of memory cell array manufacturing step is along the generalized section of Figure 1A A ' line;
Fig. 7 b illustrate for according to a preferred embodiment of the invention, a kind of memory cell array manufacturing step is along the generalized section of Figure 1B B ' line; And
Fig. 8 and Fig. 9 illustrate for according to a preferred embodiment of the invention, the generalized section of stack capacitor manufacturing step in a kind of memory cell array.
The present invention proposes a kind of manufacture method of memory cell array, wherein has the structure of a stacking electric capacity to cover On the bit line that Gai Zaiyi buries. The bit line that buries can be in field oxide, also can be in insulation shallow Among the trench, or in other insulating oxide, can solve so existing bit line and take up space too big Problem. In addition, this bit line structure that buries have source electrode in the contiguous transfering transistor of auto-alignment/ The function of drain region is by the outside diffusion of impurity in bit line and the source/drain regions (Outdiffusion), can naturally the source/drain regions in the transfering transistor be connected with the bit line that is connected Together.
At first, please refer to Fig. 1, it illustrated for according to a preferred embodiment of the invention, looked schematic diagram on a kind of memory cell array.A plurality of shallow trench 12 have wherein filled up insulating material, in order to do the usefulness of insulation isolation.Around a plurality of shallow trench 12, be distributed with the zone of coming out at the semiconductor-based end 10.One bit line that buries 17 dots in Fig. 1, and it extends under the surface of a plurality of shallow canal structures 12, vertical with the bit line that buries 17 is polysilicon gate 13, and semiconductor substrate 10 is crossed in its crosscut.In addition, an opening 14 in order to do interlayer hole, can form one herein and pile up electric capacity 15.
Then, please refer to Fig. 2, it illustrated for according to a preferred embodiment of the invention, and a kind of memory cell array manufacturing step is along the generalized section of Figure 1A A ' line.Semiconductor substrate 10 is provided,, and forms a thin oxide layer (not shown) thereon along crystal face 100 cuttings of monocrystalline silicon.On the semiconductor-based end 10, utilize anisotropy (Anisotropic) reactive ion-etching (Reactive IonEtch then; RIE), with chlorine (Cl
2) be etchant (Etchant), form a plurality of trench 12.The degree of depth of a plurality of trench 12 arrives between about 6000 dusts about 4000 dusts, and according to element design principle (DesignRules), each trench 12 all has suitable width and spacing distance.Then, utilize Low Pressure Chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition; Or plasma reinforced chemical vapour deposition method (Plasma Enhanced Chemical Vapor Deposition LPCVD); PECVD), between about 300 ℃ to about 700 ℃ of temperature, deposition one first insulating barrier 21a on the semiconductor-based end 10, the oxide of silicon for example, in order to filling up a plurality of trench 12, and the thickness of the first insulating barrier 21a is about 2/3rds of a plurality of trench 12 width.Then, utilize chemical mechanical milling method (Chemical MechanicalPolishing; CMP), or the anisotropic reactive ion-etching, be etchant with fluoroform (CHF3), a plurality of trench 12 outer first unnecessary insulating barrier 21a are removed in etching, form a plurality of insulating plugs 21.
Then, please refer to Fig. 3, utilize Low Pressure Chemical Vapor Deposition, plasma reinforced chemical vapour deposition method or thermal oxidation method (Thermal Oxidation), form one second insulating barrier 31, its thickness arrives between about 1000 dusts about 500 dusts.Then, the coating one photoresist layer 32 of limiting pattern on second insulating barrier 31.With photoresist layer 32 is mask, utilize the anisotropic reactive ion-etching, fluoroform is an etchant, forms an opening 33 on second insulating barrier 31, the semiconductor-based end 10 of exposed portions serve, and the corner (Corner) of exposing the insulating plug 21 in a plurality of insulating plugs 21.Continue etching insulating plug 21 again, form a groove 34 in trench 12, the degree of depth of groove 34 is about 2500 dusts between about 3500 dusts.Remove photoresist layer 32 then.
Then, please refer to Fig. 4, on above-mentioned each layer, deposit first a thin polysilicon layer 41, and mix arsenic (Arsine) or hydrogen phosphide impurity such as (Phosphine) at this first polysilicon layer 41.Its method is between about 550 ℃ to about 650 ℃ of temperature, is reacting gas with silicomethane (Silane), and simultaneously arsenic doped, phosphonium ion utilize Low Pressure Chemical Vapor Deposition and form.The thickness of first polysilicon layer 41 of this doping arrives between about 350 dusts about 250 dusts.Then, between about 600 ℃ to about 800 ℃ of temperature, (Tungsten Hexafluoride) is reacting gas with tungsten hexafluoride, utilizes Low Pressure Chemical Vapor Deposition, deposition one conductive layer 42 on first polysilicon layer 41, and its thickness arrives between about 2500 dusts about 1500 dusts.Material as if conductive layer 42 is a tungsten, then before forming conductive layer 42, can deposit a titanium nitride layer (Titanium Nitride) that approaches earlier as barrier layer (Barrier Layer) (not shown), is damaged in order to prevent first polysilicon layer 41.And the material of conductive layer 42 also can be the silicide (Tungsten Silicide) of tungsten, and its method is to be reacting gas with tungsten hexafluoride and silicomethane, utilizes Low Pressure Chemical Vapor Deposition and forms.
Then, please refer to Fig. 5, on above-mentioned each layer, carry out the step of etch-back (Etch Back), utilize the anisotropic reactive ion-etching, with chlorine is etchant, and etching first polysilicon layer 41 and conductive layer 42 stay the part in groove 34, proceed etching notched step (Recess) about 1000 dusts to the surface at the semiconductor-based end 10 again and form a conductive plug 51 between about 2000 dusts.The thickness of conductive plug 51 arrives between about 2500 dusts about 1500 dusts, and the position of conductive plug 51 is in the corner of insulating plug 21.
Then, please refer to Fig. 6, remove second insulating barrier 31, on the semiconductor-based end 10, between about 300 ℃ to about 700 ℃ of temperature, utilize Low Pressure Chemical Vapor Deposition or plasma reinforced chemical vapour deposition method, deposit one the 3rd insulating barrier 61, its thickness arrives between about 3000 dusts about 2000 dusts.Carrying out dry ecthing (Dry Etching) step at the 3rd insulating barrier 61 then, is etchant with the fluoroform, stays the 3rd insulating barrier 61 that reaches periphery on conductive plug 51, so conductive plug 51 becomes the bit line that buries.
Then, please be earlier with reference to Fig. 7 b, it illustrated for according to a preferred embodiment of the invention, and a kind of memory cell array manufacturing step is along the generalized section of Figure 1B B ' line.At first, on the semiconductor-based end 10, between about 850 ℃ to about 950 ℃ of temperature, utilize thermal oxidation method, the thin gate insulator 71 (Gate Insulator Layer) of growing up, silicon dioxide for example, gate insulator 71 thickness about 50 dusts between about 200 dusts.Then, between about 550 ℃ to about 650 ℃ of temperature, utilize Low Pressure Chemical Vapor Deposition, on gate insulator 71, form a grid 13, polysilicon layer for example, the thickness of grid 13 about 2000 dusts between about 4000 dusts.Then, on grid 13, carry out ion and implant (IonImplantation), inject N type ion, for example arsenic ion or phosphonium ion, between about 100KeV, dosage is about 1 * 10 about 25KeV for its energy
14Atom/square centimeter is to about 1 * 10
16Between atom/square centimeter.Also can mix N type ion, for example arsenic ion or phosphonium ion, and be full of under the environment of silicomethane gases, carry out environment doping step (Situ Doping Procedure).Grid 13 in order to do word line (Word Line), is vertical arrangement (as shown in Figure 1) with the above-mentioned formed bit line that buries 17 usually.Then, carry out ionic-implantation again, implant N type ion on the semiconductor-based end 10 on grid 13 sides, for example arsenic ion or phosphonium ion form a lightly doped source/drain regions 74, and between about 75KeV, dosage is about 1 * 10 about 30KeV for its energy
12Atom/square centimeter is to about 1 * 10
14Between atom/square centimeter.Then, on grid 13, between about 300 ℃ to about 700 ℃ of temperature, utilize Low Pressure Chemical Vapor Deposition or plasma reinforced chemical vapour deposition method, deposit about 1500 dusts of a thickness to the oxide layer 74a between about 3000 dusts.Then, utilizing the anisotropic reactive ion-etching, is etchant with the fluoroform, forms a clearance wall 74 at grid 13 sides.Then, utilize ionic-implantation again, implant N type ion on the semiconductor-based end 10 on grid 13 sides, for example arsenic ion or phosphonium ion form a heavily doped source/drain regions 75, and between about 100KeV, dosage is about 1 * 10 about 50KeV for its energy
14Atom/square centimeter is to about 1 * 10
16Between atom/square centimeter.
Then, please refer to Fig. 7 a, illustrate for according to a preferred embodiment of the invention, a kind of memory cell array manufacturing step is along the generalized section of Figure 1A A ' line.Be formed with lightly doped source/drain regions 73, heavily doped source/drain regions 75 and gate insulator 71 at the semiconductor-based end 10, above-mentioned each layer do not covered by the 3rd insulating barrier 61.Carry out a Rapid Thermal tempering (Rapid ThermalAnneal) step then, temperature is between 950 ℃ to about 1050 ℃, and the time of carrying out is between 10 seconds to about 60 seconds.Can begin diffusion and contact each other so that the impurity of first polysilicon layer 41 of the heavily doped source/drain regions that dyes 75, lightly doped source/drain regions 73 and doping obtains energy.Therefore first polysilicon layer 41 that mixes can be aimed at automatically with the position of heavily doped source/drain regions 75 and lightly doped source/drain regions 73, also the bit line 51 that buries can be aimed at automatically with the position of heavily doped source/drain regions 75 and lightly doped source/drain regions 73.Can omit subsequent optical like this and scribe the alignment procedures of making technology (Photolithography), and needn't worry that the exposure aligning of photoetching is wayward.
Then, please refer to Fig. 8, deposition one the 4th insulating barrier 81 forms one second opening 14 thereon on above-mentioned each layer, exposes the surface of lightly doped source/drain regions 73 and heavily doped source/drain regions 75.The formation of second opening 14 is to utilize the anisotropic reactive ion-etching, is etchant with the fluoroform, and temperature is between 300 ℃ to about 500 ℃.Then, between about 550 ℃ to about 650 ℃ of temperature, utilize Low Pressure Chemical Vapor Deposition, form one second polysilicon layer 83a at second opening, 14 peripheries, its thickness arrives between about 8000 dusts about 5000 dusts.The second polysilicon layer 83a is in order to filling up second opening 14, and carries out the ion implantation step thereon, injects N type ion, for example arsenic ion or phosphonium ion, and between about 75KeV, dosage is about 1 * 10 about 25KeV for its energy
16Atom/square centimeter is to about 5 * 10
16Between atom/square centimeter.Or, for example under the environment of arsenic ion or phosphonium ion, carry out environment doping step being full of silicomethane gases and mixing N type ion.Utilizing photoetching and anisotropic reactive ion-etching then, is etchant with chlorine, to the second polysilicon layer 83a composition, in order to form a storage bottom electrode 83.
Then, please refer to Fig. 9, on storage bottom electrode 83, form a dielectric layer 91, in order to do the usefulness of insulation.Dielectric layer 91 can utilize sputtering method (Sputtering) and form, with the material of high-k (HihgDielectric Constant), for example oxide of tantalum, preferably tantalum pentoxide (Ta
2O
5), about 200 dusts of its thickness are between about 300 dusts.And dielectric layer 91 also can utilize sedimentation form thickness about 40 dusts to a silicon oxide/silicon nitride/silicon oxide layer (the Oxidized/SiliconNitride/Silicon Oxide between about 80 dusts; ONO), its method be heating earlier grow up a thickness about 10 dusts to the silicon oxide layer between about 50 dusts, then form a thickness about 10 dusts to the silicon nitride layer between about 20 dusts, the step of carrying out thermal oxidation then forms one silica layer on silicon nitride layer.Then, deposition one the 3rd polysilicon layer 92a on dielectric layer 91, its method is between about 550 ℃ to about 650 ℃ of temperature, utilizes Low Pressure Chemical Vapor Deposition and forms.The thickness of the 3rd polysilicon layer 92a arrives between about 3000 dusts about 2000 dusts.Then, dopant ion on the 3rd polysilicon layer 92a, its method is to be full of silicomethane gases and to mix under the environment of phosphine gas, carrying out environment doping step.Utilizing photoetching and anisotropic reactive ion-etching then, is etchant with chlorine, to the 3rd polysilicon layer 92a composition, in order to form a top electrode 92.Above-mentioned storage bottom electrode 83, dielectric layer 91 and top electrode 92 constitute a structure of piling up electric capacity 15.
In sum; though disclosed the present invention in conjunction with the preferred embodiments; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can make various changes and retouching, so protection scope of the present invention should be limited by accompanying Claim.
Claims (40)
1. the manufacture method of a memory cell array comprises the following steps: at least
(a) in the semiconductor substrate, form a plurality of trench;
(b) on this semiconductor-based end, form one first insulating barrier, in order to fill up this a plurality of trench;
(c) remove at suprabasil this first insulating barrier of this semiconductor, stay these a plurality of trench that fill up, form a plurality of insulating plugs;
(d) on this semiconductor-based end and these a plurality of insulating plugs, deposit one second insulating barrier;
(e) on this second insulating barrier, form one first opening, this semiconductor-based end of exposed portions serve, and the corner of exposing the insulating plug in these a plurality of insulating plugs;
(f) remove this first insulating barrier under this insulating plug corner, form a groove;
(g) on this second insulating barrier, this semiconductor-based end of part of exposing and this groove, form first polysilicon layer that mixes;
(h) deposition one conductive layer on first polysilicon layer of this doping, and this conductive layer fills up this groove;
(i) remove at first polysilicon layer of this conductive layer, this doping and this semiconductor-based end of part, stay first polysilicon layer of this conductive layer in this groove and this doping, form a conductive plug;
(j) on this conductive plug, carry out an etching notched step, in order to form a bit line;
(k) on this conductive plug, reach periphery and form one the 3rd insulating barrier, in order to bury this bit line;
(l) on this semiconductor-based end, form a gate insulator, and on this gate insulator, form a grid;
(m) form a lightly doped source/drain regions at this grid on this other semiconductor-based end, and this lightly doped source/drain regions is distributed in the zone between the 3rd insulating barrier and this a plurality of trench;
(n) form a clearance wall at this grid side;
(o) form a heavily doped source/drain regions at this clearance wall on this other semiconductor-based end, so this lightly doped source/drain regions, this heavily doped source/drain regions and this grid form a transfering transistor;
(p) carry out a tempering step, make impurity in first polysilicon layer of this heavily doped source/drain regions, this lightly doped source/drain regions and this doping to spread and contact;
(q) deposition one the 4th insulating barrier on above-mentioned each layer;
(r) form one second opening at the 4th insulating barrier, expose the surface of this lightly doped source/drain regions and this heavily doped source/drain regions;
(s) form one second polysilicon layer at this second opening periphery,, form a bottom electrode in order to fill up this second opening;
(t) on this bottom electrode, form a dielectric layer; And
(u) deposition one the 3rd polysilicon layer on this dielectric layer is in order to form a top electrode, so this bottom electrode and this top electrode form a structure of piling up electric capacity.
2. the method for claim 1, wherein the formation method of these a plurality of trench of step (a) is the anisotropic reactive ion-etching, etchant is a chlorine.
3. the method for claim 1, wherein the degree of depth of these a plurality of trench all about 4000 dusts between about 6000 dusts.
4. the method for claim 1, wherein the formation method of this first insulating barrier of step (b) is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.
5. the method for claim 1, wherein this first insulating barrier comprises the oxide of silicon.
6. the method for claim 1, wherein the thickness of this first insulating barrier is about 2/3rds of these a plurality of trench width.
7. the method for claim 1, wherein to form the method for this groove be the anisotropic reactive ion-etching to step (f), etchant is a fluoroform.
8. the method for claim 1, wherein the degree of depth of this groove is about 2500 dusts between about 3500 dusts.
9. the method for claim 1, wherein the formation method of first polysilicon layer of this doping of step (g) is between about 550 ℃ to about 650 ℃ of temperature, with the silicomethane is reacting gas, and simultaneously arsenic doped, phosphonium ion utilize Low Pressure Chemical Vapor Deposition and form.
10. the method for claim 1, wherein the thickness of first polysilicon layer that should mix about 250 dusts between about 350 dusts.
11. the method for claim 1, wherein the formation method of this conductive layer of step (h) is between about 600 ℃ to about 800 ℃ of temperature, is reacting gas with the tungsten hexafluoride, utilizes Low Pressure Chemical Vapor Deposition and forms.
12. method as claimed in claim 11, wherein the material of this conductive layer comprises tungsten.
13. method as claimed in claim 11, wherein the thickness of this conductive layer arrives between about 3500 dusts about 2500 dusts.
14. the method for claim 1, wherein the formation method of this conductive layer of step (h) is between about 600 ℃ to about 800 ℃ of temperature, with tungsten hexafluoride and silicomethane reacting gas, utilizes Low Pressure Chemical Vapor Deposition and forms.
15. method as claimed in claim 14, wherein the material of this conductive layer comprises the silicide of tungsten.
16. method as claimed in claim 14, wherein the thickness of this conductive layer arrives between about 2500 dusts about 1500 dusts.
17. the method for claim 1, wherein this etching notched step of step (j) is to utilize the anisotropic reactive ion-etching, etchant is a chlorine, make the thickness of this conductive plug arrive between about 2500 dusts about 1500 dusts, and this bit line about 2000 Izod right sides under this trench surface that form.
18. the method for claim 1, wherein the formation method of step (k) the 3rd insulating barrier is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.
19. the method for claim 1, wherein the 3rd insulating barrier comprises the oxide of silicon.
20. the method for claim 1, wherein the thickness of the 3rd insulating barrier arrives between about 2500 dusts about 1500 dusts.
21. the method for claim 1, wherein this gate insulator is the oxide of silicon, and between about 200 dusts, its formation method is between about 850 ℃ to about 950 ℃ of temperature to its thickness about 50 dusts, utilizes thermal oxidation method and forms.
22. the method for claim 1, wherein this lightly doped source/drain regions of step (m) is implanted N type ion, and between about 75KeV, dosage is about 1 * 10 about 30KeV for its energy
12Atom/square centimeter is to about 1 * 10
14Between atom/square centimeter.
23. the method for claim 1, wherein this heavily doped source/drain regions of step (o) is implanted N type ion, and between about 100KeV, dosage is about 1 * 10 about 50KeV for its energy
14Atom/square centimeter is to about 1 * 10
16Between atom/square centimeter.
24. the method for claim 1, wherein the tempering step temperature of step (p) is between about 950 ℃ to about 1050 ℃, and the time of carrying out is between 10 seconds to about 60 seconds.
25. the method for claim 1, this dielectric layer of step (t) wherein, its thickness arrives between about 80 dusts about 40 dusts, the formation method be form earlier a thickness about 10 dusts to the silicon oxide layer between about 50 dusts, then form a thickness about the silicon nitride layer of 10 dusts between about 20 dusts, carry out the step of thermal oxidation then, on this silicon nitride layer, form one silica layer.
26. the method for claim 1, wherein this dielectric layer of step (t) is the oxide of tantalum, and about 200 dusts of its thickness utilize sputtering method and form between about 300 dusts.
27. the manufacture method of a memory cell array comprises the following steps: at least
(a) in the semiconductor substrate, form a plurality of trench, and deposit one first insulating barrier in order to fill up this a plurality of trench;
(b) form a groove in the corner on these a plurality of trench trench surface wherein;
(c) deposit a doped polycrystalline silicon layer at this groove;
(d) deposition one conductive layer on this doped polycrystalline silicon layer, and this conductive layer fills up this groove;
(e) this conductive layer of etch-back forms a conductive plug in this groove, carry out etching notched step then on this conductive plug, and this semiconductor-based end of etching is in order to form a bit line;
(f) on this bit line, reach periphery and form one second insulating barrier, in order to bury this bit line;
(g) on this semiconductor-based end, form source, and this source/drain regions is distributed in the zone between these a plurality of trench; And
(h) carry out tempering step, the impurity in the doped polycrystalline silicon layer can spread and contact with source/drain regions, makes this bit line that buries can aim at this source/drain regions automatically.
28. method as claimed in claim 27, wherein the formation method of these a plurality of trench of step (a) is the anisotropic reactive ion-etching, and etchant is a chlorine, and the degree of depth of these a plurality of trench all arrives between about 6000 dusts about 4000 dusts.
29. method as claimed in claim 27, this first insulating barrier of step (a) oxide that is silicon wherein, the formation method is between about 300 ℃ to about 700 ℃ of temperature, utilizes chemical vapour deposition technique and forms.
30. method as claimed in claim 27, wherein the thickness of this first insulating barrier is 2/3rds of these a plurality of trench width.
31. method as claimed in claim 27, wherein the formation method of this groove of step (b) is the anisotropic reactive ion-etching, and etchant is a fluoroform.
32. method as claimed in claim 27, wherein the degree of depth of this groove is about 2500 dusts between about 3500 dusts.
33. method as claimed in claim 27, wherein the formation method of this doped polycrystalline silicon layer of step (c) is between about 550 ℃ to about 650 ℃ of temperature, with the silicomethane is reacting gas, while arsenic doped, phosphonium ion, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this doped polycrystalline silicon layer about 250 dusts between about 350 dusts.
34. method as claimed in claim 27, wherein the material of this conductive layer of step (d) comprises tungsten, its formation method is between about 600 ℃ to about 800 ℃ of temperature, with the tungsten hexafluoride is reacting gas, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this conductive layer about 2500 dusts between about 3500 dusts.
35. method as claimed in claim 27, wherein the material of this conductive layer of step (d) comprises tungsten, its formation method is between about 600 ℃ to about 800 ℃ of temperature, with tungsten hexafluoride and silicomethane reacting gas, utilize Low Pressure Chemical Vapor Deposition and form, and the thickness of this conductive layer about 2500 dusts between about 3500 dusts.
36. method as claimed in claim 27, wherein the thickness of this bit line of step (e) arrives between about 2500 dusts about 1500 dusts.
37. method as claimed in claim 27, wherein this depression step of step (e) is the anisotropic reactive ion-etching, utilizes chlorine to be etchant, makes this bit line about 1000 dusts under this trench surface arrive about 2000 Izod right sides.
38. method as claimed in claim 27, wherein this second insulating barrier of step (f) comprises the oxide of silicon, its formation method is between about 300 ℃ to about 700 ℃ of temperature, utilize chemical vapour deposition technique and form, and the thickness of this second insulating barrier about 2000 dusts between about 3000 dusts.
39. method as claimed in claim 27, wherein this source/drain regions of step (g) utilizes ionic-implantation and forms, and implants energy and arrives between about 100KeV about 50KeV, and dosage is about 1 * 10
14Atom/square centimeter is to about 1 * 10
16N type ion between atom/square centimeter.
40. method as claimed in claim 27, wherein between about 950 ℃ to about 1050 ℃ of the tempering step temperature of step (h), the time of carrying out is between 10 seconds to about 60 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB981057624A CN1143390C (en) | 1998-03-23 | 1998-03-23 | Method of making memory unit array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB981057624A CN1143390C (en) | 1998-03-23 | 1998-03-23 | Method of making memory unit array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1230021A true CN1230021A (en) | 1999-09-29 |
| CN1143390C CN1143390C (en) | 2004-03-24 |
Family
ID=5218829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB981057624A Expired - Lifetime CN1143390C (en) | 1998-03-23 | 1998-03-23 | Method of making memory unit array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1143390C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446236C (en) * | 2002-03-25 | 2008-12-24 | 夏普株式会社 | Transistor array and active-matrix substrate |
| CN102376650A (en) * | 2010-08-10 | 2012-03-14 | 宜扬科技股份有限公司 | Manufacturing method for NOR type flash memory with multi level cell |
| CN107993941A (en) * | 2016-10-27 | 2018-05-04 | 北大方正集团有限公司 | The manufacture method and semiconductor alloy lead of semiconductor alloy lead |
| CN108156827A (en) * | 2015-10-07 | 2018-06-12 | 硅存储技术公司 | The method of in-line memory equipment of the manufacture with silicon-on-insulator substrate |
-
1998
- 1998-03-23 CN CNB981057624A patent/CN1143390C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446236C (en) * | 2002-03-25 | 2008-12-24 | 夏普株式会社 | Transistor array and active-matrix substrate |
| CN102376650A (en) * | 2010-08-10 | 2012-03-14 | 宜扬科技股份有限公司 | Manufacturing method for NOR type flash memory with multi level cell |
| CN108156827A (en) * | 2015-10-07 | 2018-06-12 | 硅存储技术公司 | The method of in-line memory equipment of the manufacture with silicon-on-insulator substrate |
| CN107993941A (en) * | 2016-10-27 | 2018-05-04 | 北大方正集团有限公司 | The manufacture method and semiconductor alloy lead of semiconductor alloy lead |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1143390C (en) | 2004-03-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1292983B1 (en) | Method of producing trench capacitor buried strap | |
| US5670404A (en) | Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer | |
| US4984038A (en) | Semiconductor memory and method of producing the same | |
| US6525371B2 (en) | Self-aligned non-volatile random access memory cell and process to make the same | |
| US6171923B1 (en) | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor | |
| US5395786A (en) | Method of making a DRAM cell with trench capacitor | |
| US6184549B1 (en) | Trench storage dynamic random access memory cell with vertical transfer device | |
| JP3466938B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| US6204140B1 (en) | Dynamic random access memory | |
| US6008084A (en) | Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance | |
| US5716881A (en) | Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip | |
| US6391705B1 (en) | Fabrication method of high-density semiconductor memory cell structure having a trench | |
| US6180453B1 (en) | Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared | |
| US6255158B1 (en) | Process of manufacturing a vertical dynamic random access memory device | |
| JPH11145275A (en) | Shallow trench isolation structure and forming method thereof | |
| US5792690A (en) | Method of fabricating a DRAM cell with an area equal to four times the used minimum feature | |
| KR0151012B1 (en) | Dram cell & its producing method | |
| US5753551A (en) | Memory cell array with a self-aligned, buried bit line | |
| US6555862B1 (en) | Self-aligned buried strap for vertical transistors | |
| US6414347B1 (en) | Vertical MOSFET | |
| US5521112A (en) | Method of making capacitor for stack dram cell | |
| KR100419926B1 (en) | Memory cell with a trench capacitor and a method for production of the same | |
| US6638815B1 (en) | Formation of self-aligned vertical connector | |
| KR960006718B1 (en) | Memory capacitor in semiconductor device and the method for fabricating the same | |
| CN1143390C (en) | Method of making memory unit array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20040324 |
|
| CX01 | Expiry of patent term |