CN1224217A

CN1224217A - Clock synchronous semiconductor memory device capable of preventing outputting of invalid data

Info

Publication number: CN1224217A
Application number: CN 98120794
Authority: CN
Inventors: 泽田诚二
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1998-01-23
Filing date: 1998-09-28
Publication date: 1999-07-28

Abstract

A gate circuit is turned on in synchronization with an internal clock signal at a timing faster than activation of an output buffer circuit (910b), and internal data (DD) is transmitted from the gate circuit to an output buffer circuit externally outputting data. Generation of an internal clock signal is stopped at a timing faster than deactivation of the output buffer circuit, and the gate circuit (910a) is set to the latching state. According such arrangement, output of invalid data is prevented.

Description

Prevent the clock synchronous semiconductor memory device of invalid data output

The present invention relates to semiconductor storage, particularly with the synchronous-type semiconductor storing apparatus of clock signal synchronization action.More particularly, relate to the control circuit of the data output of synchronous-type semiconductor storing apparatus, more particularly, relate to the structure that prevents invalid data output.

Figure 21 is that the data of existing Syncronous semiconductor memory device are read the sequential chart of action.Below, the action of Syncronous semiconductor memory device is described with reference to Figure 21.

This Syncronous semiconductor memory device synchronously is taken into outer increase control signal and output data with the clock signal extCLK that adds.The clock signal extCLK that adds is such as system clock etc.

At the rising edge of the external timing signal extCLK of clock period #1, row addressing gating signal/RAS is set to low level, row addressing gating signal/CAS and write permission signal/WE and be set to high level.The combination of these control signals is called as effective instruction, at this moment, with the address signal that adds synchronously, goes selection operation in Syncronous semiconductor memory device.When the RAS-CAS of standard DRAM finishes time delay, can carry out the column selection operation in inside.

At the rising edge of the external timing signal extCLK of clock period #3, row addressing gating signal/RAS and write permission signal/WE and be set to high level, and row addressing gating signal/CAS is set to low level.Carry out column selection operation with the address signal that adds synchronously the combination this moment that is called these control signal states of sense order, and from select memory cell sense data.

When sense data, do not carry out column selection in inside, for outwards reading the data of the selection storage piece that this selection lists, the data delivery in inside needs the time.In clock signal #4 output primary data, at the rising edge of the clock signal extCLK of clock period #5, output data Dout determines.Then,, as the beginning address, generate address signal, carry out column selection, continuously sense data with predetermined sequence with initial address signal in inside.Therefore, at each rising edge of the external timing signal extCLK of clock period #6, #7 and #8, data are all determined, and are taken a sample by external unit.

Be called a CAS stand-by period from applying sense order to the clock periodicity that valid data occur.The data number of reading continuously when applying a sense order (each data output end) is called burst length, Figure 21 represented with the CAS stand-by period be 2, burst length be 4 o'clock be the action of reading of example.

At the rising edge of the external timing signal extCLK of clock period #9, row addressing gating signal/RAS and read to allow signal/WE to be made as low level, row addressing gating signal/CAS is made as high level.The combination of the state of these control signals is called a precharge instruction, the precharge action of indication ranks.That is, the selection row in inside is driven to nonselection mode, and storage piece ranks are returned to predetermined pre-charge state, and this Syncronous semiconductor memory device enters wait (standby) state.

As shown in figure 21, by taking out external signal synchronously with external timing signal extCLK, external timing signal extCLK is determined each control signal timing preface really, deflection (skew) for control signal need not be considered the time tolerance limit, make internal actions carry out thus, can carry out zero access with sequential fast.In addition, because the data Dout and the external timing signal extCLK of output are synchronous, so, can carry out data at a high speed and transmit.

Figure 22 is the simple synoptic diagram of structure of reading relevant portion in the existing Syncronous semiconductor memory device with data.Among Figure 22, existing Syncronous semiconductor memory device comprises: the storage block array 900 with a plurality of storage pieces that are arranged in rows and columns; Be taken into the addressing input buffer 902 that adds address signal and generate inner row and column address signal synchronously with clock signal; According to the internal rows address signal that receives from addressing input buffer 902 row that the appointed addressed row (word line) the storage block array 900 is driven into selection mode is selected circuit 904; Column select circuit 906 according to the row of selecting the designated addressing the storage block array 900 from the inner array address signal of addressing input buffer 902 (bit line to); When reading, data are used to read the sensing circuit 908 of the memory cell data of selecting by column select circuit 906 that lists; When activating with internal clock signal CLKO synchronously receive from sensing circuit 908, sense data RD goes forward side by side, and row cache is handled, the output circuit 910 of generation external data Dout; Externally add the clock regtster 912 that clock signal extCLK carries out caching process, produces internal signal intCLK and CLKO; Judge the control signal/RAS that add synchronous with internal clock signal intCLK ,/CAS and/logic state of WE, and produce the instruction decoder 914 of the signal of expression judged result; Be used to carry out by control circuit 916 from the action of the output signal appointment of instruction decoder 914.

Control circuit 916 comprises: provide from demoder 914 select the relevant pattern instruction of action (activation instruction and precharge instruction) with row the time activate, and control and row select the line control circuit 916a of the action of relevant circuit; The instruction relevant with column selection from demoder 914 (sense order and designation data write write instruction) just activates, and the control circuit 916b of the action of the control circuit relevant with column selection if provide; And according to the output control circuit 916c that allows signal OEMF to activate output circuit 910 from reading of arrange control circuit 916b.When OEM activated, output circuit 910 was activated, output and internal clock signal CLKO data in synchronization Dout when the output from output control circuit 916c allows signal (being that output state allows signal).

Line control circuit 916 control addressing input buffers 902, row are selected circuit 904, not shown bit-line pre-charge circuit and the action of sensor amplifier circuit, but only show the action of control row selection circuit 904 in 22.Arrange control circuit 916b activates and reads permission signal OEMF when applying access instruction (sense order and write instruction).This is read when allowing signal OEMF to activate, and carries out reading of column selection and internal data.Column select circuit 906 comprises column decoder and the I/O door that will select row to be connected with internal data line.Sensing circuit 908 comprises the prime amplifier circuit of the data amplification that makes on the internal data line.Can contain the transmission gate that transmits with internal clock signal intCLK output signal synchronous, pre-amplifying circuit according to above-mentioned inner this sensing circuit that constitutes.

Output circuit 910 comprises: be taken into by sensing circuit 908 is that provide and the gate circuit of the sense data RD that internal clock signal CLKO is synchronous; With the output state that when output permission signal OEM activates, the output signal of this gate circuit is carried out caching process and output.Arrange control circuit 916b determines the sequential that the column address of addressing input buffer 902 is taken into, but in Figure 22, for drawing is simplified, not shown.

Figure 23 shows an example of the structure of the clock regtster 912 shown in Figure 22.

Clock regtster 912 among Figure 23 comprises: external timing signal extCLK is carried out caching process and produces the buffer circuit 912a of internal clock signal intCLK; Read the buffer circuit 912b that uses internal clock signal CLKO with external timing signal extCLK being carried out caching process and producing.Internal clock signal intCLK and the internal clock signal CLKO that reads usefulness are synchronous mutually.These internal clock signals intCLK and CLKO are (when not the using clock to allow signal) that always produces.

Figure 24 shows an example of OEMF signal generating circuit structure contained among the arrange control circuit 916b shown in Figure 22.OEMF signal generating circuit among Figure 24 comprises: read the burst length counter 920a that indicator signal/READ postpones a burst length with internal clock signal intCLK synchronization action and data; Receive the NAND circuit 920b that data are read indicator signal/READ at one of its output terminal; NAND circuit 920c with the output signal of the reset signal/RST of received pulse string length counter 920a output and NAND circuit 920b.Another input end of NAND circuit 920b receives the output signal of NAND circuit 920c, and permission signal OEMF is read in output.When applying sense order, read indicator signal/READ and place low level in the scheduled period.Burst length counter 920a and internal clocking intCLK synchronization action make during burst length and read indicator signal/READ displacement, and reset signal/RST is activated.Action below with reference to sequential chart explanation shown in Figure 25 OEMF signal generating circuit shown in Figure 24.

If externally the rising edge of clock signal extCLK applies sense order, instruction decoder 914 then shown in Figure 22 synchronously detects applying of sense order with internal clock signal intCLK, in the scheduled period readout command signal/READ is driven into low level state of activation.Respond the activation of this readout command signal/READ, allow signal OEMF to become the state of activation of high level from reading of NAND circuit 920b.Reset signal/RST is in high level, and NAND circuit 920c receives high level signal at two input ends, and output signal is driven into low level.Thus, even readout command signal/READ rises to high level, read the state of activation that permission signal OEMF also can keep high level.Read when allowing signal OEMF to be in state of activation, under the control of arrange control circuit 916b, carry out the selection of column of memory cells and the data of selected storage unit and read.The burst length counter 920a that calculates the burst length time (Figure 25 indicating impulse width is 4 o'clock action) from provide read instruction begin through 4 clock period after, synchronously drive reset signal/RST with internal clock signal intCLK, make it in a clock period, be driven into low level state of activation.When reset signal/RST reduced to low level, the output signal of NAND circuit 920c was a high level, and the NAND circuit 920b that its two input signal is a high level will read and allow signal OEMF to be urged to low level.Thus, the output signal of NAND circuit 920c is decided to be high level, even reset signal/RST is returned to noble potential, reads permission signal 0EMF and also can keep unactivated state.

Allow signal OEMF by during burst length, activating to read, read the long data of burst length that are.

Figure 26 is an example of the structure of expression output control circuit 916c shown in Figure 22 and output circuit 910.Output control circuit 916c shown in Figure 26 comprises the clock shift unit 916ca that allows signal OEMF delayed internal clock signal intCLK (CAS stand-by period-1) clock period (CAS stand-by period-1) that reads with arrange control circuit 916b output shown in Figure 22.The synchronous shift motion of (CAS stand-by period-1) clock shift unit 916ca discord internal clock signal intCLK will be read and allow signal OEMF delay (CAS stand-by period-1) clock period, produce output and allow signal (output buffers permission signal) OEM.

Output circuit 910 comprises: the gate circuit 910a that is taken into and latchs inner sense data with internal clock signal CLKO synchronization action, from sensing circuit 908 shown in Figure 22; Be activated when allowing signal OEM to activate in output, and to the output buffers circuit 910b of the latch data DD of the outside out-gate circuit 910a of device.

Gate circuit 910a comprises: the ternary anti-phase buffer 910aa that activates, makes inner sense data RD counter-rotating at internal clock signal CLKO during for high level; Make the output signal of ternary anti-phase buffer 910aa anti-phase and internal data DD is added to the negative circuit 910ab of output buffers circuit 910b; Anti-phase and be sent to the negative circuit 910ac of the importation of negative circuit 910ab with the output data DD that makes negative circuit 910ab.Negative circuit 910ab and 910ac constitute an anti-phase latch.

Output buffers circuit 910b comprises: make the anti-phase negative circuit 910ba of data DD; Receive the AND circuit 910bb that output allows signal OEM and data DD; Receive the output signal of negative circuit 910ba and the AND circuit 910bc that output allows signal OEM; Conducting and produce the n channel MOS transistor 910bd of the output data Dout of power source voltage Vcc level when the output signal of AND circuit 910bb is high level; Conducting and produce the N-channel MOS transistor 910be of size when being high level for the output data Don ' t of ground voltage Vss level with output signal as AND circuit 910bc.AND circuit 910bb and 910bc are made of NAND circuit and negative circuit.Below with reference to sequential chart shown in Figure 27 the control circuit 916c shown in Figure 26 and the action of output circuit 910 are described.

Internal clock signal intCLK and CLKO and external signal extCLK produce synchronously.Therefore, the ternary anti-phase buffer 910aa of gate circuit 910a activates/non-activation action always repeatedly, is taken into/latchs inner sense data RD repeatedly.

When the clock period, #0 applied sense order, in clock period #0, read permission signal OEMF and be in the high level state of activation.The following describes the CAS stand-by period and be 2, burst length is 4 o'clock action.Along with this reads the activation that allows signal OEMF, under the control of arrange control circuit 916b, carry out the selection of storage unit, read the data of selected storage unit.

At clock period #1, in response to the rising of internal clock signal CLKO, inner sense data RD is taken into gate circuit 910a, and in response to its decline, inner sense data RD is latched.Because the CAS stand-by period is 2, allow signal OEM synchronously to become state of activation at clock period #1 and internal clock signal intCLK from the output of (CAS stand-by period-1) clock shift unit 916ca.When output allowed signal OEM to be in the state of activation of high level, output state circuit 910b was activated and is in the output low impedance state, and the data that apply from gate circuit 910a are carried out caching process and output.

Because burst length is 4, so, to read permission signal OEMF and in clock period #4, be in unactivated state, the action of reading of sensing circuit 908 (with reference to Figure 22) is stopped.On the other hand, internal clock signal CLKO always produces, and that carries out inner sense data RD repeatedly is taken into and latchs action.Therefore, in clock period #4, the rising of gate circuit 910a and internal clock signal CLKO synchronously is taken into the data of last burst length, synchronously latchs it with the decline of internal clock signal CLKO.After the final data output of this burst length, in clock period #5, output allows signal OEM to be in low level unactivated state, and output state circuit 910b is in output high impedance state.Thus, synchronously order output of the data of burst length 4 and external timing signal extCLK.

Be the invalid data district with the zone shown in the oblique line in the sequential chart shown in Figure 27.

Figure 28 is another structural drawing of existing synchronous semiconductor memory device.The difference of synchronous semiconductor memory device shown in Figure 28 and semiconductor storage shown in Figure 22 is that device shown in Figure 28 has the function of shielding from the data output of output circuit 910, that is to say, synchronous semiconductor memory device shown in Figure 28 comprises internal shield signal generating circuit 930, in response to adding data output masking instruction DQM, synchronously produce internal shield indicator signal DQMO and impose on output control circuit 916c with internal clock signal intCLK.When the internal shield command signal DQMO from internal shield command signal generation circuit 930 is in state of activation and video data output conductively-closed, output control circuit 916c drives output and allows signal OEM to unactivated state, and output circuit 910 is set is high impedance status.The structure of other parts is with shown in Figure 22 identical, and counterpart adopts identical label.

Figure 29 is the structure diagram of internal shield signal generating circuit 930 shown in Figure 28.Internal shield signal generating circuit 930 shown in Figure 29 comprises: reception and caching process add the input buffer 930a of data mask instruction DQM; When the signal from input buffer 930a is in state of activation, produce the ono shot pulse generation circuit 930b of single trigger pulse signal in response to the rising of internal clock signal intCLK; With synchronously latch latch cicuit 930c with internal clock signal intCLK from the single trigger pulse signal DQMOF of ono shot pulse generation circuit 930b.

In the structure of internal shield command signal generation circuit 930 shown in Figure 29, when adding masking instruction DQM when being in state of activation, the data output conductively-closed of next clock period.

Figure 30 is an example of the structure of ono shot pulse generation circuit 930b shown in Figure 29.Ono shot pulse generation circuit 930b shown in Figure 30 comprises: the AND circuit 930ba that receives the output signal DQMi of internal clock signal intCLK and input buffer; The inverse delayed circuit 930bb of and delay scheduled time anti-phase the output signal of AND circuit 930ba; With the output signal and the output signal of inverse delayed circuit 930bb and the AND circuit 930bc of output signal DQMOF that receive AND circuit 930ba.The output signal DQMi of input buffer 930a shown in Figure 29 is a high level when being activated.Therefore, if internal clock signal intCLK rises to high level, when applying masking instruction, the output signal of AND circuit 930ba rises to high level.Signal DMOF becomes the state of activation of high level in the scheduled period.

The structure of ono shot pulse generation circuit shown in Figure 30 can be replaced with the set/reset two-position toggle switch, and when the output signal of AND circuit 930ba is provided with during for high level, the schedule time finishes laggard horizontal reset.This set/reset two-position toggle switch output signal DQMOF.

Shown in Figure 31 is an example of the structure of latch cicuit 930c shown in Figure 29.Latch cicuit 930c among Figure 31 comprises: make the anti-phase phase inverter 930ca of signal DQMOF; Accept the NAND circuit 930cb of internal clock signal intCLK and signal DQMOF; Accept the output signal of phase inverter 930ca and the NAND circuit 930cc of internal clock signal intCLK; NAND circuit 930cd in the output signal of the NAND of one of its input end circuit 930cb; NAND circuit 930ce with the output signal of accepting NAND circuit 930cc and 930cd.From NAND circuit 930cd output internal shield command signal DQMO.

In latch cicuit 930c shown in Figure 31, when internal clock signal intCLK was high level, NAND circuit 930cb and 930cc moved as phase inverter, and signal DQMOF is passed through.NAND circuit 930cd and 930ce constitute latch cicuit, latch the signal that applies from NAND circuit 930cd and 930cc.When signal DQMOF activates, synchronously be taken into this latch cicuit with internal clock signal intCLK, and during this clock period, kept latch mode.The action of the internal shield command signal generation circuit 930 shown in Figure 29 to 31 then, is described with reference to the oscillogram of Figure 32.

At clock period #0, add shielding indication DQM and be driven to high level, and remain high level at the rising edge that adds clock signal extCLK of clock period #1.Internal clock signal intCLK and external timing signal extCLK synchronously produce, and in response to the rising from the internal clock signal intCLK of ono shot pulse generation circuit 930b shown in Figure 30, signal DQMOF becomes high level in the scheduled period.When internal clock signal intCLK was high level, latch cicuit 930c was taken into institute's plus signal.Therefore, the signal DQMOF of high level is taken into latch cicuit 930c, and internal shield command signal DQMO rises to high level.When internal clock signal intCLK was high level, signal DQMOF kept high level.When internal clock signal intCLK reduced to low level, the output signal of NAND circuit 930b and 930cc was a high level, and latch cicuit 930c becomes latch mode.

At clock period #2, internal clock signal intCLK rises to high level once more.If between this rising stage, adding masking instruction DQM is low level, signal DQMOF from ono shot pulse generation circuit 930b also is in low level, and feasible internal shield indicator signal DQMO from latch cicuit 930c synchronously is driven to low level with internal clock signal inCLK.DQMO is consistent with the internal shield command signal, and output allows signal OEM also not to be activated.Thereby, when at the rising edge of clock period #1 when the outside applies masking instruction, in the data conductively-closed of clock period #2 output.

Figure 33 is shown schematically in the structure of output control circuit 916c shown in Figure 28.Among Figure 33, output control circuit 916c comprises: allow signal OEMF to postpone the clock shift unit 940a of (OAS stand-by period-2) clock period reading from the inside of arrange control circuit 916 (referring to Figure 28); Make the anti-phase phase inverter 940b of internal shield indicator signal DQMO; Receive the AND circuit 940c of the output signal of (CAS stand-by period-2) clock shift unit 940a and phase inverter 940b; The single clock shift unit 940d of the clock period of the output signal delayed internal clock signal intCLK of AND circuit 940c.Allow signal OEM from single clock shift unit 940d output.

(CAS stand-by period-2) clock shift unit 940a and single clock shift unit 940d are the circuit that synchronously carries out shifting function with internal clock signal intCLK, and its basic structure is identical with latch cicuit shown in Figure 31.

The structure of output circuit identical with shown in Figure 26 of front.When the output from single clock shift unit 940d allowed signal OEM to be in state of activation, output circuit and internal clock signal intCLK be output data synchronously.

Figure 34 is that the data of explanation type synchronous semiconductor memory device shown in Figure 28 are read the sequential chart of sequential.Figure 34 show the CAS stand-by period be 2, pulse width is the operation that 4 o'clock data are read.The CAS stand-by period is 2 o'clock, and (CAS stand-by period-2) clock shift unit 940a shown in Figure 33 does not postpone, and makes to read to allow the output signal of letter OEMF and (CAS stand-by period-2) clock shift unit 940a to produce at synchronization.Below, read action with reference to Figure 28 to the data that Figure 34 describes synchronous semiconductor memory device shown in Figure 28.

#0 applies sense order in the clock period.According to this sense order, read permission signal OEMF is driven to high level during growing from the train of impulses of clock period #0 state of activation.At this moment, be driven to the state of activation of high level similarly from the signal OEMFS of (CAS stand-by period-2) clock shift unit 940a.Allow signal OEMF according to reading, carry out the selection of column of memory cells and reading of internal data in inside.

At the rising edge of the clock signal extCLK of clock period #1, add shielding indicator signal DQM and be made as high level, the indication of shadow data output is provided.Respond mutually with this data output masking instruction, internal shield command signal DQMO rises to high level in the clock period of clock period #1, and the output signal of phase inverter 940b shown in Figure 33 also reaches high level.Output permission signal OEM self-clock cycle #1 rises and becomes state of activation.Even internal shield command signal DQMO is activated, this signal also is added on the single clock shift unit 940d shown in Figure 33, so output allows signal OEM to keep state of activation at clock period #1.Thus, according to the sense data RD that sensing circuit is read in inside, inner sense data DD produces and outwards output at output circuit.

At clock period #2, allow signal OEM to cover from the output of single clock shift unit 940d shown in Figure 33 and keep away command signal DQMO, in a clock period, reach low level unactivated state according to inside, make output circuit reach output high impedance state.Although inner sense data RD transmits in output circuit, not outwards output, data output is masked.Data output masking instruction DQM only is activated at the rising edge that clock period #1 adds clock signal extCLK at home and abroad.Therefore, at clock period #2, #3, #4, internal shield command signal DQMO becomes unactivated state again, make at clock period #3 and #4, output allows signal to reach the state of activation of high level again, in output circuit,, generate inner sense data DD and outwards output according to inner sense data RD.

As shown in figure 34, data output masking instruction DQM activates at clock period #1, makes the data of second clock period export conductively-closed.Thus, ppu can only be taken into data necessary.

In the structure of output control circuit shown in Figure 26 and output circuit, when output allows signal OEM when low level becomes high level, if the data DD from gate circuit is uncertain, the time that the is provided with ts that is internal data DD allows the not sufficiently long words of signal OEM with respect to output, shown in the Dout2 of Figure 27, exported invalid data.If it is sufficiently long that the time that the is provided with ts of internal data DD allows the rising edge of signal OEM with respect to output, internal data DD has been to determine state when output allows signal OEM to activate, shown in the output data Dout1 of Figure 27, in the data of beginning, can not export invalid data.

When output allows signal OEM when high level becomes low level unactivated state, internal data DD must remain unchanged.Therefore, if the retention time tH of internal data DD as shown in figure 27, outputs to invalid data among the output data Dout1 with respect to the non-activation of exporting permission signal OEM in short-term.If retention time tH long enough, shown in the output data Dout2 among Figure 27, do not export ineffective time.

Internal data DD and internal clock signal CLKO synchronously are taken into output circuit, output allows signal OEM also to change synchronously with the intCLK of internal clock signal, these internal clock signals CLKO and intCLK are produced by external timing signal extCLK, and synchronized with each other.Therefore, these outputs allow signal OEM to change in identical clock basically with internal data DD, make time tS to be set and retention time tH is difficult to prolong fully.Therefore, producing internal data DD and output allows the sequential of signal OEM to be offset on the whole each other, consequently: output allow signal OEM only to move forward with respect to internal data DD or after move, therefore, time tS minimizing or retention time tH are set all to be reduced, obtain as shown in figure 27 output data Dout1 or the such output data of Dout2, be difficult to remove invalid data.

If this invalid data satisfies be provided with time corresponding with external timing signal extCLK and the specification value of retention time and access time (promptly reading the time of illegal command from being applied to of sense order), because invalid data does not have sampled during data processing, valid data are correctly taken a sample, and just what problem can not occur.Yet, if invalid data has been exported, changing owing in output data Dout is between short-term, power supply noise appears in output circuit, cause the circuit maloperation.Particularly,, handling and action power change in voltage during sampled data, causing maloperation (the circuit maloperation that causes as the deviation between the input and output clock of the misinterpretation of high/low level, data) if power supply noise appears in the system power supply.Therefore, can not accurately carry out data processing, also can not be configured to the system of correct operation.If this invalid data, just must when determining the access time, consider the tolerance limit of invalid data to cause the access time not reduce thus.

When using output control circuit shown in Figure 33 to carry out data output, with in Figure 27, discussed the same because to the setting and retention times of beginning and last data, the problem of data mask will appear in output permission signal OEM.That is to say that as shown in figure 31, internal data shielded signal DQMO and internal clock signal intCLK synchronously change.Therefore, because output allows signal OEM also synchronously to change with internal clock signal intCLK, when applying the data mask indication, allow the non-activation of signal and the setting and the retention time of activation just to become problem corresponding to output.That is, as shown in figure 34, if allow the deactivation of signal OEM for the output of clock period #2, the retention time tH of internal data DD (0) is short, just occurs invalid data (output data Dout1) when data output shielding.If when output allowed signal OEM to activate in clock period #3, the time that the is provided with ts of the 3rd data (2) was short, can find out from the output data Dout2 of Figure 34, also can similarly export invalid data.Therefore, when data output conductively-closed, the output invalid data, power supply noises etc. cause the circuit maloperation.

The object of the present invention is to provide the synchronous semiconductor memory device that comprises the output circuit that can prevent to export invalid data reliably.

Another purpose of the present invention provides a kind of output control circuit, and it can guarantee reliably that internal data allows the time that is provided with and the retention time of signal with respect to output.

In brief, semiconductor storage according to the present invention has the structure that can only import valid data into the output buffers circuit.That is, inner sense data is imported into the only conducting during necessity of gate circuit of output buffers circuit.

More specifically, according to semiconductor storage of the present invention, comprising: a plurality of storage unit; The gate circuit that the data of selecteed storage unit in a plurality of storage unit are passed through; Data are exported the output circuit of when allowing the data of coming from gate circuit outwards being exported; With synchronously make the output control circuit of gate circuit conducting with clock signal.This output control circuit comprises in response to data does not make gate circuit be in the unit of not on-state with not allowing to export, do not rely on clock signal.

(when not allowing the data output from output circuit) is not cut off to the gate circuit of output buffers circuit transmission sense data with relying on clock signal when data output does not allow, and transmits to output circuit to prevent data.Thus, have only the data that outwards to export to be transferred to output circuit, like this, just can prevent that invalid data from outputing to the outside.

In the detailed description of in conjunction with the accompanying drawings the present invention being done below, above and other objects of the present invention, feature and advantage are more apparent.

Fig. 1 is the one-piece construction synoptic diagram of 1 semiconductor storage according to an embodiment of the present invention.

Fig. 2 A is an example of clock input buffer structure shown in Figure 1, and Fig. 2 B is the signal waveforms of the action of circuit shown in the presentation graphs 2A.

Fig. 3 A is the figure of another structure example of clock input buffer shown in Figure 1, and Fig. 3 B is the oscillogram of its action.

Fig. 4 A is the figure of the another structure example of clock input buffer shown in Figure 1, and Fig. 4 B is the oscillogram of its action.

Fig. 5 is the structural representation of the major part of 1 semiconductor storage according to an embodiment of the present invention.

Fig. 6 is the structural representation of (CAS stand-by period-2) shown in Figure 5 clock shift unit.

Fig. 7 is the signal waveforms of the action of circuit shown in Figure 6.

Fig. 8 A is the figure of the structure example of the single clock shift unit among Fig. 5, Fig. 6, and Fig. 8 B is its sequential chart.

Fig. 9 is the sequential chart of the operation of circuit shown in Figure 5.

Figure 10 is the structural representation of the major part of 2 semiconductor storage according to an embodiment of the present invention.

Figure 11 is the sequential chart of the action of circuit shown in Figure 10.

Figure 12 is the structural representation of the major part of 3 semiconductor storage according to an embodiment of the present invention.

Figure 13 is the sequential chart of the action of circuit shown in Figure 12.

Figure 14 is the structural representation of the major part of 4 semiconductor storage according to an embodiment of the present invention.

Figure 15 is the sequential chart of the operation of circuit shown in Figure 14.

Figure 16 is the structural representation of the major part of 5 semiconductor storage according to an embodiment of the present invention.

Figure 17 is the sequential chart of the action of circuit shown in Figure 16.

Figure 18 is the structural representation of the major part of 6 semiconductor storage according to an embodiment of the present invention.

Figure 19 is the sequential chart of the action of circuit shown in Figure 180.

Figure 20 is the electrical block diagram that the realization shown in the movement oscillogram shown in Figure 19 is latched.

Figure 21 is the sequential chart of data read operation of the synchronous semiconductor memory device of prior art.

Figure 22 is the integrally-built synoptic diagram of the synchronous semiconductor memory device of prior art.

Figure 23 is the structural representation of clock regtster shown in Figure 22.

Figure 24 is the structural representation of the part of generation signal OEMF shown in Figure 22.

Figure 25 is the sequential chart of the action of expression circuit shown in Figure 24.

Figure 26 is the structural representation of output control circuit shown in Figure 22 and output circuit.

Figure 27 is the sequential chart of the action of circuit shown in Figure 26.

Figure 28 is another structural representation of the semiconductor storage of prior art.

Figure 29 is the structural representation that internal shield indicator signal shown in Figure 28 produces circuit.

Figure 30 is the figure that ono shot pulse shown in Figure 29 produces the structure example of circuit.

Figure 31 is the structural representation of latch cicuit shown in Figure 29.

Figure 32 is the sequential chart that Figure 29 arrives circuit operation shown in Figure 31.

Figure 33 is the structural representation of output control circuit shown in Figure 28.

Figure 34 is the sequential chart that the data of semiconductor storage shown in Figure 28 are read action.

(embodiment 1)

Fig. 1 is the structural representation that the data of 1 synchronous semiconductor memory device are according to an embodiment of the present invention read part.Same as the prior art, synchronous semiconductor memory device shown in Figure 1 comprises: memory cell array 900, be used for select storage unit array 900 by the column select circuit 906 of the row of addressing; The sensing circuit 908 of sense data from the storage unit that column select circuit 906 is selected; With the output circuit 910 that the inside sense data RD from sensing circuit 908 is outwards exported with the form of output data Dout.Identical with structure shown in Figure 26, output circuit 910 comprises: in response to the clock signal conducting, sense data RD produces the gate circuit 910a of internal data DD internally; Internal data DD caching process, produce the output state 910b of output data Dout.

This synchronous-type semiconductor storage device further comprises: accept external timing signal extCLK, and the clock input buffer 2 of the synchronous internal clock signal intCLK of generation and external timing signal extCLK; Receive outer increase control signal/RAS ,/CAS and/WE, and the logic state of judging these control signals is with the instruction decoder 914 of identification extra order; Read the arrange control circuit 916 of indicator signal/READ control column selection operation from the inside of instruction decoder 914 with basis.Arrange control circuit 916b comprises: produce the OEMF signal generating circuit 920 of signal OEMF, the OEMF signal is activated during a pulse width according to the inside readout command signal/READ from instruction decoder 914; And selection/read-out control circuit 921, it activates when signal OEMF activates, with the action of control column select circuit 906 and sensing circuit 908.The structure of OEMF signal generating circuit 920 is with shown in Figure 24 identical.

This synchronous-type semiconductor storage device also comprises: data output control circuit 1, it receives from the signal OEMF of OEMF signal generating circuit 920 and adds data output shielding indicates DQM, and produces internal clock signal intCLKO and the output permission signal OEM that is used for data output.Data output control circuit 1 applies output to output circuit 910 contained output state 910b and allows signal (output state permission signal) OEM, applies the internal clock signal intCLK that is used to export to gate circuit 910a.When data output conductively-closed and output allow signal OEM when unactivated state changes, data output control circuit 1 makes gate circuit 910a become nonconducting state, the inside sense data RD from sensing circuit 908 is transmitted to output state 910b forbidding.When output allowed signal OEM to activate, in the moment before output buffers circuit 910b activates, gate circuit 910a was driven to conducting state.Thus, as described later, prevented the outside output of the invalid data that the unnecessary data transmission causes.The structure of different piece will be described below.

(clock input buffer)

Fig. 2 A is the figure of an example of the structure of clock input buffer 2 shown in Figure 1.In Fig. 2 A, clock input buffer 2 comprises: receive the NAND circuit 2a that adds clock signal extCLK and clock permission signal ENABLE; Anti-phase and generate the negative circuit 2b of internal clock signal intCLK the output signal of NAND circuit 2a.Clock allows signal ENABLE to add clock to allow signal, also can be the inner signal that produces when specifying specific pattern (pattern for example has a power failure).

In the structure of the clock input buffer 2 shown in Fig. 2 A, when clock allows signal ENABLE to be low level unactivated state, shown in the movement oscillogram of Fig. 2 B, the output signal of NAND circuit 2a is fixed on high level, and internal clock signal intCLK is fixed on low level.Therefore, when clock allowed the non-activation of signal ENABLE, internal circuit did not begin new action, still keeps laststate.So internal circuit is failure to actuate, do not carry out the charge and discharge of signal wire, current drain is descended, when synchronous semiconductor memory device is in such as power down or silent (sleep) pattern, when keeping holding state for a long time, clock allows signal ENABLE to keep non-activation to reduce current drain.When clock allowed signal ENABLE to rise to high level, NAND circuit 2a moved as negative circuit, produced internal clock signal intCLK according to external timing signal extCLK.

(clock input buffer 2)

Fig. 3 A is the another kind of structure of clock input buffer shown in Figure 1.In Fig. 3 A, clock input buffer 2 comprises: external timing signal extCLK is postponed a setting-up time and anti-phase inverse delayed circuit 2c; Receive the NAND circuit 2d of the output signal of external timing signal extCLK and inverse delayed circuit 2c; With phase inverter 2e anti-phase the output signal of NAND circuit 2d and generation internal clock signal intCLK.The time delay of inverse delayed circuit 2c, to be in time of high level short than adding clock signal extCLK.

In the clock input buffer 2 shown in Fig. 3 A, shown in the oscillogram of Fig. 3 B, when external timing signal extCLK rises to high level, the output signal of inverse delayed circuit 2c still is in high level, the output signal of NAND circuit 2d becomes low level, makes inverter circuit 2e be driven into high level to internal clock signal intCLK.When finished the time delay of inverse delayed circuit 2c, the output signal of inverse delayed circuit 2c was reduced to low level, made the output signal of NAND circuit 2d become high level, and internal clock signal intCLK becomes low level.In the structure of the clock input buffer 2 shown in Fig. 3 A, internal clock signal intCLK is a signal synchronous with external timing signal extCLK and that have certain pulse width.Therefore, even the pulse width of external timing signal extCLK is owing to noise effect changes, the intCLK of internal clock signal also has constant pulse width.Can accurately move with the circuit of internal clock signal intCLK synchronization action, and not be subjected to the influence of noise that external timing signal extCLK is impacted.

(clock input buffer 3)

It shown in Fig. 4 A the another formation of clock input buffer.In Fig. 4 A, clock input buffer 2 comprises: external timing signal extCLK is postponed a time of setting and an anti-phase inverse delayed circuit 2f by what odd number and phase inverter constituted; Receive clock allows the NAND circuit 2g of the output signal of signal ENABLE, external timing signal extCLK and inverse delayed circuit 2f; With inverter circuit 2h anti-phase the output signal of NAND circuit 2g and generation internal clock signal intCLK.Time when be in high level than external timing signal extCLK the time delay of inverse delayed circuit 2f is short.

In the structure of the clock input buffer shown in Fig. 4 A, when clock allowed signal ENABLE to be in low level, shown in the movement oscillogram of Fig. 4 B, the output signal of NAND circuit 2g was fixed on high level, and internal clock signal intCLK is fixed on low level.Therefore, in this state, internal circuit stops action.

When clock allowed signal ENABLE to rise to high level, identical with the clock input buffer structure shown in Fig. 3 A, the rising of internal clock signal intCLK and external timing signal extCLK synchronously rose to high level.When finished the time delay of inverse delayed circuit 2f, internal clock signal intCLK reduced to low level.Therefore, in the structure of clock input buffer shown in Fig. 4 A, the action of internal circuit allows signal ENABLE to stop to expend to reduce electric current according to clock, when having produced internal clock signal intCLK, internal clock signal has certain pulse width, makes the action sequence of internal circuit stablize constant.

The structure of the clock input buffer shown in Fig. 2 A, 3A and the 4A can adopt, and buffer same as the prior art, only caching process external timing signal also can adopt.

(formation 1 of data output control circuit)

Fig. 5 is the structural representation of data output control circuit 1 shown in Figure 1 and output circuit.The gate circuit 910a of output circuit 910 and output state circuit 910b have identical structure with existing output circuit shown in Figure 26.Corresponding part adopts identical Ref. No., repeats no more.

Data output control circuit 1 among Fig. 5 comprises: produce circuit 1a according to the internal shield indicator signal that adds data output shielding indication DQM generation internal shield command signal DQMO; Allowing signal OEMF to postpone (CAS stand-by period-2) clock shift unit 1b of (CAS stand-by period-2) individual clock period from reading of OEMF signal generating circuit shown in Figure 1; Make the anti-phase inverter circuit 1c of internal shield command signal DQMO; Receive the AND circuit 1d of the output signal of (CAD stand-by period-2) clock shift unit 1b and inverter circuit 1c; The single clock shift unit 1e of the clock period of the output signal delayed internal clock signal intCLK of AND circuit 1d; According to the steering logic door 1f that allows the conduction/non-conduction state of signal OEM and internal clock signal intCLK control gate circuit 910a from the output of single clock shift unit 1e; The delay circuit 1g that applies to output buffers circuit 910b after allowing signal OEM to postpone a schedule time from the output of single clock shift unit 1e.

Internal shield instruction signal generating circuit 1a has with Figure 29 and produces the identical structure of circuit to internal shield indicator signal shown in Figure 31.When adding data output shielding indication DQM activation, synchronously internal shield command signal DQMO is activated a clock period with internal clock signal intCLK.

AND circuit 1d comprises: the NAND door of the output signal of reception inverter circuit 1c and the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b; Phase inverter with the output signal that receives this NAND door.Steering logic door 1f comprises and receives the phase inverter that internal clock signal intCLK and output allow the NAND door of signal OEM and receives the output signal of this NAND door, and produce output complimentary to one another with internal clock signal CLKO and/CLKO.When internal clock signal intCLK allows signal OEM to be in high level, the output of permission data with output, the ternary anti-phase buffer 910aa that steering logic door 1f allows gate circuit 910a to comprise is taken into data RD from sensing circuit, and imposes on output buffers circuit 910b.

Fig. 6 is the structural representation of (CAS stand-by period-2) shown in Figure 5 clock shift unit 1b.(CAS stand-by period-2) clock shift unit 1b among Fig. 6 comprises: synchronously allow signal OEMF to postpone the single clock shift unit 1ba of a clock period reading with internal clock signal intCLK; The single clock shift unit 1b that synchronously output signal of single clock shift unit 1ba is postponed a clock period with internal clock signal intCLK; When expression the CAS stand-by period be 4 signal CL4 and/CL4 makes the tri-state buffers 1bc of the output signal process of single clock shift unit 1bb when activating, when the expression CAS stand-by period be 3 signal CL3 and/CL3 makes the tri-state buffers 1bd of the output signal process of single clock shift unit 1ba when activating; When expression the CAS stand-by period be 2 signal CL2 and/CL2 makes when activating and reads the tri-state buffers 1be that allows signal OEMF to pass through; Receive and the output signal of counter-rotating tri-state buffers ibc, 1bd and 1be and produce the phase inverter 1bf of signal OEMFS.

Fig. 7 is the sequential chart of the action of (CAS stand-by period-2) shown in Figure 6 clock shift unit 1b.Below with reference to Fig. 6 and Fig. 7 this action is described.

When applying sense order, from the clock period (being the clock period #0 of internal clock signal intCLK) of its external timing signal, during burst length in, reading and allowing signal OEMF is high level.In example shown in Figure 7, burst length is 4, read and allow signal OEMF in the period of four clock period, to be in the state of activation of high level, in the clock period of internal clock signal intCLK #4, read and allow signal OEMF to become low level unactivated state.

When the CAS stand-by period, (CL) was 2, the action of tri-state buffers 1be (see figure 6), other tri-state buffers 1bc and 1bd keep the high output impedance state.Therefore, when the CAS stand-by period is 2, reads and allow signal OEMF to be selected, become the state of activation of high level in during the pulse width that the clock period #0 of clock signal intCLK internally begins by tri-state buffers 1be and phase inverter 1bf.

When the CAS stand-by period is 3 (CL=3), tri-state buffers 1bd action, other tri-state buffers 1bc and 1be are in the high output impedance state.Therefore, the output signal of single clock shift unit 1ba is selected, outside output signal OEMFS, and the clock period #1 commencing signal OEMFS of clock signal intCLK becomes the state of activation of high level internally, becomes low level unactivated state at clock period #5.

When the CAS stand-by period is 4 (CL=4), tri-state buffers 1bc action, tri-state buffers 1bd and 1be become output high impedance state.Therefore, selected by the signal of single clock shift unit 1ba and 1bb, outside output signal OEMFS.That is, when the CAS stand-by period is 4, produce the signal OEMFS that allows signal OEMF to postpone two clock period backward than reading.That is, during the cycle 6, signal OEMFS is in the state of activation of high level at the cycle of internal clock signal #2.Read the shift time (time delay) that allows signal by regulating, can tackle a plurality of CAS stand-by period with a semiconductor storage according to the activationary time of CAS stand-by period conditioning signal OEMFS with tri-state buffers 1bc-1be.

Fig. 8 A is the figure of the structure of single clock shift unit 1ba shown in Figure 6,1bb and single clock shift unit 1e shown in Figure 5.Fig. 8 A shows their common structures, and input signal and output signal are represented with symbol IN and OUT respectively.Single clock shift unit among Fig. 8 A comprises: make the anti-phase phase inverter 1xa of input signal IN; Receive the NAND circuit 1xb of internal clock signal intCLK and input signal IN by phase inverter 1xa; Reception is from the NAND circuit 1xc of the output signal of the internal clock signal/intCLK of phase inverter 1Xa and phase inverter 1xa; Receive the NAND circuit 1xb of the output signal of phase inverter 1xb at one of its input end; And the NAND circuit 1xf of the output signal Φ A of the output signal of reception NAND circuit 1xc and NAND circuit 1xd.The output signal of NAND circuit 1xf is added in another input end of NAND circuit 1xd.NAND circuit 1xd and 1xf form a trigger.

The single clock shift unit further comprises: the circuit 1xg of the NAND of the output signal Φ A of reception internal clock signal intCLK and NAND circuit 1xd; Receive the NAND circuit 1xh of the output signal of internal clock signal intCLK and NAND circuit 1xf; Receive the NAND circuit 1xi of the output signal of NAND circuit 1xg at one of its input end; Receive the NAND circuit 1xj of the output signal of NAND circuit 1xh and 1xi.The output signal of NAND circuit 1xj is added on another input end of NAND circuit 1xi.From NAND circuit 1xi ' output signal output OUT.The action of the single clock shift unit shown in Fig. 8 A then, is described with reference to the sequential chart of Fig. 8 B.

In clock period #a, input signal IN rises to high level.At this moment, internal clock signal/intCLK is in low level, and the output signal of NAND circuit 1xb and 1xc is fixed on high level, makes signal Phi A condition constant.Therefore, output signal OUT state is constant, keeps low level.

At this clock period #a, when internal clock signal intCLK reduced to low level, corresponding internal clock signal intCLK rose to high level, and NAND circuit 1xb and 1xc are used separately as phase inverter, input signal IN is added on the NAND circuit 1xd by NAND circuit 1xb, makes signal Phi A condition change.At this moment, internal clock signal intCLK is in low level, and the output signal of NAND circuit 1xg and 1xh is fixed on high level, and the state of output signal OUT is constant.Therefore, realized having the delay circuit of the delay of 1/2 clock period by NAND circuit 1xb, 1xc, 1xd and 1xf.

At clock period #b, if internal clock signal intCLK rises to high level, NAND circuit 1xg and 1xh move as phase inverter, and signal Phi A is passed through, and make output signal OUT respective change.This action repeats, and when input signal IN was in high level, output signal OUT kept high level.

At clock period #c, when input signal IN reduced to low level, in response to the decline of internal clock signal intCLK among the clock period #c, input signal IN was transmitted, and internal signal Φ A condition changes.When internal clock signal intCLK was in low level, the state of output signal OUT was constant.When internal clock signal intCLK when the clock period, #d rose to high level, signal Phi A is by NAND circuit 1xg transmission, output signal OUT state changes.Therefore, by shifting function, can obtain a resulting output signal OUT of clock period input signal IN delayed internal clock signal intCLK.

Below, the action of data output control circuit shown in Figure 5 and output circuit is described with reference to the sequential chart of Fig. 9.Fig. 9 be 2 the CAS stand-by period, burst length is that 4 o'clock data are read action.According to external timing signal extCLK, with ono shot pulse form generation internal clock signal intCLK (using the clock input buffer shown in Fig. 3 A or the 4A).

Externally the cycle #0 of clock signal extCLK applies sense order.According to this sense order,, synchronously allow signal OEMF to be driven to state of activation reading with the rising edge of internal clock signal intCLK at clock period #0.Because the CAS stand-by period is 2, allow signal OEMF to be driven to state of activation simultaneously with reading from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b.Allow signal OEMF according to reading, under the control of selection/read-out control circuit 921 shown in Figure 1, in memory cell array, carry out the column selection operation, and the data of selected storage unit are added on the sensing circuit 908.This sense data RD becomes definite state at the latter half of clock period #0.

At the rising edge of the external timing signal extCLK of clock period #1, add data output shielding indication DQM and be activated, become high level, make internal shield indicator signal DQMO in the clock period of clock period #1, become state of activation.This internal data masking instruction signal DQMO and internal clock signal intCLK synchronously change (seeing Figure 29-31).

At clock period #1, sense data RD is in definite state.Because output allows signal OEM to be in low level unactivated state, steering logic door 1f (see figure 5) remains low level unactivated state to the clock signal clk O that is used to read.When output allows signal OEM when the clock period, #1 rose to high level, allow signal OEM according to internal clock signal intCLK with reading, the clock signal clk O that is used to read is driven to high level, gate circuit 910a conducting, sense data RD is transferred to output state circuit 910b.Output allows signal OEM quilt and internal clock signal intCLK synchronously to be driven to the state of activation of high level.Therefore, can be transferred to buffer circuit 910b reliably for the sense data RD that determines state.Output allows signal OEM to be added on the output state circuit 910b by delay circuit 1g.Therefore, postpone output according to this and allow signal OEMO, output buffers circuit 910b is actively changed, and caching process internal data DD produces outside sense data Dout.Therefore, can find out from output data Dout1 shown in Figure 9, allow signal OEMD and output to allow the time delay between the signal 0EM very long if postpone output, internal data DD can be very long with respect to the time that is provided with of this delay output permission signal OEMD, thereby can prevent to export invalid data.

According to the exterior shield indicator signal DQM among the clock period #1, output allows signal OEM to be driven to low level unactivated state at clock period #2.Thus, be used for the internal clock signal CLKO maintenance unactivated state (low level) that data are exported, gate circuit 910a remain off state at clock period #2.Thereby, in this clock period #2, gate circuit 910a exports the sense data RD (0) that is taken into constantly in clock period #1, when the retention time tH for postponing output permission signal OEMD of internal data DD extends to the internal data DD variation of #3 of following one-period always, thereby can obtain the very long retention time, prevent to export the output of invalid data when allowing signal OEM to change.

At clock period #3, output allows signal OEM to become state of activation.In response to the activation of output permission signal OEM, the clock signal clk O that is used to export rises to high level, gate circuit 910a conducting, and the data RD that sensing circuit is applied exports to output buffers circuit 910b as internal data DD.At this moment, #1 is identical with the clock period, output allows signal OEM synchronous with the clock signal clk O that is used to export, and internal data DD allows the time that is provided with of the rising of signal OEMD to prolong greatly by delay circuit 1g with respect to postponing output, thereby can prevent to export invalid data.

Below, in the last data of clock period #4 output pulse string length, output allows signal OEM to reduce to low level at clock period #5.When this output allowed signal OEM to reduce to low level, internal clock signal CLKO still kept low level, and gate circuit 910a continues output and is taken in clock period #4 and latched data.Therefore, the last data DD (3) of burst length can be set to very long with respect to the retention time that postpones output permission signal OEMD, in this case, can prevent the output of invalid data equally.

In the structure of data output control circuit shown in Figure 5, the clock signal clk O that is used to export only produces when output allows signal OEM to be in high level, and stops the generation of this output with clock signal clk when data output conductively-closed and pulse data end.Therefore, can not constitute unsettled inner sense data RD is delivered to the output buffers circuit as internal data DD, allow the retention time tH of signal OEM can be configured to long enough with respect to output.

If the time delay of gate circuit 910a is shorter, internal data DD allows the time that is provided with of signal OEM short with respect to output, just may export invalid data (seeing the output data Dout2 among Fig. 9).Yet, postpone output permission signal OEMD by adopting delay circuit 1g to produce, be added on the output buffers circuit, the time tS of setting can be set at long enough, can suppress the generation of invalid data effectively.

As mentioned above, according to embodiment of the present invention 1, only when output allows signal activation, gate circuit just and synchronously conducting of internal clock signal is taken into inner sense data and is transferred in the output buffers circuit.Therefore, it is long completely that internal data allows the retention time of signal to be set to respect to output, can prevent to export when the output buffers circuit from becoming the high output impedance state invalid data reliably.By using this output to allow the permission/unallowable state of the inhibit signal control output buffers circuit of signal, internal data can be arranged to very long with respect to the time that is provided with that the output buffers circuit allows, thereby, just can produce internal data, can prevent the output of invalid data reliably with the very long time that is provided with and very long retention time.

Thus, just can suppress the generation of the power supply noise that invalid data causes, the maloperation in the circuit such as processor or logical block that the system power supply fluctuation causes can be prevented, the operation tolerance limit (because must consider the tolerance limit decision operation tolerance limit relevant) of total system can be improved with noise.

(embodiment 2)

Figure 10 shows according to an embodiment of the present invention the figure of structure of the major part of 2 semiconductor storage.The structure of data output control circuit 1 and output circuit 910 has been shown among Figure 10.Similar to previous embodiments 1 (see figure 5), data output control circuit 1 comprises: the internal shield indicator signal produces circuit 1a; (CAS stand-by period-2) clock shift unit 1b; The anti-phase phase inverter 1c of internal shield indicator signal DQMO that produces circuit 1a from the internal shield indicator signal; Receive the AND circuit 1d of the output signal of phase inverter 1c and (CAS stand-by period-2) clock shift unit 1b; According to the clock signal/intCLK of complementation the half clock shift unit 1ea of the output signal of AND circuit 1d displacement; According to internal clock signal intCLK the half clock shift unit 1ea of the output signal OEMFS2 of half clock shift unit 1ea displacement; And be used for according to the output signal OEMFS2 of half clock shift unit 1ea and internal clock signal intCLK produce to the internal clock signal CLKO of gate circuit 910a output and/the steering logic gate circuit 1h of CLKO.

Half clock shift unit 1ea and 1eb corresponding respectively the one-level shift stages shown in Fig. 8 A.Therefore, half clock shift unit 1ea and 1eb are equivalent in the embodiment 1 single clock shift unit 1e is divided into the half clock shift unit of two-stage, difference only is that their adopt specific output to allow the signal OEMFS2 of preposition half clock period of signal OEM to produce the internal clock signal CLKO that is used to export, structure in addition all with embodiment 1 identical (see figure 5).Output circuit 910 is identical with embodiment 1, and counterpart adopts identical with reference to numbering, repeats no more.

Below, the action of output control circuit shown in Figure 10 and output circuit is described in conjunction with the sequential chart of Figure 11.Figure 11 be 2 the CAS stand-by period, burst length is that the data of carrying out in 4 o'clock are read action.

Externally the clock period #0 of clock signal extCLK applies sense order.According to this sense order, reading permission signal OEMF becomes the high level state of activation.Because the CAS stand-by period is 2, be upgraded to high level at clock period #0 rising edge from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b.At this clock period #0, exterior shield command signal DQM is in low level, makes from the signal OEMFS2 of the gate circuit 1d high level that rises in response to signal OEMFS.Then, the negative edge of half clock shift unit 1ea and internal clock signal intCLK synchronously is taken into the output signal OEMFS2 of gate circuit 1d, OEMFS2D is driven to high level signal, at clock period #0, carry out the reading of data of the selection of column of memory cells and select storage unit in inside, and at the latter half of clock period #0, sense data RD becomes definite state.Although signal OEMFS2D becomes high level, and internal clock signal intCLK is in low level, therefore, the clock signal clk O that is used to export keeps low level at clock period #0.

At clock period #1, internal clock signal intCLK rises to high level, because signal OEMFS2D is in high level, correspondingly, the clock signal clk O that is used to export from steering logic door 1h becomes high level, and sense data RD is transferred to output state circuit 910b by gate circuit 910a.The rising of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into the output signal of half clock shift unit 1ea, and output allows signal OEM to rise to high level.When this output allowed signal OEM to rise to high level, output state circuit 910b started, and caching process internal data DD produces external data Dout.

And at clock period #1, adding data output shielding indication DQM becomes high level, and the rising of internal shield indicator signal DQMO and internal clock signal intCLK synchronously rises to high level.When this internal shield indicator signal DQMO rose to high level, half clock shift unit 1ea reduced to low level to the output signal OEMFS2 of gate circuit 1d.When internal clock signal intCLK was in high level, half clock shift unit 1ea was in latch mode, and its output signal OEMFS2D is a high level.When internal clock signal intCLK reduced to low level, half clock shift unit 1ea was taken into the output signal OEMFS2 of gate circuit 1d, and the output signal OEMFS2D of self is reduced to low level, and the internal clock signal CLKO of output usefulness maintains low level.In response to the reduction of internal clock signal intCLK, half clock shift unit 1eb enters latch mode, therefore, allows signal OEM to keep high level at clock period #1 from the output of half clock shift unit 1eb.

At clock period #2, because internal clock signal intCLK is when being in high level, half clock shift unit 1ea is in latch mode, therefore, its output signal OEMFS2D maintains low level, and the internal clock signal CLKO Be Controlled logic gate 1h that is used to export remains on low level.Therefore, the data RD (1) that has stoped gate circuit 910a to be taken in clock period #1 and #2, to read, the data DD that has read in clock period #1 (0) is provided for output state circuit 910b.

When internal clock signal intCLK rose to high level, half clock shift unit 1eb was taken into the output signal OEMFS2D of half clock shift unit 1ea, allowed output signal OEM to reduce to low level.Therefore, output state circuit 910b becomes the high output impedance state.Inactivation according to output permission signal OEM at clock period #2, applies internal data DD from gate circuit 910a continuously, therefore, can guarantee very long retention time tH, and the output of invalid data does not take place.

Add data output masking instruction DQM and only activate at clock period #1, #2 is driven to low level in the clock period, and correspondingly, low level is synchronously reduced in the rising of internal clock signal intCLK among internal shield indicator signal DQMO and the clock period #2.In response to the decline of internal shield indicator signal DQMO, rise to high level (signal OEMFS during burst length in continue to keep high level) from the signal OEMFS2 of gate circuit 1d.When signal OEMFS2 when the clock period, #2 rose to high level, the negative edge of half clock shift unit 1ea and internal clock signal intCLK synchronously is taken into signal OEMFS2, OEMFS2D is driven to high level its output signal.At clock period #2, even when signal OEMFS2D rises to high level, half clock shift unit 1eb also still is in latch mode in response to the decline of internal clock signal intCLK, and output allows signal OEM to keep low level unactivated state.

At clock period #3, when internal clock signal intCLK rose to high level, because signal OEMFS2D is in high level, the internal clock signal intCLK that is used to export rose to high level.Thus, gate circuit 910a conducting is transferred to cache circuit 910b to inner sense data RD (2).

On the other hand, the rising edge of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into the output signal OEMFS2D of half clock shift unit 1ea, allows output signal OEM to be driven to high level.

When signal OEMFS2D was in high level, steering logic door 1h produced the internal clock signal CLKO that is used to export as buffer according to internal clock signal intCLK.On the other hand, the rising of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into signal OEMF2D, produces output and allows signal OEM.Therefore, output allows signal OEM to become state of activation in the late moment of rising edge than the internal clock signal CLKO that is used for data output.Thereby gate circuit 910a allows the activation moment conducting early of signal OEM specific output, is taken into inner sense data RD and exports to output buffers circuit 910b.Then, output allows signal OEM to activate, and internal data DD allows the time that the is provided with tS of signal OEM to be increased greatly with respect to output.Even exporting masked state when the data output state changes from data, also can not export invalid data, output data Dout can stably produce according to inner sense data RD.Especially, the time delay of half clock shift unit 1eb, the time tS of setting can be set as long in the extreme when being longer than the time delay of gate circuit 910a greatly.

At clock period #4,, read and allow signal OEMF and, synchronously reduce to low level with the rising of internal clock signal intCLK from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b because whole pulse length data all are read out.Thus, also reduce to low level from the output signal OEMFS2 of gate circuit 1d, the decline of half clock shift unit 1ea and internal clock signal intCLK synchronously is taken into signal OEMFS2, and OEMFS2D reduces to low level its output signal.The negative edge of half clock shift unit 1eb and internal clock signal intCLK synchronously becomes latch mode, and output allows signal OEM to keep high level.Therefore, in clock period #4, according to the internal clock signal CLKO that is used to export, inner sense data RD (3) is transferred to output buffers circuit 910b by gate circuit 910a, and output buffers circuit 910b produces output data Dout.

In clock period #5, half clock shift unit 1eb is taken into and is in low level signal OEMFS2D, synchronously allows output signal OEM to be driven to low level with the rising of internal clock signal intCLK.Thus, output circuit 910 becomes the high output impedance state.In this state, gate circuit 910a is in latch mode (internal clock signal CLKO keeps low level owing to signal OEMFS2D is in low level), data DD is very long with respect to the retention time of the decline of output permission signal OEM, therefore, when being transformed into this high output impedance state, do not export invalid data.

As shown in figure 10, the signal OEMFS2D that uses specific output to allow signal OEM to shift to an earlier date half clock period produces the internal clock signal CLKO that is used to export, thus, can be long in the extreme with respect to the time that is provided with and the retention time of exporting the variation that allows signal, can prevent the output of invalid data.

Especially, if the steering logic door 1h that produces the internal clock signal CLKO be used to export compares time delay that the gate circuit 910a of output state circuit 910b has negligible words with being taken into inner sense data RD and internal data DD being transferred to the time delay of half clock shift unit 1eb, internal data DD allows the time that the is provided with tS of signal OEM can be set to the value of an expectation reliably with respect to output, need not postpone output again and allow signal OEM, can realize that high-speed data reads.

(embodiment 3)

Figure 12 shows according to an embodiment of the present invention the figure of structure of the major part of 3 semiconductor storage.Figure 12 shows the structure of data output control circuit 1 and output circuit 910.Among Figure 12, data output control circuit 1 comprises: according to internal clock signal intCLK (CAS stand-by period-2) clock shift unit 1b that allows signal OEMF displacement that reads from OEMF signal generating circuit (not shown); The half clock shift unit 1ea of half clock period of the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b displacement internal clock signal intCLK; The half clock shift unit 1eb of half clock period of the CLK of the output signal OEMFSD of half clock shift unit 1ea displacement internal clock signal; The half clock shift unit 1ec of half clock period of the output signal OEM of half clock shift unit 1eb displacement internal clock signal intCLK; Produce the steering logic door 1I of the internal clock signal CLKO that is used for output data according to output signal OEMFSD, the OEMD of half clock shift unit 1ea, 1ec and internal clock signal intCLK.

Output from half clock shift unit 1eb allows signal OEM to be added on the output state circuit 910b.Complement signal/the intCLK of half clock shift unit 1ea and 1ec and internal clock signal synchronously is taken into added signal, and half clock shift unit 1eb and internal clock signal intCLK synchronously are taken into added signal.

Steering logic door 1i comprises: receive internal clock signal and from the NAND circuit 1ia of the signal EMFSD of half clock shift unit 1ea; Receive the output signal of NAND circuit 1ia and from the signal OEMD of half clock shift unit 1ec and produce the NAND circuit 1ib of the internal clock signal CLKO that is used for output data.Gate circuit 910a has the structure identical with previous embodiments with output buffers circuit 910b, and counterpart adopts identical figure number, repeats no more.

In structure shown in Figure 12, when the signal OEMD from half clock shift unit 1ec is in the low level unactivated state, the internal clock signal CLKO that is used for data output is in high level, and gate circuit 910a is transferred to output buffers circuit 910 to inner sense data RD.Therefore, before output allowed signal OEM to activate, inner sense data RD was transferred to output buffers circuit 910b, made that internal data DD can be very long with respect to the time that is provided with of output permission signal OEM.When signal OEMFSD became low level unactivated state and signal OEMD and becomes the state of activation of high level, the internal clock signal CLKO that is used for data output became low level, and gate circuit 910a ends, and institute adds data and is latched.Therefore, before output allowed signal OEM inactivation, gate circuit 910a became latch mode, and internal data DD allows the retention time of signal OEM to increase with respect to output.Thus, can prevent the output of invalid data.The action of data output control circuit shown in Figure 12 and output circuit is described below with reference to the sequential chart of Figure 13.

When #0 applied sense order in the clock period, the rising of reading permission signal OEMF and internal clock signal intCLK synchronously rose to high level.Because the CAS stand-by period is 2, also rise to high level from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b.Because the complement signal/intCLK of half clock shift unit 1ea and internal clock signal synchronously is taken into institute's plus signal, so at clock period #0, signal OEMFSD rises to high level according to internal clock signal intCLK.In clock period #0, output allows signal OEM and signal OEMD all to be in low level unactivated state, and output state circuit 910b is in the high output impedance state.On the other hand, the internal clock signal CLKO that is exported by steering logic door 1i is in high level, and the ternary anti-phase buffer 910aa of gate circuit 910a is in operating state.Therefore, the data of reading in clock period #0 are transferred to output state circuit 910b by gate circuit 910a.

At clock period #1, half clock shift unit 1eb and internal clock signal intCLK synchronously are taken into the plus signal OEMFSD of institute, allow output signal OEM to be driven to noble potential.Thus, output buffers circuit 910b becomes the output low impedance state, and caching process internal data DD produces output data Dout.When output state circuit 910b becomes operating state, promptly, when output allows signal OEM to become the state of activation of high level, internal data DD is transmitted, make internal data DD allow the time that the is provided with tS of signal OEM to have enough length with respect to output, therefore, produce output data Dout and do not produce invalid data according to internal data.

At clock period #1, the decline of half clock shift unit 1ec and internal clock signal intCLK synchronously is taken into output and allows signal OEM, and OEMD is driven to high level with its output signal, and the NAND circuit 1ib that steering logic door 1i comprises is as phase inverter.At this moment, signal OEMFSD also is a high level, and also as phase inverter, the internal clock signal CLKO that is used to export produces according to internal clock signal intCLK NAND circuit 1ia.Therefore, during pulse width in, promptly at clock period #2, #3 and #4, produce internal data DD according to inner sense data RD, produce output data Dout.

At clock period #4, finish during the burst length, so, read and allow signal OEMF inactivation, reduce to low level from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b.When internal clock signal intCLK was in high level, half clock shift unit 1ea was in latch mode, made signal OEMFSD keep high level, and low level is synchronously reduced in the decline of signal OEMFSD and internal clock signal intCLK.Thus, the output signal of NAND circuit 1ia becomes high level.Because signal OEMD still is in high level, remain low level from the clock signal clk O of NAND circuit 1ib.

At clock period #5, half clock shift unit 1eb and internal clock signal intCLK rise and synchronously are taken into signal OEMFSD, allow output signal OEM to be driven to the low level of non-activated state.Thus, output buffers circuit 910b becomes output high impedance state.At clock period #5, even when internal clock signal intCLK rises to high level, signal OEMD still is in high level, so, still keeping low level from the clock signal clk O of steering logic door ri, gate circuit 910a keeps latch mode.

At half clock shift unit 1ec, synchronously be taken into output with the decline of the internal clock signal intCLK of clock period #5 and allow signal OEM, signal OEMD is driven to before the low level, the internal clock signal CLKO of output usefulness keeps low level.Therefore, when output allows signal OEM inactivation, internal data DD allows the retention time tH of signal OEM to equal half clock period of internal clock signal intCLK with respect to output, can prevent the invalid data output when this output allows signal OEM inactivation reliably.Afterwards, internal clock signal CLKO keeps high level, and gate circuit 910 keeps conducting state, and output state circuit 910b utilizes output to allow signal OEM inactivation and keeps output high impedance state.

As mentioned above, according to an embodiment of the present invention 3, the internal clock signal CLK that is used to export is arranged on the state that keeps the gate circuit conducting, utilize the inhibit signal of the output permission signal of the output impedance of controlling the output buffers circuit, produce the clock signal that is used to export according to internal clock signal, and, use specific output to allow the signal of preposition half clock period of signal to stop the generation of internal clock signal, utilize to postpone the conducting that output allows signal to keep gate circuit.Therefore, when output allows signal activation, data have been added on the output state circuit, also have, when output allowed signal OEM inactivation, the generation of internal clock signal stopped, gate circuit is in latch mode, therefore, the time that is provided with of internal data and retention time can be very long, can prevent the output of invalid data.

(embodiment 4)

Figure 14 shows according to an embodiment of the present invention the figure of structure of the major part of 4 semiconductor storage.Figure 14 shows the structure of data output control circuit 1 and output circuit 910.Structure shown in Figure 14 and shown in Figure 12 basic identical, difference is, is used to produce the internal shield command signal DQMO of circuit 1a and produce the internal clock signal CLKO and the output that are used to export from the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b from the internal shield indicator signal allow signal OEM.

Promptly, in structure shown in Figure 14, provide the anti-phase phase inverter 1c of the internal shield indicator signal DQMO that produces circuit 1a from the internal shield indicator signal and received the output signal of phase inverter 1c and the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b and its output signal OEMFS2 is added to the AND circuit 1d that half clock shift unit 1ea gets on.In addition structure is same as shown in Figure 12, is the title difference from the next signal of half clock shift unit 1ea.The action of circuit shown in Figure 14 is described below with reference to the sequential chart of Figure 15.

At clock period #0, apply sense order, the rising of reading permission signal OEMF and internal clock signal intCLK synchronously rises to high level, and because pulse width is 4, keeps high level before clock period #4.Because the CAS stand-by period is 2, synchronously rises to high level from the signal OEMFS of (CAS stand-by period-2) clock shift unit 1b and the rising of internal clock signal intCLK, correspondingly, makes the output signal OEMFS2 of AND circuit 1d also rise to high level.Because signal OEMD is in low level, so the internal clock signal CLKO of the NAND circuit 1ib output from steering logic door 1i keeps high level, gate circuit 910a is in conducting state.

At clock period #0, the signal OEMFS2D and the internal clock signal intCLK that export from half clock shift unit 1ea synchronously rise to high level.

At clock period #1, adding data output shielding indication DQM becomes high level, and internal shield indicator signal DQMO becomes high level according to the rising of internal clock signal intCLK, and feasible signal OEMFS2 from AND circuit 1d reduces to low level.The decline of half clock shift unit 1ea and internal clock signal intCLK synchronously is taken into signal OEMFS2, and OEMFS2D is driven to low level with its output signal.

On the other hand, the rising of the internal clock signal intCLK of half clock shift unit 1eb and clock period #1 synchronously is taken into the signal OEMFS2D that is in high level, and OEM is driven to high level with its output signal.At this moment, inner sense data RD is transferred to output state circuit 910b by the gate circuit 910a of conducting state, and output state circuit 910b allows signal OEM caching process internal data DD according to the output of state of activation, produces output data Dout.Therefore, similar to previous embodiments 3 in this case, the time that the is provided with tS of internal data DD is long completely, does not follow the generation of invalid data when producing output data Dout.

At clock period #1, the decline of half clock shift unit 1ec and internal clock signal CLK synchronously is taken into the output high level and allows signal OEM, and OEMD is driven to high level with its output signal.Signal OEMFS2D synchronously is driven to low level by the decline with internal clock signal intCLK, and two inputs of the NAND circuit 1ib of steering logic door 1i become high level, and CLKO is fixed on low level internal clock signal.

At clock period #2, low level (add output shielding indication DQM and only indicate shielding second output data) is synchronously reduced in the rising of internal shield indicator signal DQMO and internal clock signal intCLK.Decline in response to internal shield command signal DQMO, signal OEMFS2 from AND circuit 1d rises to high level, therefore, synchronously rise to high level from the signal OEMFS2D of half clock shift unit 1ea and the decline of internal clock signal intCLK, the NAND circuit 1ia of steering logic door 1i is as phase inverter.

At clock period #2, the rising of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into and is in low level OEMFS2D, makes output allow signal OEM to be driven to low level, and output buffers circuit 910b becomes output high impedance state.At this clock period #2, when internal clock signal intCLK was in high level, the internal clock signal CLKO that is used to export was fixed on low level.Therefore, gate circuit 910 is in latch mode.Then, synchronously drop to low level from the signal OEMD of half clock shift unit 1ec and the decline of internal clock signal intCLK, internal clock signal CLKO becomes high level.Therefore, when output allows signal OEM when clock period #2 becomes low level non-activated state, internal data DD is in latch mode in during half clock period of internal clock signal intCLK, so, allow signal OEM for output, internal data DD has the sufficiently long retention time.Therefore, when masked state changes, can prevent the output of invalid data.

When internal clock signal CLKO rose to high level, gate circuit 910a conducting was carried inner sense data RD (1) to output state circuit 910b.Yet in this case, output allows signal OEM to be driven to low level, and output state circuit 910b is in output high impedance state, and Chuan Shu data DD (1) is not output thus.Then, at clock period #2, new content sense data RD is transmitted and becomes definite state.Internal clock signal CLKO is in low level, and gate circuit 910a conducting makes sense data RD (2) be transferred to output state circuit 910b.

At clock period #3, the rising of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into the signal OEMFS2D that is in high level, make output allow signal to rise to high level, then, also synchronously rise to high level from the signal OEMD of half clock shift unit 1ec with the decline of internal clock signal intCLK.Therefore, allow signal OEM when activated state changes in output, inner sense data RD (2) is transferred to output buffers circuit 910b as data DD (2), makes that time ts is set is long completely.Therefore, do not follow invalid data ground that internal data DD (2) is carried out caching process, output output data Dout (2).

Then, at clock period #4, finish during the burst length, signal OEMF and OEMFS drop to low level, then, when signal OEMFS2 reduced to low level, signal OEMFS2D also synchronously reduced to low level with the decline of internal clock signal intCLK, and the output signal of NAND circuit 1ia is fixed on high level.Thereby, at clock period #4, when internal clock signal intCLK was in high level, signal OEMFS2D and OEMD were in low level, make internal clock signal CLKO according to internal clock signal intCLK output, inner sense data RD is outputed to output state circuit 910b by transmission.When internal clock signal intCLK reduced to low level, signal OEMFS2D became low level, and two inputs of NAND circuit 1ib become high level, and therefore, CLKO is fixed on high level internal clock signal.Thus, gate circuit 910a becomes latch mode.

At clock period #5, the rising of half clock shift unit 1eb and internal clock signal intCLK synchronously is taken into and is in low level signal OEMFS2D, allows output signal OEM to reduce to low level, at this moment, internal clock signal CLKO is still in low level, and gate circuit 910a is in latch mode.IntCLK reduces to low level when internal clock signal, and half clock shift unit 1ec is taken into low level output and allows signal OEM, and OEMD is driven to low level with its output signal.Thus, the internal clock signal CLKO that is used to export is fixed on high level.Therefore, allow signal OEM when state of activation changes in output, inner sense data DD is in latch mode in during half clock period, makes retention time tH long completely, has prevented the output of invalid data.

Promptly, inner sense data is according to allowing the synchronous internal clock signal intCLK of signal OEM to transmit to the output buffers circuit with output, so internal data can be long completely with respect to the time that is provided with and the retention time of output permission signal, can prevent the output of invalid data.Its reason is: when output allows signal transition to become state of activation, at first inner sense data is transferred to the output buffers circuit, when output allowed the signal inactivation, gate circuit remained on latch mode.

(embodiment 5)

Shown in Figure 16 is the figure of the major part structure of 5 semiconductor storage according to an embodiment of the present invention, and Figure 16 also shows the part-structure of data output control circuit 1 and output circuit 910.Similar to data output control circuit 1 shown in Figure 12, data output control circuit 1 shown in Figure 16 comprises: allow signal OEMF to postpone (CAS stand-by period-2) clock shift unit 1b of (CAS stand-by period-2) (individual) clock period reading; The half clock shift unit 1ed that the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b is postponed half clock period; The half clock shift unit 1ef that the output signal OEMFSD of half clock shift unit 1ed is postponed again half clock period; The half clock shift unit 1eg that the output signal of half clock shift unit 1ef is postponed half clock period.According to the complement signal/intCLK of internal clock signal, half clock shift unit 1ec and 1eg are taken into and latch institute's plus signal.Half clock shift unit 1f is taken into and latchs institute's plus signal according to the CLK of internal clock signal.

Data output control circuit 1 further comprises: produce circuit 1a according to the internal shield indicator signal that adds data output shielding indication extDQM generation internal shield command signal DQMO; The half clock shift unit 1ja that instructs DQMO to postpone half clock period from the internal shield of internal shield indicator signal generation circuit 1a; The half clock shift unit 1jb that the output signal DQMO of half clock shift unit 1ja is postponed again half clock period; The half clock shift unit 1jc that the output signal DQMi of half clock shift unit 1jb is postponed again half clock period.Half clock shift unit 1ja and 1jc are taken into institute's plus signal according to the complement signal/intCLK of internal clock signal, and half clock shift unit 1jb is taken into and latchs the signal that is taken into according to internal clock signal intCLK.

Data output control circuit 1 further comprises: the steering logic door 1k that produces the internal clock signal CLKO that is used for data output according to the output signal DQMD from the output signal DQMOD of signal OEMFSD, the half clock shift unit 1ja of half clock shift unit 1ed and half clock shift unit 1ac.Steering logic door 1k comprises: receive the output signal OEMFSD of internal clock signal intCLK, half clock shift unit 1ed and the NAND circuit 1ka of the output signal DQMOD of the half clock shift unit 1ja that applies by phase inverter 1x; Receive the output signal of output signal OEMD, NAND circuit 1ka of half clock shift unit 1eg and the output signal DQMD of the half clock shift unit 1jc that applies by anti-phase letter 1y, and produce the NAND circuit 1kb of the internal clock signal CLKO that is used to export.Internal clock signal CLKO is by the anti-phase benefit internal clock signal/CLKO that becomes of phase inverter, the conduction/non-conduction of the ternary anti-phase buffer 910aa that control gate circuit 910a is contained.

Gate circuit 910a has the structure similar to prior art.Output state circuit 910b comprises: the anti-phase phase inverter 910ba of the output signal of gate circuit 910a; Reception allows signal OEM, indicates the AND circuit 910bf of the output signal of DQMi and gate circuit 910a from the internal shield of half clock shift unit 1jb from the output of half clock shift unit 1ef; Receive the AND circuit 910bg that output allows the output signal of signal OEM, internal data output shielding indication DQMi and phase inverter 910ba, conducting when the output signal of AND circuit 910bf is high level, the n channel MOS transistor 910bd of the output signal Dout of generation high level (supply voltage value); And conducting when the output signal of AND circuit 910bg is high level, produce the n channel MOS transistor 910be of the output signal Dout with earth level.

When output allowed signal OEM activation, the non-activation of internal data output masking instruction DQMi, output state circuit 910b produced output data Dout according to the data of giving from gate circuit 910a.In the structure of data output control circuit 1 shown in Figure 16, internal shield indication DQMi allows signal OEM to form by different approach with output, allows the output impedance of signal OEM and internal data output masking instruction DQMi control output state circuit 910b according to output.

At output state circuit 910b when output high impedance state changes, steering logic door 1k gate circuit 910a is set to latch mode, when the output low impedance state changes, is set to conducting state with fast sequential gate circuit 910a, thus, the time of setting and retention time have been prolonged.Below, the action of data output control circuit shown in Figure 16 1 and output circuit 910 is described with reference to the sequential chart of Figure 17.Figure 17 also show the CAS stand-by period be 2, burst length is that 4 o'clock data are read action.

#0 applies sense order in the clock period, and inside is read and allowed signal OEMF and internal clock signal intCLK synchronously to rise to high level, also rises to high level from the OEMFS of (CAS stand-by period-2) clock shift unit 1b.Then, synchronously rise to high level from the output signal OEMFSD of half clock shift unit 1ed and the decline of internal clock signal intCLK.According to reading the activation that allows signal OEMF, carry out the selection of storage unit and reading of data in inside.

At clock period #1, adding data output masking instruction extDQM becomes high level, synchronously rises to high level from the signal DQMO of internal shield indicator signal generation circuit 1a and the rising of internal clock signal intCLK.Output from half clock shift unit 1ef allows the rising of signal OEM and internal clock signal intCLK synchronously to become the state of activation of high level, synchronously rises to high level from the signal OEMD of internal clocking shift unit 1eg and the decline of internal clock signal intCLK.When signal OEMD rises to high level, become high level from the signal DQMOD of half clock shift unit 1ja, the output signal of phase inverter 1x becomes low level, and the output signal of NAND circuit 1ka becomes high level.Signal DQMD from half clock shift unit 1ac remains low level, and the output signal of phase inverter 1y is a high level.Therefore, the output signal CLKO of NAND circuit 1kb drops to low level in response to the rising of signal OEMD.Thus, become the state that is taken into and latchs by gate circuit 910a at the inside sense data RD that clock period #1 reads.

Because it is high level that output allows signal OEM, inner sense data output shielding indication DQMi is a low level, and output state circuit 910b is according to producing output data Dout by the added data DD of gate circuit 910a.Allow signal OEM when state of activation changes in output, gate circuit 910a is transferred to output state circuit 910b to inner sense data RD according to the internal clock signal CLKO of high level, thereby obtained the very long time that is provided with, only exported valid data, do not exported invalid data.

Be in signal DQMOD time of a clock period of high level from half clock shift unit 1ja, the output signal of phase inverter 1x is a low level, the output signal of NAND circuit 1ka is Gao Ping accordingly, and the internal clock signal CCKO that is used to export kept low level always before the output signal DQMD of half clock shift unit 1jc rises to high level.Therefore, at this moment, gate circuit 910a keeps latch mode, even at the inner sense data RD of clock period 2 transmission, this inside sense data RD is not transmitted during this.

If the decline of the output signal DQMD of half clock shift unit 1jc and the internal clock signal intCLK of clock period #2 synchronously rises to high level, the output signal of phase inverter 1y just becomes low level, the output signal CLKO of NAND circuit 1kb becomes high level, gate circuit 910a conducting, sense data RD is transferred to output state 910b.Yet, at this moment, with the rising of the internal clock signal intCLK of clock period #2 synchronously, rise to high level from the signal DQMi of half clock shift unit 1jb, complement signal/the DQMi of internal shield signal becomes low level, thus, output state circuit 910b becomes output high impedance state, thereby invalid data DD (1) does not export.

At clock period #3, with the rising of internal clock signal intCLK synchronously, reduce to low level from the signal DQMi of half clock shift unit 1jb, accordingly, complement signal/the DQMi of internal shield signal becomes high level, and output state circuit 910b becomes the output low impedance state again.At this moment, with the decline of the internal clock signal intCLK of clock period #2 synchronously, internal clock signal CLKO becomes high level state according to signal DQMD, till the internal clock signal intCLK that this state remains to clock period #3 always descends.Therefore, before signal DQMi descended, inner sense data RD had been transferred to output state circuit 910b, and it is very long therefore to be set the time, output valid data and do not export invalid data.

At clock period #4, signal DQMOD and DQMD become low level, signal DEMD is a high level, therefore, the internal clock signal CLKO that is used to export produces according to internal clock signal intCLK, inner sense data RD (3) is added on the output buffers circuit 910b by gate circuit 910a, exports last data Dout (3).

At clock period #5, output allows signal OEM synchronously to drop to low level according to the rising of internal clock signal intCLK, and output buffers circuit 910b becomes the high output impedance state.At this moment, signal OEMFSD synchronously drops to low level with the decline of the internal clock signal intCLK of clock period #4, the output signal of the NAND circuit 1ka of steering logic door 1K becomes high level, accordingly, the output signal of NAND circuit 1kb also becomes low level, and gate circuit 910a is in latch mode.When signal OEMD reduced to low level, the decline of internal clock signal CLKO that is used to export and the internal clock signal intCLK of clock period #5 synchronously was returned to high level.Thereby in during half clock period of internal clock signal intCLK, gate circuit 910a is in latch mode, and the retention time tH of the internal data DD when output allows that signal OEM is non-to be activated ten minutes is long, can prevent the output of invalid data thus.

As mentioned above, according to embodiment of the present invention 5, even in produce the output state circuit that output allows signal OEM and internal data shielding indication DQMi by different approaches according to the structure of these two kinds of signal controlling output impedance, when allowing data output to change, lead to the output buffers circuit the gate circuit guide and transmit data, from allowing data output when not allowing data output to change, use output to allow the be shifted signal of half clock period of signal and internal data output shielding indicator signal the conduction and cut-off of gate circuit to be controlled to be gate circuit is remained on latch mode, so, the time that is provided with of internal data signal and retention time can be set at very long, can not exported the output circuit of invalid data.

(embodiment 6)

Figure 18 shows according to an embodiment of the present invention the figure of structure of the major part of 6 semiconductor storage.Also show the structure of data output control circuit 1 and output circuit 910 among Figure 18.Among Figure 18, data output control circuit 1 comprises: allow signal OEMF to postpone (CAS stand-by period-2) clock shift unit 1b of (CAS stand-by period-2) (individual) clock period reading; The output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b is postponed 1 clock period, produces the single clock shift unit 1e that output allows signal OEM; Produce circuit 1a according to the internal shield indicator signal that adds data output shielding indication extDQM generation internal shield indicator signal DQMO; The half clock shift unit 1ja of half clock period of internal shield indicator signal DQMO delayed internal clock signal intCLK; The half clock shift unit 1jb of half clock period of the output signal DQMOD delayed internal clock signal intCLK of half clock shift unit 1ja, generation internal data output shielding indication DQMi; And according to the output signal DQMOD of half clock shift unit 1ja and internal clock signal intCLK produce the internal clock signal CLKO that is used for data output and/the steering logic door 1m of CLKO.

This steering logic door 1m comprises: receive signal DQMOD and the internal clock signal intCLK that applies by phase inverter 1mc, the NAND circuit 1ma that produces complement signal/CLKO; And phase inverter 1mb anti-phase the output signal of NAND circuit 1ma, that produce the internal clock signal CLKO of output usefulness.

Output circuit 910 comprises: according to the internal clock signal CLKO that is used to export and/CLKO becomes the gate circuit 910a of conducting or cut-off state; And allow signal OEM and internal data output shielding indication/DQMi to control its output impedance, export output buffers circuit 910b from the internal data DD of gate circuit 910a according to output.Gate circuit 910a has and identical structure shown in Figure 16 with output buffers circuit 910b, and appropriate section adopts identical figure number.

Output buffers circuit 910b receives internal data output shielding indication/DQMi and output allows signal OEM.Yet, also can adopt structure same as shown in Figure 5, the output signal that wherein, will receive the AND circuit of the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b and internal shield indicator signal DQMO is added on the single clock shift unit 1e.

In data output control circuit shown in Figure 180 1, steering logic door 1m stops to export the generation of using internal clock signal CLKO according to data mask indicator signal DQMOD.Therefore, the generation of internal clock signal CLKO only stops during shielding.That is, gate circuit 910a becomes latch mode.Below, the action of circuit shown in Figure 180 is described in conjunction with the sequential chart of Figure 19.Figure 19 be 2 the CAS stand-by period, burst length is the action of carrying out in 4 o'clock.

#0 applies sense order in the clock period, reads to allow the rising of signal OEMF and internal clock signal intCLK synchronously to rise to high level, and the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b also rises to high level.Because internal shield indicator signal DQMO is nonactivated low level, signal DQMOD also is in low level, and output produces according to internal clock signal intCLK with internal clock signal CLKO and/CLKO.At clock period #0, carry out the data of select storage unit and read.

At clock period #1, adding shielding indicator signal extDQM becomes high level, and the rising of internal shield indicator signal DQMO and internal clock signal intCLK synchronously becomes high level (only carrying out data output shielding at clock period #1) in time clock period.Then, the output signal DQMOD of half clock shift unit 1ja and the decline of internal clock signal intCLK synchronously rise to high level, the output signal of the NAND circuit 1ma that steering logic door 1m is contained becomes high level, the output signal CLKO of phase inverter 1mb becomes low level, and gate circuit 910a becomes latch mode.At this clock period #1, output allows the rising of signal OEM and internal clock signal intCLK synchronously to rise to high level, and output data Dout produces according to the internal data DD from gate circuit 910a transmission.

At clock period #2, the rising of internal data output shielding indication DQMi and internal clock signal intCLK synchronously becomes high level, and output state 910b becomes output high impedance state.Under this state, the internal clock signal CLKO that is used to export keeps low level, so, gate circuit 910a correspondingly keeps latch mode, make output state circuit 910b retention time tH of internal data DD when output high impedance state changes equal the length of a clock period, its long enough can prevent the output of invalid data.At clock period #2, the output signal DQMOD of half clock shift unit 1ja and the decline of internal clock signal intCLK synchronously become low level, thus steering logic door 1m according to internal clock signal intCLK produce internal clock signal CLKO and/CLKO.

At clock period #3, the rising of internal data output shielding indication DQMi and internal clock signal intCLK synchronously becomes low level, and output state circuit 910b produces output data Dout according to adding internal data DD.

Then,, finish between train of impulses is long-term, read the rising of permission signal OEMF and internal clock signal intCLK and synchronously reduce to low level, and the output signal OEMFS of (CAS stand-by period-2) clock shift unit 1b also reduces to low level at clock period #4.At this moment, output allows signal OEM still at high level, produces internal clock signal CLKO.Therefore, according to data clock signal CLKO, inner sense data RD (3) is added on the output state circuit 910b by gate circuit 910a, and the last data DD (3) of burst length produces as output data.

Then, at clock period #5, output allows the rising of signal OEM and internal clock signal intCLK synchronously to reduce to low level, and output state circuit 910b becomes output high impedance state.

Internal data DD allows the time that the is provided with tS of signal OEM with respect to output, by longer than the time expand of steering logic door 1m and gate circuit 910a being set to the time delay of single clock shift unit 1e (gate delay counter), with regard to long enough.Yet, allow signal OEM when non-activated state changes in output, the retention time tH of internal data DD can shorten, and when output high impedance state changed, invalid data may be exported among the output data Dout1 in Figure 19.On the contrary, when time tS shortening was set, retention time tH increased, and allowed signal OEM invalid data when non-activated state changes not export in output, and time tS shortening is set, and as shown in figure 19, output has the possibility of invalid data.For preventing the generation of this situation, when the long final data of pulse was exported, inner sense data RD ' remained latch mode.At this moment, if adopt the very long time that is provided with, promptly, if constitute data output with internal clock signal CLKO with the activation of specific output permission signal OEM faster sequential rise to high level, make gate circuit 910a conducting, then because the retention time tH of this structure ten minutes is long, shown in internal data DD ' and output data Dout1 ', do not export invalid data.For internal data DD ', produce internal clock signal CLKO, apply the sense data RD ' (3) that latchs repeatedly, so same data are applied as internal data DD ' continuously, can prolong retention time tH.

Figure 20 is the figure of structure that produces the part of inner sense data RD ' and internal data DD '.

In Figure 20, the transfer circuit 10 that becomes conducting or latch mode according to signal OEMFS is set between sensing circuit 908 and output circuit 910.Transfer circuit 10 comprises: handle was from the anti-phase ternary anti-phase buffer 10a of the inside sense data RD of sensing circuit 908 when signal OEMFS activated; Anti-phase the output signal of ternary anti-phase buffer 10a, as to produce inner sense data RD ' phase inverter 10b; And phase inverter 10c anti-phase the output signal RD ' of phase inverter 10b, that transmit to the importation of phase inverter 10b.Phase inverter 10b and 10c form the phase inverter latch.

According to structure shown in Figure 20, in signal waveforms shown in Figure 10, transfer circuit 10 produces sense data RD ' according to added inner sense data RD in clock period #0-#4, and it is added on the gate circuit 910a of output circuit 910.When signal OEMFS was in low level non-activated state, ternary anti-phase buffer 10a became output high impedance state, and transfer circuit 10 becomes latch mode.Thereby, if signal OEMFS synchronously reduces to low level words in the rising of clock period #4 and internal clock signal intCLK, at this moment added inner sense data RD (3) just becomes latch mode, and internal data DD ' can be very long with respect to the retention time of the decline of output permission signal OEM.Because signal OEMFS specific output permission signal OEM is 1 clock period forward, even internal data DD ' allows the time that the is provided with tS of signal OEM to increase greatly with respect to output, the retention time tH of inside sense data DD ' when output allows signal OEM inactivation can be set at very long, thereby has prevented the output of invalid data.

Except structure shown in Figure 20, also can adopt such structure, promptly constitute the prime amplifier that the afterbody that makes at sensing circuit 908 drives inner sense data line and have latch function.In this case, also can use apply precharge when instruction with prime amplifier reset, structure that inner sense data bus is pre-charged to predetermined magnitude of voltage carries out, the structure that latchs shown in Figure 20 only is an example, and this transfer circuit 10 also can be included in the sensing circuit 908.Also have, as long as the structure that the final data of burst length is latched, any structure can adopt.

As mentioned above, according to an embodiment of the present invention 6, because the generation that stops to export all internal clock signals according to internal data shielding indication, so, when data output shielding, can prevent the output of invalid data reliably.Particularly, by the long final data of latch pulse string, can be provided with time and retention time all set long enough, can prevent the output of invalid data reliably.

As mentioned above, according to the present invention, when not allowing data output to change, control is to the generation of the internal clock signal that internal data transfer is applied to the gate circuit of output buffers circuit, make the data of determining state always be added on the output buffers circuit, thereby can prevent the generation of invalid data effectively.

Claims

1. semiconductor storage is characterized in that:

Comprise:

A plurality of storage unit are used for storing data respectively;

Gate circuit when the data readout mode, passes through the data of the select storage unit in above-mentioned a plurality of storage unit;

Output circuit when data output allows, is exported the data that apply from above-mentioned gate circuit to the outside; And

Output control circuit makes the synchronously conducting of above-mentioned gate circuit and clock signal;

Above-mentioned output control circuit includes in response to exporting unallowed transfer to data, irrespectively making above-mentioned gate circuit become the unit of nonconducting state with above-mentioned clock signal.

2. the described semiconductor storage of claim 1 is characterized in that:

Above-mentioned output control circuit comprises:

Make data output allow the unit of signal activation in response to specifying above-mentioned data readout mode data designated to read indication;

Receive the output of above-mentioned data allow signal and above-mentioned clock signal, when above-mentioned data output allows signal to be in state of activation and above-mentioned clock signal synchronously make above-mentioned gate circuit become the steering logic of conducting state.

3. the described semiconductor storage of claim 1 is characterized in that:

Above-mentioned output control circuit comprises:

In response to the data sense order of specifying above-mentioned data readout mode, make and read the unit that allows signal activation;

Above-mentioned the 1st delay circuit that allows the signal delay stipulated time of reading;

Receive the output signal of above-mentioned the 1st delay circuit and above-mentioned clock signal, when the above-mentioned output signal of above-mentioned the 1st delay circuit is in state of activation and above-mentioned clock signal synchronously make the steering logic of above-mentioned gate circuit conducting; And

The 2nd delay circuit that the output signal of above-mentioned the 1st delay circuit continues to be added on the above-mentioned output circuit behind the delay stipulated time, handle is exported to the outside from the data of above-mentioned gate circuit on above-mentioned output circuit when above-mentioned output signal is in state of activation.

4. the described semiconductor storage of claim 3, it is characterized in that: above-mentioned output control circuit also comprises:

In response to the activation of the shielding indication of the data of the shielding select storage unit that comes from above-mentioned output circuit output, make the unit that allows the signal inactivation of reading that is added on above-mentioned the 1st delay circuit.

5. the described semiconductor storage of claim 1 is characterized in that:

Above-mentioned output control circuit comprises

Read indication, make and read the unit that allows signal activation in response to the data of specifying above-mentioned data readout mode;

Delay cell, postpone the above-mentioned permission signal of reading, produce the 1st inhibit signal, have than long the 2nd time delay above-mentioned the 1st time delay and the 3rd inhibit signal that synchronously is added to the 2nd inhibit signal on the above-mentioned output circuit and has the 3rd time delay longer with above-mentioned clock signal than the 2nd time delay with the 1st time delay;

Steering logic receives above-mentioned the 1st, the 3rd inhibit signal and above-mentioned clock signal, during above-mentioned the 1st, the 3rd inhibit signal is in state of activation, synchronously makes above-mentioned gate circuit become conducting state with above-mentioned clock signal.

6. the described semiconductor storage of claim 5 is characterized in that:

Above-mentioned output control circuit also comprises:

In response to indicating, make the unit that allows the signal inactivation of reading that is applied to above-mentioned delay cell to the shielding of external data output from the selected storage unit of the shielding of above-mentioned output circuit.

7. the described semiconductor storage of claim 1 is characterized in that:

Above-mentioned output control circuit comprises:

Read indication, produce and read the unit that allows signal in response to the data of specifying above-mentioned data readout mode;

Delay cell, postpone the above-mentioned permission signal of reading, produce have postpone read output signal the 1st of the 1st time delay, have than the 1st time delay long the 2nd postpone read output signal and with synchronous the 2nd the postponing read output signal and have the 3rd readout delay circuit that postpone read output signal longer of above-mentioned clock signal than the slow time of the 2nd place;

In response to from the shielding indication of the output of the shielding select storage unit data of above-mentioned output circuit, produce the unit of internal shield indicator signal;

Receive above-mentioned internal shield indicator signal, produce have respectively above-mentioned the 1st,, the 1st, the 2nd and the 3rd shielding delay cell that postpones the shielding indicator signal of the 2nd and the 3rd time delay;

Receiving above-mentioned the 1st readout delay signal, above-mentioned the 1st delay shielding indicator signal and above-mentioned clock signal, postponing read output signal the above-mentioned the 1st is the steering logic that synchronously makes above-mentioned gate circuit conducting during state of activation and the above-mentioned the 1st postpones the shielding indicator signal to be unactivated state with above-mentioned clock signal.

8. the described semiconductor storage of claim 7 is characterized in that:

Above-mentioned output circuit comprises

In response to the above-mentioned the 2nd state of activation and the above-mentioned the 2nd that postpones read output signal postpone the unactivated state of shielding indicator signal, the unit of select storage unit data from above-mentioned gate circuit to outside output that apply from.

9. the described semiconductor storage of claim 7 is characterized in that, also comprises

Receive the above-mentioned the 3rd postpone that read output signal and the above-mentioned the 3rd postpones the shielding indicator signal, the unactivated state that postpones the shielding indicator signal in response to the above-mentioned the 3rd state of activation and the above-mentioned the 3rd that postpones read output signal is added to the output signal of above-mentioned steering logic on the above-mentioned gate circuit, makes the output signal of above-mentioned steering logic in addition invalid, makes second steering logic of above-mentioned gate circuit conducting.

10. the described semiconductor storage of claim 1 is characterized in that:

Comprise:

Response is specified the data of above-mentioned data readout mode to read indication and is produced the unit of reading the permission signal;

Postpone the above-mentioned unit that allows signal, produces output permission signal of reading;

In response to from the shielding indication of the data output of the shielding select storage unit of above-mentioned output circuit, produce the unit of internal shield indicator signal;

Receive above-mentioned internal shield indicator signal, above-mentioned internal shield indicator signal produced the 1st and the 2nd delay circuit that postpones the shielding indicator signal of the 2nd time delay that has the 1st time delay and Bi Di length 1 time delay respectively;

Receive the above-mentioned the 1st postpone shielding indicator signal and above-mentioned clock signal, when the above-mentioned the 1st postpones shielding indicator signal inactivation and above-mentioned clock signal synchronously make the steering logic of above-mentioned gate circuit conducting;

Above-mentioned output circuit allows the state of activation and the above-mentioned the 2nd of signal to postpone the unactivated state of shielding indicator signal in response to above-mentioned output, from the data that foregoing circuit applies, makes data in addition become output high impedance state to outside output.

11. the described semiconductor storage of claim 10 is characterized in that:

Above-mentioned output allows the signal generation unit to comprise with above-mentioned clock signal synchronization action, read the clock period of the regulation number that allows the above-mentioned clock signal of signal delay and produce the unit that above-mentioned output allows signal above-mentioned;

Above-mentioned delay circuit comprises and above-mentioned internal shield indicator signal being postponed and 1 clock period and produce the above-mentioned the 1st and the 2nd unit that postpones the shielding indicator signal half of above-mentioned clock signal.

12. the described semiconductor storage of claim 1 is characterized in that:

Also comprise

The prime setting of above-mentioned gate circuit, latch the data latches that is added to the data on the gate circuit.

13. the described semiconductor storage of claim 1 is characterized in that:

Above-mentioned semiconductor storage and above-mentioned clock signal are carried out the input and output of data synchronously.

14. the described semiconductor storage of claim 1 is characterized in that: above-mentioned output control circuit comprise with than activate above-mentioned output circuit faster sequential make above-mentioned gate circuit become the unit of conducting state.

15. the described semiconductor storage of claim 1 is characterized in that: above-mentioned output control circuit comprises

With than make above-mentioned output circuit inactivation faster sequential make above-mentioned gate circuit become the unit of cut-off state.