CN1224104C

CN1224104C - Non-volatility memory and making technology thereof

Info

Publication number: CN1224104C
Application number: CN 01119624
Authority: CN
Inventors: 周国煜
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2001-05-16
Filing date: 2001-05-16
Publication date: 2005-10-19
Anticipated expiration: 2021-05-16
Also published as: CN1385903A

Abstract

The present invention relates to a nonvolatile memory and a making technology thereof. The nonvolatile memory comprises a semiconductor basal plate, a compound dielectric layer of an oxidizing layer/ a nitride layer/ the oxidizing layer, which is formed on the semiconductor basal plate, a floating gate formed on the compound dielectric layer of the oxidizing layer/the nitride layer/the oxidizing layer and a control gate formed on the floating gate. The making technology is that the compound dielectric layer of the oxidizing layer/the nitride layer/the oxidizing layer is added in a memory structure of an oxidizing film of a traditional floating gate, so simultaneously, the improved memory structure has effects of high reliability and high storage density.

Description

Nonvolatile memory and manufacture craft thereof

Technical field

The present invention relates to a kind of Nonvolatile memory and manufacture craft thereof.

Background technology

The application of Nonvolatile memory (nonvolatile memory) is general day by day, EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) (Electrically Erasable Programmable Read Only Memory) for example, fast storage (Flash memory) etc. promptly is.

See also Fig. 1.The structure of common Nonvolatile memory has floating gate oxide-film (FLOTOX) storage organization, it is to apply one to be enough to make oxide layer to produce the voltage of Fowler-Nordheim (F-N) tunnel effect between control grid 21 and substrate (substrate) 25 basically, by electronics from drain 24 through tunnel oxide layer 26 (tunneling oxide) tunnel to floating grid 22, promote critical voltage, the purpose of (erase) data of erasing to reach.And electronics can be passed tunnel oxide 26 from poly floating grid 22 is drawn onto in the drain electrode 24, to reduce transistorized critical voltage, to reach the purpose that writes data.

See also Fig. 2.Another kind of SONOS non-volatile memories structural principle and above-mentioned close has two layers of oxide layer 74,75 and one deck nitride layer 73 below grid 71.In the time of write-in program (program) data, add a high voltage at grid 71 and wellblock (well) 72,72 attract electrons are to nitride layer (Nitride) 73 from the wellblock, and when erasing (erase), then can be with grid 71 ground connection, grant wellblock 72 (well) high voltage, make hole (holes) inject nitride layer (Nitride) 73 and the electrical effect that neutralizes of electron production.So then can reach the purpose that writes/erase the storage data by changing critical voltage Vt (threshold voltage).

In Nonvolatile memory, the worst memory cell of condition (cell) is played the part of important role usually.As long as it lost efficacy (fail), whole internal memory just lost efficacy.That is to say that as long as have a memory cell its memory time (retention time) or endurance (endurance) not to reach standard, then entire chip (chip) just lost efficacy ahead of time.

Generally speaking, the main cause of FLOTOX memory element inefficacy is the quality of tunnel oxidation layer.If its quality is bad, then can't store charge in the floating gate, will cause the loss of data like this.And the defective of tunnel oxidation layer (defect) often occurs at random, so in order to improve the correctness of storage data, often use the single data of a plurality of FLOTOX memory element stores.

See also Fig. 3.With Q-cell is that example (sees also people such as Fan Ku [41], SEEQ 1988, IEEE's permission (with permission of IEEE), Vancu et al, SEEQ 1998, withpermission of IEEE), an one memory cell is made up of two series connection memory elements 11.Its principle is mainly utilized the differentiation of induction amplifier (sense Amplifier) as dividing potential drop, unless two series component all lost efficacy (fail), not so data are still correct.Though can improve data correctness whereby, but memory cell size (cellsize) is bigger.

And, make it to have the size that can reduce assembly again as the high-reliability degree of Fig. 1 and while how by in conjunction with traditional FLOTOX structure and SONOS structure, be to be concern person of the present invention.

Summary of the invention

The purpose of this invention is to provide a kind of Nonvolatile memory and manufacture craft thereof of improving structure that have, can realize: the broad critical voltage difference (write/erase threshold voltagewindow) that writes/erase is provided; Prolong the memory time and the endurance of non-volatile memory device; Promote reliability and reduce assembly volume; Increase radiation-resistant effect; Manufacture process is close with traditional F LOTOX manufacture craft.

For achieving the above object, Nonvolatile memory according to an aspect of the present invention is characterized in that it comprises: the semiconductor substrate; The composite dielectric layer of one oxide layer/nitride layer/oxide layer (ONO) is to be formed on the described semiconductor substrate; One floating gate is to be formed on the composite dielectric layer of described oxide layer/nitride layer/oxide layer; And a control gate, be to be formed on the described floating gate.

Wherein, described semiconductor substrate is to be the one source pole and the in type substrate that drains, tool one passage (channel), between its source electrode and drain electrode, and described ONO storage organization is formed at promptly that the passage (Channel) of the described source electrode and the in type substrate that drains is gone up and described floating gate between.

First oxide layer of ONO storage organization is to be formed on the described semiconductor substrate, and its nitride layer is to be formed on described first oxide layer, and other second oxide layer then is formed on the described nitride layer.

Can write down a numerical data by injecting some electronics in the ONO storage organization.Certainly, some electronics is the nitride layer that injects the ONO storage organization.And by injecting some holes in ONO storage organization (erase) the described numerical data of can erasing.In like manner, some holes are the nitride layers that inject the ONO storage organization.

Certainly, comprise a dielectric layer between floating grid (floating gate) and the described control grid (control gate).

For achieving the above object, propose a kind of manufacture craft of Nonvolatile memory according to a further aspect of the invention, be characterized in, it comprises the following steps: to provide the semiconductor substrate; The composite dielectric layer that forms one oxide layer/nitride layer/oxide layer (ONO) is on described semiconductor substrate; Form a floating grid on the composite dielectric layer of described oxide layer/nitride layer/oxide layer; And form a control grid on described floating grid.

The present invention is owing to form an ONO composite dielectric layer between semiconductor substrate passage and floating gate, the size of Nonvolatile memory is dwindled and improves reliability.

Description of drawings

Be clearer understanding purpose of the present invention, characteristics and advantage, the present invention is described in detail below in conjunction with accompanying drawing.

Fig. 1 is the structure of existing Nonvolatile memory;

Fig. 2 is the schematic diagram of existing SONOS structure;

Fig. 3 is the schematic diagram of the memory cell of existing two memory elements;

Fig. 4 is the schematic diagram of the present invention's parasitic ONO storage organization in the FLOTOX structure;

Fig. 5 is the circuit diagram of cooperation table one of the present invention and table two;

Fig. 6 (a) to Fig. 6 (e) be the schematic diagram of manufacture craft process of the present invention;

Fig. 7 is the schematic diagram that another kind is applicable to FLOTOX structure of the present invention.

Embodiment

In Fig. 1,, then in the Flotox memory cell, form a SONOS memory cell if oblique line thick oxide layer 23 partly is replaced into oxide layer/nitride layer/oxide layer (ONO) composite dielectric layer (Oxide/Nitride/Oxide).So then can get:

1. broad write/erase critical voltage difference (write/erase threshold voltage window).

2. memory time (retention time) and endurance (endurance) can prolong.

3. increase radiation-resistant effect.

In Fig. 4, ONO composite dielectric layer 31 is formed between semiconductor substrate 25 and the floating grid 22.ONO composite dielectric layer 31 comprises oxide layer 51,53 and nitride layer 52, and it in fact is a storage organization, can inject the mode of nitride layer 52 by electrons/, reaches the purpose that writes/erase data.So, when ONO composite dielectric layer 31 and floating grid 22 are used for storing identical data, can have Fig. 3 advantage on the one hand, improve reliability, also can reach the effect of dwindling assembly volume on the other hand.

If add a step in addition, make the tunnel oxidation layer thickening of source terminal, then its source electrode and consecutive storage unit (adjacent cell) can be shared.Circuit as shown in Figure 5.

Table one is the operating condition of Fig. 5, and shown numerical value only is a reference value, can utilize and adjust coupling ratio (Coupling ratio) change, and be not unalterable.

While can adjust big capacitance oxidization layer (bulk oxide) thickness of ONO composite dielectric layer and the tunnel oxidation layer (tunneling oxide) of floating grid (floating gate) makes its operating voltage (operationvoltage) roughly the same.

The manufacture method of the nonvolatile memory among Fig. 4 is as follows:

(a), at first on semiconductor substrate, form (Oxide/Nitride/Oxide) composite dielectric layer of oxide layer/nitride layer/oxide layer (ONO) as Fig. 6 (a).First oxide layer, 51 thickness are 20-50 , nitride layer 52 be formed at first oxide layer 51 on, then form second oxide layer 53, thick about 50 .

(b), then put mononitride dottle pin (Spacer) 54, and implement ion and implant (implantation) as Fig. 6 (b).

(c), then form a wet oxidation layer 55 (wet oxide) as Fig. 6 (c).

(d) as Fig. 6 (d), then remove nitride dottle pin (Nitride Spacer) 54, and deposition tunnel oxidation layer 56, thick about 80 ~ 150 .

(e), form floating grid 22 at last in regular turn, dielectric layer (dielectric) 57, control gate (control gate) 21 as Fig. 6 (e).

Main characteristics of the present invention is:

One, the thick oxide layer in the traditional F lotox structure partly replaces with the ONO composite dielectric layer.

Two, in addition, use (with the ONO composite dielectric layer, floating gate is write-in program (program) respectively) if utilize suitable wiring, this memory cell to can be used as polymorphic (multi-state).

Three, secondly, the present invention also is applicable to another kind of Flotox structure as shown in Figure 7.In like manner, the flotox structure of Fig. 7 also can in thick oxide layer 23 partly form an ONO composite dielectric layer, can reach improved effect.

What deserves to be mentioned is that in addition the structure of array proposed by the invention (array) is to be one or non-(NOR) memory cell.Listed operation row culture (operation condition) can be adjusted by the thickness or its shape (coupling ratio, coupling ratio) that change tunnel oxidation layer and each layer of ONO composite dielectric layer, is limited.

About the ONO composite dielectric layer, wherein the thickness of tunnel oxidation layer is about 20 ~ 60 , and nitrogen thing layer thickness is about 20 ~ 100 , and the thickness of thick oxide layer is about 20 ~ 500 .

In addition, about the operation of memory cell, also can operate floating gate (floating gate), SONOS structure respectively, for example operation SONOS partly operates floating gate partly more earlier.Its operating voltage of O/N/O (20 /85 /50 ) can change by the thickness that changes nitride layer and thick oxide layer.The operating condition of SONOS and floating gate is shown in table two, table three.

By above-mentioned diagram and explanation as can be known, novelty of the present invention is to form an ONO composite dielectric layer between semiconductor substrate passage and floating gate, and progressive then is by structural change, reaches minification and increases effectiveness such as reliability.

Table one

Operating condition	W1	W2	D1	D2	P-well	S
Operating condition	W1	W2	D1	D2	P-well	S	Erase	7	7	-5	-5	-5	Open
Write (41)	-5	Open	7	Open	7(41) -5(42) Open(43，44)	Open	Erase	7	7	-5	-5	-5	Open
Write (41)	-5	Open	7	Open	7(41) -5(42) Open(43，44)	Open	Read (41)	5	0	S.A.	Open	Open	0

Table two: SONOS operating condition

Operating condition	W	D	S	P-well
Operating condition	W	D	S	P-well	Erase	7	-5	-5	-5
Write	-5	Open	Open	7	Erase	7	-5	-5	-5

Table three: the operating condition of floating grid

Operating condition	W	D	S	P-well
Operating condition	W	D	S	P-well	Erase	7	-5	-5	-5
Write	-5	7	Open	Open	Erase	7	-5	-5	-5

Claims

1. Nonvolatile memory is characterized in that it comprises:

The semiconductor substrate, it has an one source pole and a drain electrode, and is positioned at the passage between described source electrode and described drain electrode;

One storage organization, be formed on the described semiconductor substrate and described drain electrode and described source electrode between described passage on, described storage organization is one oxide layer/nitride layer/oxide layer composite dielectric layer;

One floating gate is to be formed on the described storage organization; And

One control gate is to be formed on the described floating gate.

2. Nonvolatile memory as claimed in claim 1 is characterized in that, described nitride layer be used for injecting some electronics to described storage organization to write down a numerical data.

3. Nonvolatile memory as claimed in claim 1 is characterized in that, described nitride layer be used for injecting described some holes to described storage organization with the numerical data of erasing.

4. Nonvolatile memory as claimed in claim 1 is characterized in that, comprises a dielectric layer between described floating grid and the described control grid.

5. the manufacture craft of a Nonvolatile memory is characterized in that, it comprises the following steps:

The semiconductor substrate is provided; Described semiconductor substrate has an one source pole and a drain electrode, and is positioned at the passage between described source electrode and described drain electrode;

Form a storage organization on the described semiconductor substrate and on the described passage between described drain electrode and described source electrode, described storage organization is one oxide layer/nitride layer/oxide layer composite dielectric layer;

Form a floating grid on the composite dielectric layer of described oxide layer/nitride layer/oxide layer; And

Form a control grid on described floating grid.

6. the manufacture craft of Nonvolatile memory as claimed in claim 5, it is characterized in that, described storage organization by inject some electronics in described nitride layer writing down a numerical data, and by inject some holes in described nitride layer with the described numerical data of erasing.

7. the manufacture craft of Nonvolatile memory as claimed in claim 6 is characterized in that, described storage organization comprises:

One first oxide layer is to be formed on the described semiconductor substrate;

The mononitride layer is to be formed on described first oxide layer; And

One second oxide layer is to be formed on the described nitride layer.

8. the manufacture craft of Nonvolatile memory as claimed in claim 5 is characterized in that, described storage organization be by inject some electronics in described nitride layer to write down a numerical data.

9. the manufacture craft of Nonvolatile memory as claimed in claim 5 is characterized in that, described storage organization also by inject some holes in described storage organization with the described numerical data of erasing.

10. the manufacture craft of Nonvolatile memory as claimed in claim 5 is characterized in that, comprises a dielectric layer between described floating grid and the described control grid.