CN1223031A - Oversampled, noise-shaping, mixed-signal processor - Google Patents
Oversampled, noise-shaping, mixed-signal processor Download PDFInfo
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- CN1223031A CN1223031A CN 97195669 CN97195669A CN1223031A CN 1223031 A CN1223031 A CN 1223031A CN 97195669 CN97195669 CN 97195669 CN 97195669 A CN97195669 A CN 97195669A CN 1223031 A CN1223031 A CN 1223031A
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Abstract
A signal processing circuit is provided which includes a frequency selective network in a feedback loop for noise shaping purposes. A sampling analog-to-digital converter in the feedback loop operates at a sample frequency substantially above the Nyquist frequency. A switching device is driven by the sampling analog-to-digital converter and produces a continuous-time output signal which is continuously monitored by and fed back to the frequency selective network for noise and distortion correction in the feedback loop. State feedback (i.e., digital or sampled) of the output of the analog-to-digital converter may also be employed in combination with the continuous-time feedback of the switching device output.
Description
For example the present invention relates to comprise the over-sampling of ∑-Δ modulation technique, noise shaping signal processing field.Especially, the present invention uses with other signal processing applications for intelligent power a kind of method and apparatus that over-sampling, noise shaping and mixed signal are handled that carries out is provided.The mixed signal is here handled and is referred to continuous time (for example simulation) and discrete time (for example numeral or sampled analog signal) Signal Processing.The present invention has substituted the PWM technology that may adopt in pulse width modulation (PWM) The Application of Technology any.For example, in the described here particular embodiment, the invention provides one and use the over-sampling of revising, the switch power amplifier of noise shaping processor rather than PWM increases efficient, reduces noise and distortion performance.
The market demand of personal computer (PC) that need have multimedia performance is in rapid expansion.The graphics performance of consumer wants processor and improvement faster moves growing complex software application and CD-ROM exercise question.But, only there are processing speed and high-quality video to be nowhere near for many application.For example, for video-game, the market demand to the sound of big volume and stereo-quality is just arranged.In addition, for the surrounding sound effective value of regenerating truly, need Hi-Fi sound reproduction.
General 16 bit architectures that result from 1-2 watt of power output that adopt of present PC sound card.If the audio power that consumer wants is higher, multimedia PC generally need comprise the accessory speakers by the linear power amplifier (for example, AB class) of independent power source power supply.General A category-B audio frequency amplifier roughly is 60% in the actual efficiency of peak power, but average or rms power output significantly reduces.For example, for 10W
Rms, the efficient of a class ab ammplifier more may be in 20 to 30% scope.Suppose efficient be 25% and the required audio power of each sound channel be 10W
Rms, then need 80W power to drive loud speaker.Suppose that a typical PC only has 200-250W power, show independent power source of needs.
The intrinsic poor efficiency of linear amplifier has caused other method of many solution audio frequency scale-up problems.For example, owing to compare with linear amplifier, aspect power efficiency, the D class A amplifier A of employing PWM has advantage clearly, and some have adopted the D class A amplifier A in using.But, because some distortion sources comprise the cross modulation distortion; The sideband of sample frequency causes that spectrum folding advances base band; The asymmetry of rising and fall time; Low-Gao and height-low asymmetry that postpones of propagating; (being the dead band) distorts " to disconnect (break before make) before making "; Power surge; With the fact of the distortion performance that causes owing to low over-sampling rate with the voiced band marked change, the magnitude of the signal power that present PWM technology is realized and the ratio of THD+ noise only is 40-60dB.Because pulse rise time and become the pith in sampling clock cycle fall time and the distortion of other type plays a major role, by, for example increase the method that sample frequency (sideband of will sampling thus is away from base band) solves these problems and be restricted.As a result, than being at least the medium to senior voice applications of 90dB, present PWM technology can not provide enough sound qualities for noise suppressed.
In order to satisfy this demand, there have been some to adopt over-sampling, noise shaping modulator, particularly the method for sigma-delta modulator designs the switch audio frequency amplifier, and the characteristic of sigma-delta modulator is seen " using the 12V ∑-Δ D class A amplifier A of 5VCMOS technology " pp.559-562 (IEEE 1995 Custom Integrated CircuitsConference) that H.Ballan and M.Declercq deliver.But, as will be described, comprise that in a sigma-delta modulator ring power CMOS transistor will produce the problem that other hinders the amplifier overall performance.Fig. 1 has described a standard single order sigma-delta modulator 100.Integrator 102 and a sample rate are that the comparator 104 of two level quantizer of fs is connected.The output of comparator 104 feeds back to integrator 102 through digital to analog converter (D/A) 106 and adder 108.This feedback forces the mean value of quantized output signal and the mean value that inputs to the signal of modulator 100 to be consistent.Any difference between quantification output and the modulator input all is integrated device 102 accumulations and is finally corrected.For the single order sigma-delta modulator, over-sampling rate (OSR) whenever doubles once, because the noise in the signal band that quantization error causes just reduces roughly 9dB.OSR is defined as f
s/ 2f
o, 2f wherein
oBe Nyquist rate, i.e. baseband signal bandwidth f
oTwice.For the second order sigma-delta modulator, owing to increased OSR in the same manner, this noise has reduced roughly 15dB (9dB+6dB).But, as mentioned above,, increase OSR because the rise time and the fall time of output for the sampling period are very big, promptly increase f
sThe method of improving noise has a finally restriction.See " the over-sampling ∑-Δ data converter " that Candy and Temes write, pp.1-25 (IEEE Press, 1992) about discussing fully of ∑-Δ modulation technique.
As described above, in a standard sigma-delta modulator, add power MOS transistor and be attended by other performance issue.For voice applications, power MOS transistor drives lower impedance, so must make output impedance less than 1 ohm for the whole efficiency that obtains.As a result, this transistorized switching characteristic is slower, and departs from perfect switch characteristic as shown in Figure 2, produces thus to be typically-60dB or higher distortion.The switching characteristic of power MOS transistor is a p channel mosfet and n channel mosfet its typical switching characteristic when forming the push-pull type structure of knowing among Fig. 2.Because the standard sigma-delta modulator uses numeral or state feedback (being D/A106 among Fig. 1), integrator stage can not be seen the asymmetric edge of power transistor output.So because unique state feedback, the standard sigma-delta modulator can not be corrected the distortion that power MOS transistor causes.
In addition, present sigma-delta modulator uses sampling integrator, and the power transistor of conversion is not exported feed back to integrator stage and do not had much effects simply.This is because sampling integrator has the problem of obscuring with high frequency distortion.
In addition, the delay that power MOS transistor level causes makes feedback very uncorrelated with input, further weakens the correction function of feedback.Further, the additional delay of a power MOS transistor level can have a negative impact to the stability of circuit.In brief, the improvement of using standard ∑-any reduction noise that Δ modulation is obtained is offset by power MOS transistor and the caused distortion of associated drives level and is become not remarkable.
Look back the discussion of front, clearly need the power amplifier of the low distortion of a high efficiency to be used for audio frequency and multimedia application.
The present invention uses for intelligent power and many other signal processing applications provide an over-sampling, noise shaping mixed-signal processor.As above-mentioned, processor of the present invention can be used for substituting the PWM technology of the application of using PWM.This comprises that for example motor control is used, and power factor is corrected, switching regulator, and the mode of resonance switch, the uninterruptible power source, or the like; Many potential application.So,, should be appreciated that the present invention can be used for many different application through optimization although only described embodiment here.
According to a special implementing mode, provide one high efficiency and can produce the switch power amplifier of the lower strong output signal of distortion.In order to obtain this result, the present invention at first uses feedback continuous time (comparing with the pure state feedback) from its power switch level output.This will guarantee, when comparing with input, can use all to be included in information in the output, can allow correction over-sampling as described herein like this, and the caused distortion of power MOS transistor of switching stage is handled and corrected to noise shaping modulator.
The second, the present invention provides continuous time feedback in such a way, caused on feedback path, to reduce by power MOS transistor, might the interference base band signal extremely the high frequency distortion of unacceptable degree obscure effect.According to execution mode 1, on feedback path, used a low pass antialiasing filter.According to execution mode 2, used continuous time integrator in the integrator stage that receives the feedback of exporting from the power switch level.According to execution mode 3, for the comparator sample frequency, receive one or more use over-sampling of integrator of feedback continuous time.Each solution provided by the present invention is all united to have used and is fed back compensate for low frequency distortion and some decay continuous time or reduce the device that the high frequency distortion of introducing through feedback path is obscured effect.Should be appreciated that the present invention is not limited only to base-band application, many changes to embodiment as described herein make the present invention can be applied to any frequency band, comprise high frequency power amplifier and a lot of other frequency applications.These changes comprise, for example, use bandpass filtering in feedback path, the integrator that links to each other in the logical structure of band and from the feedforward of the input that outputs to another integrator stage of an integrator stage.
As will be described below, many embodiments of the present invention are used continuous time and state (for example, numeral or quantification) are united the not same order over-sampling that feeds back to different integrator stage, noise shaping processor in a variety of forms.Because the distortion of first integrator level input is the main source of final distortion, later on what in addition can use the pure state feedback.In addition, as described below, even the sub-fraction state feedback can be introduced into the first integrator level, to stablize loop.
Like this, according to the present invention, provide a signal processing circuit that in feedback control loop, comprises the frequency selection network that is used for noise shaping.Sampled analog a to digital quantizer is operated on the sample frequency that roughly is higher than nyquist frequency in the feedback control loop.A switching device is driven by this sampled analog to the digital quantizer in the feedback control loop, and produce one continuous time output signal, and select network in feedback control loop, to carry out noise and distortion is corrected this signal feedback to the frequency.In more detailed execution mode, obscure effect and reduced by many modes.
With reference to the remaining part and the accompanying drawing of this explanation, can further understand essence of the present invention and advantage.
Fig. 1 is a standard single order over-sampling, the simplified block diagram of noise shaping modulator;
Fig. 2 is the figure that the typical switching characteristic of a power MOS transistor is compared with the perfect switch characteristic;
Fig. 3 A-D designs according to the present invention, second order correction over-sampling, the simplified block diagram of the various detailed execution modes of noise shaping digital amplifier;
Fig. 4 A and 4B design according to the present invention, second order correction over-sampling, the simplified block diagram of two kinds of detailed execution modes of noise shaping digital amplifier;
Fig. 5 is according to embodiment of the present invention 3 design, and over-sampling is revised on three rank, the noise shaping digital amplifier simplified block diagram;
Fig. 6 is according to embodiment of the present invention 4 designs, and over-sampling, the simplified block diagram of noise shaping digital amplifier are revised in three rank;
Fig. 7 is according to prior art design, the simplified block diagram of traditional B uck pressurizer;
Fig. 8 special implementing mode according to the present invention designs, and uses an over-sampling, the simplified block diagram of the correction Buck pressurizer of noise shaping mixed-signal processor;
Fig. 9 is an over-sampling, noise shaping, the power spectral density plot figure of the power spectral density plot of mixed-signal processor and a typical PWM generator;
One according to the present invention particular embodiment design of Figure 10, a noise shaping, the simplified block diagram of mixed-signal processor; With
Figure 11 is the simplified block diagram of another execution mode of the present invention.
Fig. 3 A-D designs according to the present invention, second order correction over-sampling, four kinds of detailed execution modes 300,340,350 of noise shaping digital amplifier and 360 simplified block diagram.With reference to the common trait of these execution modes, an input signal is introduced into first integrator level 302 through adder 304.The output of first integrator level 302 is introduced into second integral device level 306 through adder 308.One with sample frequency f
sThe clock comparator level 310 of sampling receives the output of second integral device level 306, and the logical signal that is produced is sent to power switch level 312.According to various execution modes, the output of power switch level through low pass antialiasing filter 314 and continuous time gain stage 316 optionally fed back to first integrator level 302 (and 317 feed back to second integral device level 306 through gain stage continuous time among Fig. 3 A-3D).By high frequency distortion was removed the feedback signal from continuous time, low pass filter 314 has reduced the high frequency distortion of switching stage 312 generations and has obscured effect.The gain level of gain stage 316 and 317 is set like this, so that integrator stage is operated in their dynamic ranges with interior optimal level.This feedback signal permission continuous time integrator is seen the actual rising edge and the trailing edge of output signal, and compensates them.
Input for amplifier is not the application of a baseband signal, antialiasing filter 314 may comprise the band pass filter that has with the matched cut-off frequency of input signal frequency band, and in integrator 302 and 306 each by the logical equivalence of a band for example a resonator substitute.According to other execution mode, integrator 302 and 306 can be configured to be tuned to and be fit to frequency band to obtain the band general integral device of same effect.In other words, the principle of execution mode as described herein not only can be used in the logical application of band, and can be used in any required frequency band.For example, over-sampling of the present invention, noise shaping, mixed-signal processor can be used for realizing the power amplifier of the 900Mhz of cellular radio, and potential is that owing to increased the efficient of amplifier, the service time of telephone cells can be more than twice.
According to the various execution modes among Fig. 3 A-3D, the output of comparator stage 310 also is fed to integrator stage through D/ A converter 318 and 319, feeds back so that above-mentioned state feedback and continuous time to be provided.In the amplifier 300 of Fig. 3 A, only continuous time, feedback signal was provided to integrator.In the amplifier 340 of Fig. 3 B, continuous time, feedback only was provided to integrator 302, and state feedback is provided to integrator 306.In the amplifier 350 of Fig. 3 C, pure state feedback is provided to integrator 306, and continuously and the combination of state feedback be provided to integrator 302 through adder 324, the loop unsteadiness of being introduced with the delay that compensates low pass filter 314.At last, in the amplifier 360 of Fig. 3 D, combination continuous and state feedback is provided respectively to integrator 302 and 306 through adder 324 and 326.Should be appreciated that various combinations continuous and state can be applied to the not integrator stage of same order circuit, and can not depart from scope of the present invention.
Fig. 4 A and 4B are that over-sampling is revised on two rank of the design according to the present invention, two execution modes 400 of noise shaping digital amplifier and 440 simplified block diagram.With reference to the common trait of these two execution modes, an input signal is introduced into a first integrator level 402 through adder 404.The output of first integrator level 402 is introduced into second integral device level 406 through adder 408.One with sample frequency f
sThe clock comparator level 410 of sampling receives the output of second integral device level 406, and the logical signal that is produced is sent to power switch level 412.Output continuous time of power switch level through adder 404 and continuous time gain stage 416 be fed to first integrator level 402.In the amplifier 400 of Fig. 4 A,, provide continuous feedback to second integral device level 406 through continuous time gain stage 417 and adder 408.Alternatively, in the amplifier 440 of Fig. 4 B,, provide the state feedback of exporting from comparator 410 to second integral device level 406 through D/A converter 418 and adder 408.
Because integrator stage 402 and 406 comprises intrinsic can receive low frequency and suppress the continuous time integrator of high frequency, not use an antialiasing noise filter continuous time in the amplifier 400 and 440 in the feedback path.This has eliminated the above-mentioned problem of obscuring.According to other detailed execution mode, because the error originated from input of first integrator level is the main source of final distortion, only the first integrator level is a continuous time integrator.Integrator stage subsequently can be used sampling integrator, and can use or not have the state of antialiasing noise filter and/or continuous time to feed back.
According to other detailed execution mode of amplifier 400 and 440, because integrator stage 402 and 406 comprises sampling integrator, and sampling integrator is with respect to comparator sample frequency f
sBe over-sampling, can reduce high frequency thus and obscure (folding) noise, so in feedback path, do not use an antialiasing noise filter.
Fig. 5 revises over-sampling, the simplified block diagram of noise shaping digital amplifier 500 according to embodiment of the present invention 3 designs, three rank.An input signal is introduced into first integrator level 502 through adder 504.The output of first integrator level 502 is introduced into second integral device level 506, and then from being introduced into third integral device level 509 through adder 508 here.One with sample frequency f
sThe clock comparator level 510 of sampling receives the output of third integral device level 509, and the logical signal that is produced is sent to power switch level 512.Output continuous time of power switch level 512 through low pass antialiasing filter 514 and continuous time gain stage 516 and 517 (through adder 524 and 504) be fed to first integrator level 502, (through adder 526 and 508) is fed to third integral device level 509.Process D/A converter and attenuation grade 518 and 519 outputs from comparator 510 provide state feedback.This state feedback is in adder 524 and 526 places and the combination mutually of feedback continuous time, and then provided respectively to first and third integral device level 502 and 509.Provide forward path from the output of first integrator level 502 to adder 508, this has simulated the feedback of 506 inputs from feedback path to second integral device level.This forward path also is used to improve the dynamic range of this integrator stage.Because amplifier 500 has used sampling integrator (for example, switched-capacitor integrator), reduce and obscure noise effects so in the continuous time feedback path, insert low pass filter 514 as mentioned above.In a more detailed execution mode, the input of dither is provided to the input of comparator 510 through adder 528, by it, can the pull-in frequency shaping, at random or pseudo noise eliminate audio frequency.
Fig. 6 revises over-sampling, the simplified block diagram of noise shaping digital amplifier 600 according to embodiment of the present invention 4 designs, three rank.An input signal is introduced into first integrator level 602 through adder 604.The output of first integrator level 602 is introduced into second integral device level 606 through adder 608, and then from being introduced into third integral device level 609 here.One with sample frequency f
sThe clock comparator level 610 of sampling receives the output of third integral device level 609, and the logical signal that is produced is sent to power switch level 612.Output continuous time of power switch level 612 through adder 604 and continuous time gain stage 616 be fed to first integrator level 602.Because the feedback path to the first integrator level comprises a continuous time integrator, so this feedback path does not need the antialiasing noise filter.Also pass through gain stage 617, low pass antialiasing noise filter 614 and adder 608 to third integral device level 609 provide continuous time feedback.Because the feedback path to third integral device level 609 has comprised a sampling integrator, so in this feedback path, insert low pass filter 614.As described in Fig. 5 execution mode, provide forward path from the output of first integrator level 602 to adder 608, this has simulated the feedbacks of 606 inputs from feedback path to second integral device level.This forward path has also increased overall dynamic range.
Though describe and specify the present invention with reference to its detailed execution mode, those of ordinary skill in the art will understand that, aforementioned change and other change can be made in form and details, and scope and spirit of the present invention can be do not departed from.For example, as above-mentioned, can use the not over-sampling of same order, the noise shaping structure.In addition, different integrator stage can be used the various combination of continuous time and state feedback.Can also use filter, gain, the high frequency distortion that the various combination of continuous time integrator and over-sampling integrator reduces in the feedback path is obscured noise effects.Also have a bit very important, should be noted that promptly the logical implementation of band of above-mentioned execution mode can realize.
Be to be further noted that and the invention is not restricted to the treatment of simulated input.That is, only need input interface is changed slightly, just can construct different execution mode of the present invention and handle 1 digital bit input (Figure 11 is described as reference).For example, over-sampling of the present invention, noise shaping, mixed-signal processor just can be used for digital power and amplify application, handle the 1 digital bit input from each provenance.
In addition, the switch power amplification sector only is one of adaptable many fields of the present invention.As above-mentioned, in that almost each uses PWM The Application of Technology, for example motor control is used, and power factor is corrected, switching regulator, and mode of resonance switchable power source or the like all can use the present invention to substitute the PWM technology in using.Fig. 7 is the simplified block diagram of a traditional B uck pressurizer 700, this Buck pressurizer be one know from a DC source (V who does not have voltage stabilizing
UNREG) provide voltage stabilizing DC source (V to a load 702
REG) switching regulator.V
UNREGThrough coming a MOSFET708 of switch to be provided to a low pass LC filter that comprises inductance 704 and electric capacity 706 by a PWM generator 710.During the typical case used, inductance 704 spans were 50-200 microhenrys; The span of electric capacity 706 is 100-2000 microfarads.The value of electric capacity 706 depends on the driving force of required load and special ripple demand.By reverse recovery diodes 712, be typically a Schottky diode, discharge path is provided.A resistor network that comprises resistance 714 and 716 provides the rectification VD to an error-detector circuit 718, this error-detector circuit 718 be basically one with direct voltage of voltage regulation and a reference voltage V
REFMutual differential amplifier relatively.The output of this error-detector circuit 718 drives PWN generator 710, and according to this detection and V
REFBetween error regulate duty ratio.That is, forced down if detect commutated direct current, PWM generator 710 just is added in the duty ratio on the MOSFET708 grid.On the contrary, pressed height if detect commutated direct current, PWM generator 710 just reduces this duty ratio.
Fig. 8 is according to a detailed execution mode design of the present invention, over-sampling of use, noise shaping, the correction Buck pressurizer 800 of mixed-signal processor 820.Except PWM generator 710 and error-detector circuit 718 are substituted by processor 820 and error amplifier 822 and beyond feedback introduced from the output of MOSFET808 through resistance 824 and 826, the design class of pressurizer 800 was similar to the pressurizer 700 of Fig. 7.Processor 820 can be by above-mentioned with reference to figure 3A-D, 4A, 4B, 5 and 6 or come like configurations below with reference to any one execution mode that Figure 10 describes.Load 802, inductance 804, electric capacity 806, MOSFET808, diode 812 and resistance 814 and 816 basically with Fig. 7 in the parts of corresponding label identical functions is arranged.
When substituting the PWM technology with mixed-signal processor of the present invention, some advantages can be arranged, this can understand with reference to figure 9.Fig. 9 is an over-sampling, noise shaping, the power spectral density plot 900 of mixed-signal processor and the power spectral density plot 902 of a typical PWM generator.As shown in the figure, for PWM generator, most of signal power is positioned at f
ClkIn the narrow band on every side.On the contrary, use identical MOS technology, processor of the present invention can be operated on the sample frequency that substantially exceeds similar PWM generator frequency.This is to be subjected to variable pulse width to limit this fact by the sample frequency that PWM uses to cause.That is, this is because in order to modulate, must provide a scope between narrow and broad pulse, so the sample frequency of PWM is restricted.Determined minimum pulse width and clock cycle decision maximum pulse the switching time of MOSFET.This is for the present invention who does not use pulse width modulation, and this restriction is a problem of course not.Like this, relevant with the selection of sample frequency, in frequency f
ClkIn the frequency band on every side, the noise power of the processor of design is very low with the amplitude that frequency increases according to the present invention.
But,, can in pressurizer 800, use time realization associated advantages of the present invention, because the size of inductance 804 and electric capacity 806 has reduced if output can be tolerated more noise.For example, can tolerate the ripple of the equal number that pressurizer 700 is introduced if use the application of pressurizer 800, the bandwidth that can increase pressurizer 800LC filter reaches the identical noise energy of noise energy quantity that produces with pressurizer 700LC filter, and promptly one or two size reduces in inductance 804 and the electric capacity 806.Like this, the increase of noise energy can be less by having, the advantage that obtained of light LC parts comes balance.In addition, owing to have less and lighter LC parts, pressurizer 800 can adapt to the variation of load more quickly such as traditional B uck pressurizer shown in Figure 7, thereby pressurizer 800 can have better dynamic load to regulate.
Compare with the PWM pressurizer of Fig. 7, another advantage of revising Buck pressurizer 800 is relevant with transformation (transition) number of MOSFET input.Using for PWM, is pulse duration decision voltage stabilizing point.Like this, for a given sampling rate f
Clk, 2f is arranged
ClkIndividual transformation.But,, only when needs, just change for pressurizer 800.This means that for identical sample frequency, number of transitions can be much smaller than 2
Fclk
For the execution mode in many various application, can represent the present invention by the signal processor 1000 of Figure 10.In some embodiments, frequency is selected the integrator of network 1002 corresponding to Fig. 3-6, but also may comprise many dissimilar circuit, comprises for example one or more resonator stages.Sampled analog is to the output that 1012 receptions come automatic network 1002 through adder of numeral (A/D) transducer 1004, then with frequency f
sSampling and be sent to switching device 1006.A/D converter 1004 and switching device 1006 are general respectively corresponding to comparator among Fig. 3-6 and power switch level.Should be appreciated that, can realize in these features each with many modes.For example, A/D converter 1004 can be one two level quantizer or a n level quantizer.In addition, switching device 1006 can comprise a single transistor or a power switch network.Output continuous time of switching device 1006 feeds back to the input of network 1002 through feedback device 1008 with through adder 1010 then.Feed back the various distortion effects that reduce or avoid switching device 1006 outputs place continuous time as describing with reference to above-mentioned detailed execution mode, using.For the pull-in frequency shaping, at random, perhaps pseudo noise is eliminated audio frequency, can provide an optional dither input through adder 1012.Generally, dithering technique and the present invention adapt, and known as those persons skilled in art, can be at over-sampling, and noise shaping, a plurality of points of mixed-signal processor are introduced dithering technique.
Be to be further noted that and the invention is not restricted to the treatment of simulated input.That is, only need input interface is done to revise slightly, just can construct a plurality of execution mode of the present invention and handle the numeral input.For example, in digital power amplification is as shown in figure 11 used, a digital sigma-delta modulator 1100 receives one 16 digital bit input (after module 1101 is carried out suitable interpolation/raising sampling number), and this 16 digital bit input is converted to individual bit in the output of modulator 1100.Should be appreciated that modulator 1100 can be a numeral, over-sampling, any in the noise shaping processor, required interpolation/raising sampling number (module 1101) can realize according to many technology of knowing.Modulator 1102 is the designs according to the present invention, receives the mixed-signal processor from the individual bit input of modulator 1100, and carries out aforesaid power amplification.Modulator 1102 is corrected the distortion relevant with power switch, otherwise, if being directly inputted into the power switch level, 1 bit signal just will introduce this distortion.If mixed-signal processor 1102 neither one synchronised clocks can use a phase-locked loop to come recovered clock.Alternatively, if mixed-signal processor 1102 has the antialiasing noise characteristic, continuous time integrator for example, it can asynchronous working.
Principle with reference to Figure 11 discussion can also be used in the content of ∑-Δ digital-to-analog conversion.Aforementioned digital-to-analog method has generally used a reception from sigma-delta modulator or some other numerals, over-sampling, and 1 bit that the noise shaping processor comes is imported, and this 1 bit input signal is converted to the integrator of an analog signal.But part is the open loop feature owing to integrator stage, and analog signal is relatively more responsive to many simulated defects.Mixed-signal processor of the present invention can be used for substituting the analogue integrator level, corrects these defectives.
So, because signal processing technology as described herein and device can be used for wide like this application, the application of for example any use PWM, scope of the present invention should not be limited to the execution mode of describing in the detailed description, and should be decided by appended claims.
Claims (44)
1. over-sampling, noise shaping, mixed-signal processor comprises:
At least one integrator stage in feedback control loop, described at least one integrator stage has an input;
A sample stage in the described feedback control loop, this sample stage links to each other with described at least one integrator stage, and is used for analog signal of a sample frequency sampling;
A switching stage in the described feedback control loop, described switching stage links to each other with described sample stage, and an input and an output are arranged; With
One continuous time feedback path, described continuous time, feedback path was from the input that exports described at least one integrator stage to of described switching stage, form described feedback control loop thus, described feedback control loop also comprises and reduces the device of obscuring noise effects with described sample frequency accordingly.
2. over-sampling as claimed in claim 1, noise shaping, mixed-signal processor, wherein said processor comprises a plurality of integrator stage, described processor further comprises in the described a plurality of integrator stage of inputing to of described switching stage the state feedback path of at least one.
3. over-sampling as claimed in claim 2, noise shaping, mixed-signal processor, further comprise at least one and the described adder that continuous time, feedback path linked to each other with described state feedback path, so that at least one provides the combination of continuous time feedback and state feedback in described a plurality of integrator stage.
4. over-sampling as claimed in claim 1, noise shaping, mixed-signal processor, wherein said minimizing device comprise an antialiasing noise filter that is arranged in described continuous time of feedback path.
5. over-sampling as claimed in claim 1, noise shaping, mixed-signal processor, wherein said processor comprises a plurality of integrator stage, at least one comprises a continuous time integrator in these a plurality of integrator stage.
6. over-sampling as claimed in claim 1, noise shaping, mixed-signal processor, wherein said processor comprises a plurality of integrator stage, at least one comprises a sampling integrator in these a plurality of integrator stage.
7. over-sampling as claimed in claim 6, noise shaping, mixed-signal processor, wherein said sampling integrator are over-samplings for described sample frequency.
8. over-sampling as claimed in claim 1, noise shaping, mixed-signal processor further comprises a device of introducing a high-frequency vibration signal, to eliminate audio frequency.
9. switch power amplifier comprises:
A first integrator level, described first integrator level is arranged in a feedback control loop, and an input is arranged;
A second integral device level, described second integral device level is arranged in described feedback control loop, links to each other with described first integrator level, and an input is arranged;
A comparator stage, described comparator stage is arranged in described feedback control loop, links to each other with described second integral device level;
A power switch level, described power switch level is arranged in described feedback control loop, and has an input and an output, and the input of described power switch level links to each other with described comparator stage; With
One continuous time feedback path, at least one the input in described first and second integrator stage of exporting to of described power switch level of described continuous time of feedback path, form feedback control loop thus, described feedback control loop also comprises and reduces the device of obscuring noise effects with a sample frequency accordingly.
10. switch power amplifier as claimed in claim 9 further comprises a state feedback path of the input of at least one in described first and second integrator stage of inputing to of described power switch level.
11. switch power amplifier as claim 10, further comprise one with described continuous time of feedback path, described state feedback path, with the adder that the input of at least one in described first and second integrator stage links to each other, described adder be used to provide continuous time feedback and the combination of state feedback.
12. switch power amplifier as claimed in claim 9, wherein said minimizing device comprise an antialiasing noise filter that is arranged in described continuous time of feedback path.
13. switch power amplifier as claimed in claim 9, wherein said power switch level comprises a plurality of DMOS transistors.
14. as the switch power amplifier of claim 13, the structure of wherein said a plurality of DMOS amplifiers is a H-bridge shape.
15. switch power amplifier as claimed in claim 9 further comprises the device of introducing a high-frequency vibration signal, to eliminate audio frequency.
16. a switch power amplifier comprises:
A first integrator level, described first integrator level is arranged in a feedback control loop, and an input is arranged;
A second integral device level, described second integral device level is arranged in described feedback control loop, links to each other with described first integrator level, and an input is arranged;
A third integral device level, described third integral device level is arranged in described feedback control loop, links to each other with described second integral device level, and an input is arranged;
A comparator stage, described comparator stage is arranged in described feedback control loop, links to each other with described third integral device level;
A power switch level, described power switch level is arranged in described feedback control loop, and has an input and an output, and the input of described power switch level links to each other with described comparator stage; With
One continuous time feedback path, described continuous time, feedback path was from exporting to of described power switch level described first, second and third integral device level at least one input, form feedback control loop thus, described feedback control loop also comprises and reduces the device of obscuring noise effects with a sample frequency accordingly.
17. the switch power amplifier as claim 16 further comprises:
An adder is with described continuous time of feedback path and described the first, the second link to each other with the input of at least one in the third integral device level;
A state feedback path is from the described adder of inputing to of described power switch level;
Wherein said adder to described the first, the second and third integral device level at least one input provide continuous time feedback and the combination of state feedback.
18. as the switch power amplifier of claim 16, wherein said minimizing device comprises an antialiasing noise filter that is arranged in described continuous time of feedback path.
19. as the switch power amplifier of claim 16, wherein said power switch level comprises a plurality of DMOS transistors.
20. as the switch power amplifier of claim 19, the structure of wherein said a plurality of DMOS amplifiers is a H-bridge shape.
21. as the switch power amplifier of claim 16, further comprise the device of introducing a high-frequency vibration signal, to eliminate audio frequency.
22. a signal processing method comprises step:
An input signal is introduced a frequency select network, produce a frequency thus and select signal;
Select signal with sample described frequency of a sample frequency, produce a sampled signal thus;
The described sampled signal of switch, produce thus one continuous time output signal; With
With described continuous time output signal feed back to described frequency and select network, produce a noise shaping signal thus.
23. as the method for claim 22, wherein said introducing step is carried out by at least one integrator stage, described method further comprises described sampled signal is fed back to step to described at least one integrator stage.
24., further comprise step as the method for claim 23:
Make up described continuous time of output signal and described sampled signal, produce the feedback signal of a combination thus; With
Described combination feedback signal is fed back to described at least one integrator stage.
25., further comprise and reduce the step of obscuring noise effects as the method for claim 22.
26. as the method for claim 25, wherein said minimizing step be included in described continuous time output signal feed back to select network to described frequency before, with an antialiasing noise filter to the described step that continuous time, output signal was carried out filtering.
27. as the method for claim 25, wherein said frequency selects network to comprise at least one sample stage, described minimizing step comprises for described sample frequency, the step of described at least one sample stage of over-sampling.
28. as the method for claim 25, wherein said frequency selects network to comprise at least one integrator stage, described minimizing step comprises the step that the antialiasing noise characteristic is provided to described at least one integrator stage.
29., further comprise to described frequency and select signal to introduce the step of a high-frequency vibration signal, to eliminate audio frequency as the method for claim 22.
30. as the method for claim 22, wherein said input signal comprises an analog signal.
31. as the method for claim 22, wherein said input signal comprises a digital signal.
32. a signal processing circuit comprises:
A frequency is selected network, is arranged in a feedback control loop;
A sampled analog-digital quantizer, described sampled analog-digital quantizer is arranged in described feedback control loop, and is sampled with a sample frequency;
A switching device is coupled into by described sampled analog-digital quantizer and drives, with produce one continuous time output signal; With
Be used for continuous detecting and with described continuous time output signal feed back to the device of selecting network to described frequency, in described feedback control loop, to correct noise and distortion and to carry out noise shaping.
33. as claim 32 signal processing circuit, it is that an analog frequency with antialiasing noise characteristic is selected network that wherein said frequency is selected network.
34. as claim 32 signal processing circuit, it is that an analog frequency selects network and wherein said detection and feedback device to comprise an antialiasing noise filter that wherein said frequency is selected network.
35. as claim 32 signal processing circuit, it is that a sample frequency is selected network that wherein said frequency is selected network.
36. as claim 35 signal processing circuit, it is over-sampling for described sample frequency that wherein said sample frequency is selected network.
37. as claim 35 signal processing circuit, wherein said detection and feedback device comprise an antialiasing noise filter.
38. as claim 32 signal processing circuit, wherein said frequency selects network to comprise at least one integrator stage.
39. as claim 32 signal processing circuit, wherein said frequency selects network to comprise at least one resonator stages.
40. as claim 32 signal processing circuit, wherein said sampled analog-digital quantizer comprises one two level quantizer.
41. as claim 32 signal processing circuit, wherein said sampled analog-digital quantizer comprises a n-level quantizer.
42. as claim 32 signal processing circuit, wherein said frequency selects net structure for receiving an analog signal input.
43. as claim 32 signal processing circuit, wherein said frequency selects net structure for receiving a digital input signals.
44. as claim 32 signal processing circuit, further comprise one second feedback device, select at least one intermediate point the network so that a sampled signal is fed back to described frequency from described sampled analog-digital quantizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97195669 CN1223031A (en) | 1996-06-20 | 1997-05-28 | Oversampled, noise-shaping, mixed-signal processor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/667,925 | 1996-06-20 | ||
| CN 97195669 CN1223031A (en) | 1996-06-20 | 1997-05-28 | Oversampled, noise-shaping, mixed-signal processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1223031A true CN1223031A (en) | 1999-07-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97195669 Pending CN1223031A (en) | 1996-06-20 | 1997-05-28 | Oversampled, noise-shaping, mixed-signal processor |
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| Country | Link |
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| CN (1) | CN1223031A (en) |
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| CN104604127A (en) * | 2012-09-04 | 2015-05-06 | 康塔普罗纳特有限公司 | Sinus-cosinus-modulator (sine-cosine modulator) |
| CN104423409A (en) * | 2013-08-29 | 2015-03-18 | 亚德诺半导体集团 | Closed loop control system, and an amplifier in combination with such a closed loop control system |
| CN104423409B (en) * | 2013-08-29 | 2017-04-12 | 亚德诺半导体集团 | Closed loop control system, and an amplifier in combination with such a closed loop control system |
| US9705465B2 (en) | 2013-08-29 | 2017-07-11 | Analog Devices Global | Closed loop control system, and an amplifier in combination with such a closed loop control system |
| CN104423413A (en) * | 2013-08-30 | 2015-03-18 | 英特尔移动通信有限责任公司 | Controller and a method for controlling a process variable and a power supply circuit comprising a power supply and a controller |
| CN104423413B (en) * | 2013-08-30 | 2017-01-04 | 英特尔德国有限责任公司 | Controller and method for controlling a process variable and power supply circuit comprising a power supply and a controller |
| CN109792235A (en) * | 2016-09-27 | 2019-05-21 | 思睿逻辑国际半导体有限公司 | Amplifier with configurable final output grade |
| CN109792235B (en) * | 2016-09-27 | 2023-11-21 | 思睿逻辑国际半导体有限公司 | Amplifier with configurable final output stage |
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| CN114124203B (en) * | 2021-10-09 | 2023-11-14 | 浙江大学 | Back scattering electric signal detection transmission system |
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