CN1219359C - Automatic gain control circuit and method of direct sequenc spread spectrum receiver - Google Patents
Automatic gain control circuit and method of direct sequenc spread spectrum receiver Download PDFInfo
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- 238000009792 diffusion process Methods 0.000 abstract 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/70735—Code identification
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B2001/70706—Spread spectrum techniques using direct sequence modulation using a code tracking loop, e.g. a delay locked loop
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Abstract
The invention provides an automatic gain control circuit for a direct sequence diffusion spectrum receiver. A discriminating unit (10) generates a discrimination signal error from a received in-phase and orthogonal base band signal, and a multiplying unit (16) simultaneously multiplies the signal error by a first loop gain constant of the signal tracing period and a second different loop gain constant of a signal tracking period. A recursive integrator (22) obtains an integrating AGC value from the multiplied signal error. This automatic gain control circuit can switch a 'high-speed mode' of the signal capturing period and a 'low-speed tracking' mode of the signal tracking period by using two different loop gain values.
Description
Technical field
The present invention relates to be used for the automatic gain control circuit and the method for receiver mobile telephone, particularly in mobile telephone system, use the circuit and the method for direct sequence spread spectrum skill, be used for sending synchronizing signal by the common sparing of frequency spectrum.
Background technology
Mobile telephone system must adopt the scheme that makes mobile radio station find and analyze the wireless signal that usually is the different radio frequency from one or more base stations.The process of this search different base station is called Cell searching.During cell search process, mobile radio station is discerned all base stations, and determines that base station is suitable for connecting with it most.Connect and mean whether begin monitoring exists incoming call or allow the user to breathe out.Cell searching must carry out periodically, because when mobile radio station is mobile, the speech quality that has been identified as best cell may descend, and the wireless signal that forms another sub-district has become better.Based on the replicated plot search, mobile radio station keeps the tabulation of the regular update of all available cell.When the signal quality that forms current available cell had dropped under a certain threshold value, mobile radio station was with old sub-district disconnection and receive a new sub-district, carries out handover in other words.
In most of mobile systems, as W-CDMA, even when calling out, also must periodically carry out Cell searching, so that finish handover, the signal quality in currently used sub-district descends and exists under the situation of another available better sub-district, and ongoing calling does not disconnect yet.
In relying on the mobile system of spread spectrum, as W-CDMA, usually design transmission and receive agreement like this makes mobile radio station temporarily stop to transmit and receive and carry out Cell searching on the different radio channel.Transmission and the instantaneous interruption that receives do not cause any loss of data, because mobile radio station and base station are by the transmission speed compensation of interim increase, so kept average data transfer rate.For example, if the used time of Cell searching accounts for 50% of all up durations, base station and mobile radio station will be launched in remaining 50% time with the twice of normal speed.Yet emission rate can not infinitely increase, because in the interim that increases transmission speed, the logarithm of the ratio between the quantity of transmission error and the speed of increase and the normal speed is directly proportional.Concerning most of application aims, allow a spot of transmission error.Mobile telephone system is more satisfactory as W-CDMA, and the up duration that is used to measure is very limited, because must keep the current whole quality that is connecting.
When mobile radio station when Cell searching interim stops normal transmission and receives, it retunes to different wireless channels.On this different wireless channel, the level of the wireless signal of reception is different from the level of the wireless channel of nominal.Most of mobile station receivers adopt automatic gain control (AGC) system, so that can adjust the signal of varying strength.The AGC system must determine the intensity of received signal, and by this intensity gain in the receiver is set, promptly to higher gain is set than low-signal levels.
In the situation of dual mode receiver, when carrying out Cell searching on the different radio channel or in the different cellular system (as GSM), must in the very short time interval, find the new gain value of search channel, because it is very limited to be used for the up duration of Cell searching, be several W-CDMA time slots basically.In this case, need automatic gain control function to make most scouting intervals be used for signal measurement and obtain fast enough.Yet the speed automatic gain control circuit of prior art is not very stable, when receiver is connected to single W-CDMA sub-district, can not satisfy the use of signal trace, and selects for use slowly operation to make the bit error rate (BER) optimization.
Summary of the invention
The automatic gain control circuit and the method that the purpose of this invention is to provide a kind of W-CDMA of being used for or other Receiver of Direct-sequence Spread Spectrum, its improvement or overcome one or more problems of known automatic gain control circuit.
Another object of the present invention provides a kind of automatic gain control circuit and method that is used for Receiver of Direct-sequence Spread Spectrum, and it is best during signal obtains and follows the tracks of.
According to the present invention, an aspect of of the present present invention provides the automatic gain control circuit that is used for Receiver of Direct-sequence Spread Spectrum, comprising:
Recognition device is used for producing the identification signal error from the homophase and the digital orthogonal baseband signal that receive;
The phase quadrupler is used for the identification signal error is multiplied each other with the first loop gain constant during signal obtains and second different loop gain constant during the signal trace; And
The recurrence integrator is used for obtaining from the identification signal error that multiplies each other the AGC value of integration, and wherein, described recurrence integrator comprises:
First register is used for storing an AGC value in search channel operating period;
Second register is used in second different AGC value of nominal channel operating period storage; And
The AGC conversion equipment is used for optionally the first and second current AGC values being loaded in the recurrence integrator respectively when search and nominal channel operation beginning.
According to another aspect of the present invention, a kind of method of automatic control Receiver of Direct-sequence Spread Spectrum gain comprises:
(a) produce the identification signal error from homophase and the digital orthogonal baseband signal that receives;
(b) the identification signal error is multiplied each other with the first loop gain constant during signal obtains and second different loop gain constant during the signal trace;
(c) use recurrence integrator obtains the AGC value of integration from the identification signal error that multiplies each other, wherein, and an AGC value of in first register, using during the memory search channel operation;
Second different AGC value of storage nominal channel operating period use in second register;
Beginning according to search and nominal channel operation alternately is loaded into the recurrence integrator respectively with the first and second current AGC values.
Description of drawings
Describe various features of the present invention below in detail.For ease of understanding the present invention, with reference to having shown that the automatic gain control circuit figure of preferred embodiment is described.Yet, should be appreciated that automatic gain control circuit is not confined to illustrated compression.
In the accompanying drawings:
Fig. 1 illustrates the block diagram of key functional blocks of the baseband module of Receiver of Direct-sequence Spread Spectrum;
Fig. 2 illustrates the block diagram of the automatic gain control circuit of the part baseband module that forms Fig. 1;
Fig. 3 is illustrated in operating period, the time slot map of the signal level on the diverse location of the automatic gain control circuit of Fig. 2.
Embodiment
Refer now to Fig. 1, Fig. 1 illustrates the general baseband module 1 that forms the Receiver of Direct-sequence Spread Spectrum part.Baseband module 1 comprises receiver mould/number (A/D) modular converter 2, automatic gain control (AGC) circuit 3, AGC D/A (D/A) transducer 4, baseband processing unit 5, radio frequency (RF) preamplifier 6, Digital Signal Processing (DSP) and time slot control unit 7.A/D modular converter 2 receives analog in-phase and digital orthogonal baseband signal from the AFE (analog front end) down-converter (not shown) in the receiver, and the I of digital equivalent and Q component are offered agc circuit 3.
Agc circuit 3 is determined receiver gain, and output signal
AGC.WORDOffer AGCD/A conversion module 4, use subsequently, with the gain of the received signal of control analog in-phase and quadrature by the RF module of receiver.Agc circuit 3 additionally is that the control of RF preamplifier 6 produces an output signal
PREAMP ON
Baseband processing unit 5 is carried out from/to the signal reception of the audio-frequency module of receiver and all band spectrum modulation and the demodulation between transmission period.Agc circuit 3 produces output signal
SEARCH WINDOW,
AGC VALIDWith
RSSI, be used to control the operation of baseband processing unit 5.
The operation of AGC calculation block 3 is by DSP and time slot control unit 7, by digital control parameter DECIMATION_FACTOR, REF_LEVEL, HYSTERESIS, GAIN_SLOW, GAIN_FAST, CALIBTATION_DATASET, ACO_GUARD_TIME and ACO_TIMEOUT, and output signal
COMMANDControl.Output signal
RSSIAlso offer DSP and time slot control unit 7 by agc circuit 3.
Fig. 2 has shown that the basic function of agc circuit shown in Figure 13 is fast.Agc circuit 3 comprises recognition unit 43, is used for the homophase and digital orthogonal baseband signal I and the Q generation identification signal error that receive from digitlization.Recognition unit 43 comprises power block 21, is used for (the I according to function P=SQRT
2+ Q
2) digitized inphase of calculating reception and the amplitude P of orthogonal signalling sampling.
According to function, AVG=SUM{P[k] .P[k-1] ... P[k-DECIMATION_FACTOR] } ÷ DECIMATION_FACTOR, average block 22 is carried out the output integration of power block 21 in the time cycle that Control Parameter DECIMATION_FACTOR determines.The homophase of this reception and the sample rate of orthogonal signalling reduce to the sample rate that is suitable for agc circuit 3.According to function AVG_dB=log (AVG) constant, dB piece 23 calculates the logarithm AVG_dB of output signal AVG from average block 22.
The output of dB piece 23 is deducted from the value of Control Parameter REF_LEVEL by subtraction function piece 24, to produce the identification signal error
ERRThen, hysteresis block is 25
ERRSignal and Control Parameter HYSTERESIS compare.If the absolute value of ERR signal is less than the value of HYSTERESIS, so, the value HYST_output=0 of first output signal, the value HYST_detect=of second output signal is true.If identification signal error
ERRBe not less than the value of Control Parameter HYSTERESIS, so, the value HYST_output=signal of first output signal
ERRValue, the value HYST_detect=vacation of second output signal.
Agc circuit 3 also comprises the unit 44 that multiplies each other, and is used for the identification signal error
ERRMultiply each other with the first loop gain constant during signal obtains and the second different loop gain constants during the signal trace.As a result, multiply each other that unit 44 comprises handoff block 28 and the piece 26,27 that multiplies each other.According to the gain that whether obtains received signal, optionally operation is multiplied each other unit 44 the value of output HYST_output and Control Parameter GAIN_SLOW is multiplied each other or multiply each other with the value of GAIN_FAST.
The identification signal error that multiplies each other of unit 44 output of multiplying each other is provided for recurrence integrator 45.
Recurrence integrator 45 comprises first and second registers 33 and 34, switch 35, saturate block 32, adder 31.The second different AGC values of using first register, 33 storage nominal channel to manipulate.When receiver carries out cell search on intermediate frequency (inter-frequency) or intermediate system (inter-system) channel, second register, 24 storages the one AGC value.This channel usually is called " search channel ".Recurrence integrator 45 is pressed the following formula computing:
GAIN[k]=GAIN[k-1]+HYST_Output*GAIN_SLOW, or
GAIN[k]＝GAIN[k-1]+HYST_Output*GAIN_FAST
Wherein, GAIN is the current AGC value that remains in first or second register 33 and 34.These registers keep the current logarithm value of the used gain control signal of receiver.
Be provided to the input signal of AGC computing block 3 from DSP and time slot control unit 7
COMMANDDirectly supplied to and obtained control logic piece 29.According to from
COMMANDSignal and signal
HYST_detectThe instruction that receives of state, obtain control logic piece 29 and determine
SEI AB.HOLDState with signal 41.
SEL_ABSignal determines whether the AGC value that is stored in first or second register is fed, and is reconfigured by adder 31 and the identification signal error that multiplies each other, so that carry out the recurrence integration.
By multiplier 26 of selecting to have the GAIN_SLOW constant that is used for " following the tracks of slowly " pattern or the multiplier 27 that is used for the GAIN_FAST constant of " obtaining fast " pattern, whether signal 41 control AGC pieces 3 are " following the tracks of slowly " pattern or " obtaining fast " patterns.
Work as signal
HOLDWhen obtaining control logic piece 29 and keep, it is 0 that switch 30 makes first input that obtains adder 31, and adder has kept the current yield value that is kept in first or second register 33 or 34 effectively.
The output that unit 36 is connected to recurrence integrator 45 searched in preamplifier control and AGC word, and the output of recurrence integrator 45 is converted into two output signals, promptly
PREAMP ONWith
AGC WORDUse
PREAMP ONOutput signal control lawnmower amplifier 6.If the gain of the output of recurrence integrator 45 surpasses predetermined threshold value, then be provided with
PREAMP ONOutput signal on the contrary, if another different threshold values are fallen in gain, then is provided with to first state
PREAMP ONOutput signal is to spurious state.It is different values that these two threshold values are set, with the concussion that prevents to cause by the following fact, the switching delay of preamplifier is different from the response time of gain-controlled amplifier, and when signal level during near the threshold value of preamplifier, frequent switching transition meeting causes the reduction of signal quality.
AGC WORDOutput signal is produced by the yield value of conversion recurrence integrator 45 outputs, and uses the storage copy of the control response of gain-controlled amplifier.All Control Parameter in this unit 36 are provided by DSP and time slot control unit 7, and set with respect to radio-frequency channel frequency and temperature correction.
Gain on the output of recurrence integrator 45 is also supplied to received signal intensity display (RSSI) formatting unit 37, and the value of its conversion integrator output becomes incoming signal level dBuV.Again, conversion is based on the CALIBTATION_DATASET ratio data that DSP and time slot control unit 7 provide, and with respect to radio-frequency channel frequency and temperature correction.
Automatic gain control circuit also comprises and obtains logical circuit 29, is used for:
(a) whether detection signal obtains and obtains;
(b) selectivity of carrying out phase quadrupler 44 is operated;
(c) in recurrence integrator 45, select whether to use first or second register 33 or 34.
(d) detection of obtaining according to signal or the new instruction of reception produce signal
AGC_VALIDWith
SEARCH_WINDOW
Obtaining control logic circuit 29 operates as follows: have five different modes of operation: " maintenance ", " obtaining nominal ", " obtaining search ", " nominal ", " search ".Also have five instructions of corresponding aforesaid operations state, it uses identical title.When DSP and time slot control unit 7 exist
COMMANDWhen sending new instruction on the signaling bus, then say of the change of state of row to another state.
After receiving " hold " instruction, control logic 29 is provided with very immediately
HOLDSignal, and falseness is set
AGC_VALIDWith
SEARCH_WINDOWSignal.Signal 41 Hes
SEL_ABBe held constant.
After receiving " obtaining nominal " instruction, control logic 29 is provided with immediately
HOLDSignal is false, is provided with
SEL_ABBe vacation, signalization 41 is true, and is provided with
AGC_VALIDWith
SEARCH_WINDOWBe vacation.Simultaneously, start the time-out count device.Each AGC clock cycle of this counter adds one.If the number of the clock cycle of counting is more than or equal to ACQ_TIMEOUT, then signalization 41 is false,
AGC_VALIDFor very.Simultaneously, if signal
HYST_detectBecome very, then second counter resets to 0.When the value of second counter greater than ACQ_GUARD_TIME, then control logic 29 signalizations 41 are false,
AGC_VALIDFor very, and stop first counter.In principle, ACQ_TIMEOUT is set is bigger value, with box lunch
HYST_detectNever become true time and cover this situation.This situation only takes place during the system failure of not expecting, for example, and out of order AGC D/A converter 4.In normal condition, after the short time
HYST_detectBecome true.Signalization 41 is false AGC is switched to " following the tracks of slowly " pattern, so that announce that greater than the moment of ACQ_GUARD_TIME AGC obtains at second counter.
After receiving " obtaining search " instruction, control logic 29 is provided with immediately
HOLDSignal is false, is provided with
SEL_ABFor very, signalization 41 is true, is provided with
AGC_VALIDWith
SEARCH_WINDOWBe vacation.Afterwards, its behavior is afterwards the same with " obtaining nominal " instruction, except
AGC_VALIDBe set to very,
SEARCH_WINDOWOutside also being set to very.After receiving " nominal " instruction, control logic 29 is provided with immediately
HOLDSignal is false, is provided with
SEL_ABBe vacation, signalization 41 is false, is provided with
AGC_VALIDFor very, be provided with
SEARCH_WINDOWBe vacation.In this case, two timers do not move.
After receiving " search " instruction, control logic 29 is provided with immediately
HOLDSignal is false, is provided with
SEL_ABFor very, signalization 41 is false, is provided with
AGC_VALIDFor very, be provided with
SEARCH_WINDOWFor very.In this case, two timers do not move.
In principle, when when keeping the power mobile radio station prepare to switch radio-circuit, issue " maintenances " is instructed.Keep pattern operating period at this, loop gain optionally is maintained at fixed value.When radio-circuit was switched on after some time, issue " nominal " or " search " was instructed, thereby, recovered to be used for the yield value of knowing at last of nominal or search channel.
The instruction issue of the first Cell searching cycle on new wireless channel in principle of " obtaining search ".The search cycle subsequently of used wireless channel of cycle is in front used in " search " instruction basically, and has obtained already to gain and be stored in second register " 34 ".
When mobile radio station is during in nominal channel, but also obtain gain, " obtaining nominal " instruction is issued after energized in principle.
As shown in Figure 3, the valid data that are used for the nominal transmission channel send with packet 50,51,52, and these packets are separated by transmission slot 53 and 54.Intermediate frequency or intermediate system Cell searching are carried out by the receiver in transmission slot 53 and 54 search channel of determining.After beginning to detect each transmission slot, DSP and time slot control unit 7 send " obtaining search " instruction 55.Instruction 55 detects by obtaining control logic 29.The detection of instruction 55 causes the selection operation of phase quadrupler 44, so that switch 28 work also are connected in series multiplier 27 and HYSTERESIS piece 25 and recurrence integrator 45.Now, AGC computing block 3 is in " obtaining fast " pattern.
The detection of " obtaining search " additionally makes second register 34 be connected in series with recurrence register 45, and can obtain search channel used AGC value of operating period in second register 34.The value that increases gradually of second register 34 is reflected in
AGC_VORDOutput signal overflow edge 57.The identification signal error that detects extra block 14 output when HYSTERESIS piece 25 less than from the Control Parameter HYSTERESIS of DSP and time slot control unit 7 time, as
AGC_VORDShown in the point 58 of output signal, obtain control logic unit 29 and reset signal 41 after the cycle, and be set at rising edge 59 signals at AGC_GUARD_TIME
AGC_VALIDTrue value.At that point, in other words, obtain according to gain, phase quadrupler 44 makes switch 28 optionally work at once, and multiplier 26 is connected in series between HYSTERESIS piece 25 and the recurrence integrator 45 now.Therefore, AGC computing block 3 is placed on " following the tracks of slowly " pattern, has followed the tracks of valid data 60 during transmission slot 53.Because instruct 55 to be " obtaining search ", so also with signal
SEARCH_WINDOWBe set to true value.
On the end point of transmission slot 53, DSP and time slot control unit 7 send " nominal " instruction 62.This instruction makes phase quadrupler 44 carry out selectivity operation, so that switch 28 works again, and multiplier 26 is connected in series between HYSTERESIS piece 25 and the recurrence integrator 45.Therefore, AGC computing block 3 remains on " following the tracks of slowly " pattern again automatically.
And instruction 62 makes that obtaining control logic 29 resets
SEL_ABSignal is false, and the register 33 of winning is connected in series with recurrence integrator 45, therefore, loads the first current AGC value that is stored in this, is used for the nominal channel operation of receiver.The difference of AGC that is stored in first register 33 and second register 34 is by rising edge 64
AGC_WORDVariation in the signal value shows.
If the loop gain of nominal channel operating period obtains in advance, the identification signal error will be less than command word HYSTERESIS, therefore, and from the output signal of HYSTERESIS piece 25
HYST_OUTPUTTo be 0.So, receiver continue to be handled the packet 51 of the valid data that nominal channel operating period receives.
During next one transmission slot 54, DSP and time slot control unit 7 send " search " instruction 66, win register and recurrence integrator 45 are connected in series, and the 2nd AGC values that are stored in second register 34 are offered AGC D/A converter 4 by piece 36.Reload and be stored in the trailing edge 67 that value in second register 34 is presented at AGC WORD output signal.
From foregoing description as can be seen, AGC computing block 3 is operated in two kinds of patterns, that is, and and " obtaining fast " and " following the tracks of slowly " pattern.Conversion between two kinds of patterns is realized by two kinds of different loop yield values that Control Parameter GAIN_SLOW and GAIN_FAST determine.In the beginning of each scouting interval, AGC computing block 3 is in " obtaining fast " pattern automatically, and when obtaining control logic 29 and determine to have obtained suitable channel gain, AGC computing block 3 is switched " following the tracks of slowly " pattern of getting back to.Therefore, the AGC acquisition time is minimized, so in intermediate frequency and intermediate system operating period, influencing the time cycle that Cell searching measures can optimization.In addition, two yield values of knowing at last that are used for the operation of nominal and search channel are stored in each register, so, can obtain to obtain fast.If do not obtain loop gain in the programmable time cycle number that Control Parameter ACQ_TIMEOUT represents, AGC computing block 3 automatically returns to " following the tracks of slowly " pattern.If AGC computing block 3 is in " following the tracks of slowly " pattern, then only generation shows that loop gain is effective output logic signal.
At last, should be appreciated that under the situation that does not break away from the spirit and scope of the present invention, can make the automatic gain control circuit that is described in this and revise and add.
Claims (16)
1. automatic gain control circuit that is used for Receiver of Direct-sequence Spread Spectrum comprises:
Recognition device is used for producing the identification signal error from the homophase and the digital orthogonal baseband signal that receive;
The phase quadrupler is used for the identification signal error is multiplied each other with the first loop gain constant during signal obtains and second different loop gain constant during the signal trace; And
The recurrence integrator is used for obtaining from the identification signal error that multiplies each other the AGC value of integration, and wherein, described recurrence integrator comprises:
First register is used for storing an AGC value in search channel operating period;
Second register is used in second different AGC value of nominal channel operating period storage; And
The AGC conversion equipment is used for optionally the first and second current AGC values being loaded in the recurrence integrator respectively when search and nominal channel operation beginning.
2. by the described automatic gain control circuit of claim 1, it is characterized in that also comprising the device that optionally is maintained fixed gain.
3. by the described automatic gain control circuit of claim 1, it is characterized in that the AGC conversion equipment when nominal channel operation beginning in first register current AGC value of storage first.
4. by the described automatic gain control circuit of claim 1, it is characterized in that the AGC conversion equipment also when search channel operation beginning in second register storage the 2nd AGC value.
5. by the described automatic gain control circuit of claim 1, it is characterized in that the AGC conversion equipment optionally is connected respectively to the recurrence integrator to first and second registers in search and nominal channel operating period.
6. by the described automatic gain control circuit of claim 1, it is characterized in that also comprising:
Obtain logical circuit, be used for detection signal and obtaining, and obtain according to the signal that detects and to make the phase quadrupler carry out selection operation.
7. by the described automatic gain control circuit of claim 6, it is characterized in that obtaining logical circuit and comprise:
When recognition device is used in the predetermined cycle detection identification signal error that continues less than programmable lagged value.
8. by the described automatic gain control circuit of claim 7, it is characterized in that recognition device determines the identification signal error from the difference between the logarithm of the mean amplitude of tide of the baseband signal of preset value and reception.
9. control the method that Receiver of Direct-sequence Spread Spectrum gains automatically for one kind, comprising:
(a) produce the identification signal error from homophase and the digital orthogonal baseband signal that receives;
(b) the identification signal error is multiplied each other with the first loop gain constant during signal obtains and second different loop gain constant during the signal trace;
(c) use recurrence integrator obtains the AGC value of integration from the identification signal error that multiplies each other, wherein, and an AGC value of in first register, using during the memory search channel operation;
Second different AGC value of storage nominal channel operating period use in second register;
Beginning according to search and nominal channel operation alternately is loaded into the recurrence integrator respectively with the first and second current AGC values.
10. by the described method of claim 9, it is characterized in that also comprising:
(d) optionally be maintained fixed gain.
11., it is characterized in that when nominal channel operation beginning, in first register, storing the first current AGC value by the described method of claim 9.
12., it is characterized in that when search channel operation beginning, in second register, storing the 2nd AGC value by the described method of claim 9.
13. by the described method of claim 9, it is characterized in that alternately first and second registers being connected respectively to the recurrence integrator in search and nominal channel operating period.
14., it is characterized in that also comprising by the described method of claim 9:
Detection signal obtains; And
Obtain according to the signal that detects, the identification signal error and the first loop gain constant are multiplied each other.
15., it is characterized in that also comprising by the described method of claim 14:
Be scheduled to when to continue cycle detection identification signal error less than programmable lagged value.
16., it is characterized in that also comprising by the described method of claim 15:
Determine the identification signal error from the difference between the logarithm of the mean amplitude of tide of the baseband signal of preset value and reception.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AUPR1177/2000 | 2000-11-01 | ||
| AUPR1177/00 | 2000-11-01 | ||
| AUPR1177A AUPR117700A0 (en) | 2000-11-01 | 2000-11-01 | Automatic gain control circuit for direct sequence spread spectrum receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1381957A CN1381957A (en) | 2002-11-27 |
| CN1219359C true CN1219359C (en) | 2005-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011368683A Expired - Fee Related CN1219359C (en) | 2000-11-01 | 2001-10-31 | Automatic gain control circuit and method of direct sequenc spread spectrum receiver |
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| Country | Link |
|---|---|
| JP (1) | JP3767456B2 (en) |
| CN (1) | CN1219359C (en) |
| AU (1) | AUPR117700A0 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6959055B2 (en) * | 2002-07-26 | 2005-10-25 | Thomson Licensing | Multi-stage automatic gain control for spread-spectrum receivers |
| CN102348271B (en) * | 2010-07-30 | 2014-02-26 | 富士通株式会社 | Wireless communication terminal and automatic gain control method |
| CN102348274B (en) * | 2010-07-30 | 2014-07-23 | 富士通株式会社 | Wireless communication terminal |
| CN104144307B (en) * | 2013-05-10 | 2018-02-27 | 硅实验室股份有限公司 | Receiver with automatic growth control freeze capacity |
-
2000
- 2000-11-01 AU AUPR1177A patent/AUPR117700A0/en not_active Abandoned
-
2001
- 2001-10-31 JP JP2001334034A patent/JP3767456B2/en not_active Expired - Fee Related
- 2001-10-31 CN CNB011368683A patent/CN1219359C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3767456B2 (en) | 2006-04-19 |
| JP2002204185A (en) | 2002-07-19 |
| AUPR117700A0 (en) | 2000-11-23 |
| CN1381957A (en) | 2002-11-27 |
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