CN1219324C - Non-volatile semiconductor memory and method - Google Patents
Non-volatile semiconductor memory and method Download PDFInfo
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- CN1219324C CN1219324C CNB021543887A CN02154388A CN1219324C CN 1219324 C CN1219324 C CN 1219324C CN B021543887 A CNB021543887 A CN B021543887A CN 02154388 A CN02154388 A CN 02154388A CN 1219324 C CN1219324 C CN 1219324C
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches through the intervention of a second insulating film; and a third electrode formed on the second electrode through the intervention of a third insulating film.
Description
Technical field
The present invention relates to non-volatile semiconductor memory and method thereof, also include the nonvolatile semiconductor memory and the method thereof of can be high integrated contactless unit.
Background technology
Volume for the storage unit that reduces non-volatile semiconductor memory has adopted the contactless array.This array does not need contact between bit line and drain region diffusion layer, this makes cell design (adjustment) also be suitable for big storage easily.
For example, shown in figure .15 (a) and figure .15 (b) (IEDM 92, pp.991-993,1992), proposed contactless and the unit.
In this unit, the door 24 that suspends is to set up by insert gate insulation film 23 on the passage that forms on the Semiconductor substrate between the high concentration impurity diffusion layer 22 21.In addition, control gate (CG) the 26th forms on the suspension door 24 by being inserted in of dielectric film 25.The function of high concentration impurity diffusion layer 22 not only as source/drain region also as bit line.
In the unit of Miao Shuing, use high concentration impurity diffusion layer 22 must reduce impedance in the above as bit line.Usually, inject as impurity, under 750 ℃ or higher temperature, do heat treatment and activate high concentration impurity diffusion layer 22 as the phosphorus or the arsenic ion of high concentration.
Yet impurity is also in horizontal proliferation during high-temperature process, and this has increased as scheming suspension door 24 shown in the .15 (b) and the overlap length between the high concentration impurity diffusion layer 22.As a result, the adjustment of overlap length becomes difficult.
Moreover if attempt to make the unit microminiaturization, in order to stop the passage length L that is called short-channel effect and remains valid, the overlap length that suspends between door 24 and the high concentration impurity diffusion layer 22 is very important factor.Therefore, adjust the length M of door, the overlap length between adjustment suspension door and the high concentration impurity diffusion layer plays an important role to the microminiaturization of unit.
Summary of the invention
According to the present invention, a kind of non-volatile semiconductor memory with memory cell has been proposed, comprising: have the Semiconductor substrate that forms a pair of groove in its surface; By forming first electrode respectively in a pair of groove of being inserted in of first dielectric film; Form second electrode on the Semiconductor substrate between the groove by being inserted in of second dielectric film; Form third electrode by being inserted on second electrode of the 3rd dielectric film.
According to the present invention, the method for writing non-volatile semiconductor memory is provided, wherein write operation is:
(1) first step applies a voltage that is lower than the gate transistor threshold value to first electrode of the gate transistor that is connected with the source region,
The drain region is applied one gives the voltage of determining earlier,
All first electrodes to the gate transistor that is connected with the drain region apply a voltage that is higher than the threshold value of gate transistor, and channel region is charged immediately makes it be lower than the drain voltage of second electrode of memory cell;
(2) second steps applied a voltage that is lower than the threshold value of gate transistor to first electrode of the gate transistor that is connected with the drain region that does not have selecteed memory cell,
The drain region ground connection that is connected with selected memory cell,
Third electrode with selected memory cell is applied a voltage that is higher than selected memory cell threshold value.
Description of drawings
Figure .1 (a) is the vertical view of principle, and figure .1 (b) and figure .1 (c) are the principle profiles, and each figure has shown the embodiment of the non-volatile semiconductor memory of the present invention;
Figure .2 is the equivalent diagram of non-volatile semiconductor memory of figure .1;
Figure .3 (a) is the vertical view of principle, and figure .3 (b) and figure .3 (c) are the principle profiles, and each figure has shown the embodiment of another non-volatile semiconductor memory of the present invention;
Figure .4 is the equivalent diagram of non-volatile semiconductor memory of figure .3;
Figure .5 has shown the equivalent diagram of another embodiment of the non-volatile semiconductor memory of the present invention;
Figure .6 has shown that the present invention makes the principle profile of major part of the method step of non-volatile semiconductor memory;
Figure .7 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .8 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .9 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .10 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .11 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .12 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .13 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .14 is the principle profile that the major part of the method step of making non-volatile semiconductor memory is described by the present invention;
Figure .15 (a) and figure .15 (b) illustrate the equivalent diagram and the principle profile of aforementioned non-volatile semiconductor memory respectively.
Embodiment
Nonvolatile semiconductor memory of the present invention comprises one or more memory cell of being made up of Semiconductor substrate, first electrode, second electrode, third electrode.
So long as be generally used for the Semiconductor substrate of semiconductor memory obviously is not limited.For example, Semiconductor substrate such as silicon and Ge element, compound semiconductor substrate such as GaAs, InGaAs compound and ZnSe, SOI substrate and multilayer SOI substrate can be considered.In them, silicon substrate is preferable.Semiconductor substrate is included in this device isolation district that forms above.In addition, Semiconductor substrate and transistor, electric capacity, element such as resistance, insulating film of intermediate layer, circuit and the semiconductor device be made up of them are combined to form the single or multiple lift structure.The insulation layer of device can be formed the film as LOCOS by the dielectric film of multiple device, groove oxide-film and STI film, and the STI film is used better in them.
Form in the groove that first electrode forms on the semiconductor substrate surface by being inserted in of first dielectric film.
As, about 2000 to 5000 of formed groove depth.
First dielectric film obviously is not limited, and for example, it may be made up of the single or multiple lift film, promptly; Dielectric film such as silicon oxide film and silicon nitride film, or high dielectric film such as TiO
2And AL
2O
3The thickness of first dielectric film is that 50 to 300 are suitable, and this thickness can be consistent in groove, or changes in bottom and cell wall.The thickness of trench bottom first dielectric film than the thickness of cell wall bigger for good.For example, at about 50 to 300 of trench bottom thickness at about 100 to 500 of cell wall.If the first dielectric film trench bottom and groove edge varied in thickness are as described above, first electrode added than the high voltage of transistor threshold off status of bottom land when the channel region that cell wall forms guarantee easily.
If do not change the thickness of trench bottom and groove edge first dielectric film, dope in the part side of the bottom surface of groove and groove that impurity concentration is different just to obtain effect described above.In this case, impurity concentration is preferable to be to change in this manner, has the zone of different impurities concentration to be arranged in the two sides symmetry on a groove.This might only improve the impurity concentration near the bottom surface of the groove of (bottom that the comprises the side) bottom surface, or only in the impurity concentration of the bottom of the side of groove.In this case, the excursion that impurity concentration is suitable is about 10
10To 10
11Cm
-3Lower zone and about 10
17To 10
19Cm
-3Higher zone.
For example, the thickness of first dielectric film can change by following step, promptly, on the Semiconductor substrate that forms groove, form dielectric film, etch into and only on groove, stay dielectric film, then, this Semiconductor substrate is done heat treatment and is formed heat oxide film at the sidewall of groove, and this is thinner than the dielectric film in groove bottom.
Further, as the method that changes impurity concentration, it is from the vertical direction injection ion of the Semiconductor substrate that forms groove that method is arranged, and does not form the semiconductor substrate surface of groove with dielectric film or photoresist mask, so has only injected impurity in the bottom surface of groove.Another kind method is for to inject ion with different injection energy several times with mask or without mask.
In single memory cell, form two first electrodes, promptly a pair of.The function of these first electrodes is called storbing gate and is called gate transistor with what first dielectric film was formed.
One of first electrode pair (the first electrode transistor) links to each other better with the source region, and other better links to each other better with the drain region.
If form an above memory cell, first electrode of memory cell connects better along the Y direction.
If form an above memory cell, better in shared first electrodes (the first electrode transistor) of contiguous two memory cell of directions X, the first shared electrode (the first electrode transistor) is connected better with the source region.
If form an above memory cell, better in shared first electrodes (the first electrode transistor) of contiguous two memory cell of directions X, other of memory cell first electrode (the first electrode transistor) links to each other with the drain region.Therefore first electrode that links to each other with the drain region may add identical voltage to them for the connection of electricity, may therefore add different voltage for the insulation of electricity to them, perhaps, Dian connection or the electricity insulation and several groups first electrodes have been added identical voltage or different voltage.In any case, with the contiguous the first region that is connected the drain region between form can be more better in the device isolation district.
First electrode may be by elemental semiconductor (as silicon and germanium) or compound semiconductor (as GaAs, InP, ZnSe and C
sS) single or multiple lift of Zu Chenging, this is N type or P type and amorphous, monocrystalline or polycrystalline; Metals like gold, platinum, silver, copper and aluminium; High some metal such as Tai ， Tantalum and the tungsten of holding; Or silicide and the high polymer that holds the some metal of tool.In above material, polysilicon is used better.The thickness of first electrode can suitably be regulated according to the degree of depth of groove and the thickness of first dielectric film.As, about 500 to 2000 .
Insertion second electrode by second dielectric film forms on the Semiconductor substrate between the groove.Second electrode function is called the door that suspends.The material of second dielectric film and thickness may with the equating of first dielectric film.The material of second electrode may with the identical of first electrode so thickness that it is suitable, as, about 50 to 150nm.
Insertion third electrode by the 3rd dielectric film forms on second electrode.The third electrode function is called control gate.The material of the 3rd dielectric film and thickness may with the equating of first dielectric film.Preferably, the 3rd dielectric film is formed with the ONO film of the thickness about 100 to 200nm of oxide-film form.Third electrode may be by forming with the first electrode identical materials, so its suitable thickness, as, about 100 to 300nm.
If form an above memory cell,, third electrode is connected along directions X better with memory cell.
The method of work of semiconductor memory of the present invention is described in detail with following mask body mode.Yet, hereinafter the added voltage of embodiment not to be placed restrictions on, any magnitude of voltage can be considered as long as work can realize under the voltage effect of mentioning below.
Hereinafter, the concrete formation and the method for work of non-volatile semiconductor memory are described with the description of the drawings equally.
Embodiment 1: single memory cell
Fig. 1 (a), 1 (b), the single memory cell of 1 (c) and the non-volatile semiconductor memory of 2 explanation the present invention.
To shown in 1 (c), memory cell comprises P type silicon substrate 1, forms groove on this substrate as Fig. 1 (a), and by the insertion that bottom surface and side at groove form the storbing gate oxide-film 6 of groove, the storbing gate of being made up of polysilicon 8 (SG1 and SG2) is embedded in the groove.The insertion of the tunnel dielectric film 10 by forming ONO film 14 and control gate 15 (CG) in the above according to this forms the suspension door of being made up of polysilicon 12 (FG) on the plane of the silicon substrate between the groove 1.
As shown in Figure 2, an end of memory cell links to each other with the drain region by storbing gate (SG1), and the other end links to each other with the source region by storbing gate (SG2).
The working method of the single memory cell parameter interpretation of table 1.
Table 1
| SG1 | SG2 | D | S | CG | |
| Read | 3V | 3V | 1V | 0 | 4V |
| Write | 4V | 0 | 1/4V | 0 | 20V |
| Wipe | 0 | 0 | 0 | 0 | -20V |
When reading, the voltage that is higher than the threshold value of storbing gate SG1 and SG2 is added in the state that makes it on storbing gate SG1 and the SG2 to opening for 3 volts.The drain region is added 1 volt, and source region ground connection also adds 4 volts to control gate, if transistorized threshold voltage be lower than 4 volts of the voltages of control gate or more the higher position set up the state that closes, and the voltage of the control gate state that to be 4 volts or lower just foundation open.
When wiping, source region, drain region and storbing gate SG1 and SG2 be ground connection, and control gate adds-20 volts negative high voltage.Therefore, electronics is extracted into Semiconductor substrate from the door that suspends, and this threshold value that has reduced memory cell is wiped with execution.
When writing, the storbing gate SG2 of the storbing gate SG1 of drain region end and source region end is added 4 volts and source region ground connection.Because the drain region ground connection of selected cell, the drain region of selected cell does not add 4 volts, and control gate adds 20 volts, the selectable T of selected cell
rThe state that enters out has acted on high electric field on the tunnel oxide-film, electronics is injected into the door that suspends from Semiconductor substrate, therefore, has improved the threshold value of selected cell.On the other hand, to selected cell not, selectable T
rEnter the state of pass, the depletion layer that the semiconductor substrate surface in the tunnel district forms becomes suspended state.In the case, the electric field that acts on the tunnel oxide-film is lower, electronics does not take place inject, so threshold value does not change.Under the effect of the above voltage, carry out write operation.
Embodiment 2: the memory cell battle array
Fig. 3 (a), 3 (b), the memory cell battle array of 3 (c) and the non-volatile semiconductor memory of 4 explanation the present invention.
As Fig. 3 (a) to shown in 3 (c), the memory cell battle array comprise a large amount of as Fig. 1 (a) to the single memory cell shown in 1 (c), shared storbing gate 8 (SG2) between contiguous two memory cell on the directions X, control gate 15 (CG1 and CG2) is connected with a large amount of single memory cell on being arranged in directions X.
With reference to figure 4,, the gate voltage of storbing gate 8 (SG1) can act on memory cell even being provided with identical, different drain voltage.Two-wire among Fig. 4 has been pointed out transistor channels.
The working method of the memory cell parameter interpretation of table 2.
Table 2
| Read | Write | Wipe | |
| SG1 | 3V | 4V | 0 |
| SG2 | 3V | 0 | 0 |
| D1 | 1V | 0 | Suspend |
| D2 | 0 | 4V | Suspend |
| CG1 | 4V | 20V | -20V |
| CG2 | 0 | 0 | 0 |
| S | 0 | 0 | 0 |
In this embodiment, do reference for the easy memory cell battle array that comprises two row, two row of explaining.C11 is a selected cell.
When reading, the voltage that is higher than the threshold value of storbing gate SG1 and SG2 is added in the state that makes it on storbing gate SG1 and the SG2 to opening for 3 volts.When the drain region 1 of selected cell C11 adds 1 volt (drain region 2 adds 0 volt), source region ground connection, control gate CG1 adds 4 volts of voltages (control gate CG2 adds 0 volt), if the voltage of the threshold value of unit is lower than 4 volts (erase statuses), the state that state just transfers to open, if the voltage of the threshold value of unit is higher than 4 volts (writing state), state just transfers the state of pass to, therefore, the state of selected cell C11 just can be read.
When wiping, control gate adds-20 volts negative high voltage (SG3 and source region add 0V for SG1, SG2, and drain region 1,2 is for opening) electronics and is extracted into Semiconductor substrate from the door that suspends, and this has reduced the threshold value of memory cell, and like this, wiping is finishing of a line of line.
When writing, drain region 1 ground connection of selected cell C11, the drain region 2 of selected cell does not add 4 volts, and storbing gate (SG1) adds 4 volts, simultaneously, the state of storbing gate (SG2) 1 ground connection to keep closing.Under inclined to one side state of value, the control gate of selected cell (CG1) adds 20 volts high pressure, and therefore high electric field only acts on the tunnel oxide-film of selected cell C11, and electronics is injected into the door that suspends from substrate.Like this, threshold value becomes higher.Under the effect of the above voltage, carry out write operation.
Embodiment 3: the memory cell battle array
The memory cell battle array comprise a large amount of as Fig. 3 (a) to 3 (c) and single memory cell shown in Figure 5, contiguous shared storbing gates 8 of two memory cell (SG2) on directions X wherein, control gate 15 (CG1 and CG2) is connected with a large amount of single memory cell on being arranged in directions X.
The insulation layer of device forms between the contiguous storbing gate that is connected with the drain region, thereby provides electric insulation between row.
Shown in Figure 5 between the adjoining memory cell that adds different selectable gate voltages (SG1: be divided into SG1a and SG1b) drain region shared.Two-wire among Fig. 5 is pointed out transistorized passage.
The working method of the memory cell battle array parameter interpretation of table 3
| Read | Write | Wipe | |
| SG1a | 3V | 6V | 0 |
| SG1b | 0 | 6V→0V | 0 |
| SG2 | 3V | 0 | 0 |
| D1 | 1V | 4V→0 | Suspend |
| D2 | 1V | 4V→4V | Suspend |
| CG1 | 4V | 6V→20V | -20V |
| CG2 | 0 | 6V | 0 |
| S | 0 | 0 | 0 |
When reading, the voltage that is higher than the threshold value of selecting door SG1a and SG2 is added in the state that makes it on storbing gate SG1a and the SG2 to opening for 3 volts.When the drain region of selected cell C11a and C12a adds 1 volt (drain region 1 and drain region 2 add 1 volt), source region ground connection, control gate CG1 adds 4 volts of voltages (control gate CG2 adds 0 volt), if the threshold voltage of unit is 4 volts or the lower state of just setting up out, and if threshold voltage be 4 volts or more the higher position set up the state of pass.Therefore, data are read from selected cell C11a and C12a.
When wiping, control gate (CG1) adds-20 volts negative high voltage and SG1, SG2, and SG3 and source region add 0V, and drain region 1,2 is for opening.Therefore, electronics is extracted into Semiconductor substrate from the door that suspends, and this has reduced the threshold value of memory cell.Like this, wipe finishing of a line of line.
When writing, storbing gate (SG2) free ground connection to enter the state of pass, write by following two steps and finish.Though Fig. 5 shows 2 unit C11a and C11b on single control gate, the explanation that this situation is provided is that data write on unit of C11a.
The first step, the storbing gate SG1 of two unit (SG1a and SG1b) adds 6V, and drain region 1 and drain region 2 add 4V, and control gate (CG1 and CG2) adds 6 volts, makes unit channel be charged to about 4V.
Second step, be connected in the storbing gate SG1b ground connection of not selected unit (C11b and C12b), then, in a selected unit (C11a and C12a), drain region 1 ground connection of selected cell, the drain region 2 of selected cell does not remain on 4 volts, and the voltage of the control gate (CG1) of selected cell (C11a) is elevated to 20V.Simultaneously, high electric field only acts on the tunnel oxide-film of selected cell (C11a), and electronics is injected into the door that suspends from substrate.Like this, the threshold value of unit improves.Under the effect of the above voltage, carry out write operation.On the other hand, because the channel region of selected cell still is not charged to 4 volts and be in suspended state, the electric field that acts on the passage oxide-film is low, and electronics does not obtain by the passage oxide-film and gives.Like this, be finishing of bit one bit to writing of selected cell.
Embodiment 4: manufacture method
At first, as shown in Figure 6, the silicon substrate 1 that it is first conductivity type that the oxide-film 2 that 20nm is thick is deposited on through 900 ℃ of high-temperature oxydations, the nitride film 3 that 100nm is thick is deposited on the oxide-film 2.As mask, it is the groove 5 of 300nm that etched silicon substrate 1 forms the degree of depth with the photoresist with the shape of pre-determining.
Then, remove photoresist, on groove 5, form the thick flowing current separation open gate oxide-film 6 of 20nm with thermal oxidation method as shown in Figure 7.In order to obtain final silicon substrate 1, inject boron with 0 ° of injector angle, only form diffused layer of boron 7 in groove 5 bottoms, therefore, the threshold value of groove 5 bottoms is brought up to also higher than the groove sidewall threshold value that electric insulation between groove left side wall and the right side wall is provided.
As shown in Figure 8, polysilicon film 8a deposits to and buries the such thickness of groove 5, as, 300nm, is exposed by the flatten surface of nitride film 3 of CMP.
As shown in Figure 9, thermal oxidation is filled into the polysilicon film 8a of groove 5, forms heat oxide film 9 and storbing gate 8 is provided on polysilicon film 8a surface.
As shown in figure 10, removed the polysilicon film 1 of nitride film 3 and oxide-film 2 from above and make the thick tunnel oxide-film 10 of thermal oxidation formation 7nm under 800 °, therefore, oxide-film 14 that about 14nm is thick and heat oxide film 9 are arranged in respectively on the limit and top of polysilicon film.
As shown in figure 11, polysilicon film is to be deposited on the final silicon substrate 1, and this is to form figure and form door (FG) 12 that suspend as mask with photoresist.
At last, as shown in figure 12, deposition is equivalent to 14nm thick ONO film 14 and silicide film with the oxide-film conversion.The figure that is etched into word line of silicide film, ONO film 14 and door 12 orders that suspend.Control gate 15 forms with self aligned form, and has obtained transistor.
Embodiment 5: manufacture method
As shown in Figure 6, groove 5 forms at silicon substrate 1.
After removing photoresist 4, form oxide-film on final silicon substrate 1, etching is only returned and is stayed oxide-film 6a in the bottom surface of groove as shown in figure 13.
As shown in figure 14, form ratio in the groove side at the thin heat oxide film 6b of the oxide-film 6a of groove bottom.
Following manufacturing step is identical with embodiment 4
According to this method, the oxide-film 6a that forms in the bottom surface of groove is thicker than the oxide-film 6 that the side at groove forms, and this has improved the threshold value in groove bottom, simultaneously, and can electrically insulated from one another at the channel region on the groove left side and the right.
By the present invention, first electrode is embedded in the groove that is formed on the Semiconductor substrate, and passes through the channel region connection source/drain region of the gate transistor of formation first electrode.This has eliminated the needs in the source/drain region of the channel region of Direct Attached Storage unit and impurity diffusion layer.Therefore, do not overlap between the suspension door of impurity diffusion layer and memory cell, this has improved the adjustable of door length greatly.Therefore can provide large buffer memory and low bit loss non-volatile semiconductor memory.
Utilize FN tunnel current and channel hot electron finish from reading and wiping non-volatile semiconductor memory.So, provide highly reliable and non-volatile semiconductor memory high-speed writable.
Claims (14)
1. non-volatile semiconductor memory with memory cell comprises:
On the surface of Semiconductor substrate, form a pair of groove;
By forming first electrode respectively in a pair of groove of being inserted in of first dielectric film;
Form second electrode on the Semiconductor substrate between the groove by being inserted in of second dielectric film;
Form third electrode by being inserted on second electrode of the 3rd dielectric film.
2. by the described nonvolatile semiconductor memory of claim 1, it is characterized in that memory cell is connected with pair source respectively by the gate transistor that comprises first electrode.
3. by the described non-volatile conductor memory of claim 1, it is characterized in that the thickness of first dielectric film on bottom land and wall is different.
4. by the described nonvolatile semiconductor memory of claim 1, it is characterized in that mixing in the side and the bottom surface of the groove that forms on Semiconductor substrate, its doping content is different on the bottom surface of groove and a pair of side.
5. by the described nonvolatile semiconductor memory of claim 2, it is characterized in that the threshold voltage that is higher than gate transistor is added in respectively on first electrode, with change two gate transistors from off status to the state of opening.
6. by the described nonvolatile semiconductor memory of claim 2, it is characterized in that the threshold voltage that is higher than gate transistor is added on one of them first electrode, change this gate transistor from off status to the state of opening, the threshold voltage that is lower than gate transistor is added on another first electrode, changes this gate transistor from opening state to the state that closes.
7. by the described nonvolatile semiconductor memory of claim 1, it is characterized in that:
A plurality of memory cell are arranged with matrix-style;
The memory cell of arranging at directions X is connected with the third electrode that is positioned at directions X;
The memory cell of arranging in the Y direction is connected with first electrode that is positioned at the Y direction;
Memory cell is connected with pair source respectively by the gate transistor that comprises first electrode, and common source/drain region.
8. by the described nonvolatile semiconductor memory of claim 7, it is characterized in that, by the gate transistor foundation of shared first electrode formation and being connected of source region at contiguous shared one of them first electrode of memory cell of directions X.
9. by the described nonvolatile semiconductor memory of claim 7, it is characterized in that all first electrodes of the gate transistor that is connected with the source region all link to each other usually.
10. by the described nonvolatile semiconductor memory of claim 7, it is characterized in that all first electrodes of the gate transistor that is connected with the drain region all link to each other usually.
11. by the described nonvolatile semiconductor memory of claim 7, it is characterized in that first electrode of the gate transistor that is connected with the drain region is an electric insulation, thereby can add different voltage.
12., form the device isolation district between adjacent first electrode that it is characterized in that being connected with the drain region by gate transistor by the described nonvolatile semiconductor memory of claim 7.
13., it is characterized in that source region ground connection by the described nonvolatile semiconductor memory of claim 7.
14. the method that nonvolatile semiconductor memory is write, wherein write operation is as follows:
(1) first step applies a voltage that is lower than the gate transistor threshold value to first electrode of the gate transistor that is connected with the source region;
The drain region is applied a predetermined voltage;
All first electrodes to the gate transistor that is connected with the drain region apply a voltage that is higher than the gate transistor threshold value, and channel region is charged immediately makes it be lower than the drain voltage of second electrode of memory cell;
In (2) second steps, first electrode of the gate transistor that is connected with the drain region that does not have selecteed memory cell is applied a voltage that is lower than the gate transistor threshold values;
The drain region ground connection that is connected with selected memory cell;
Third electrode with selected memory cell is applied a voltage that is higher than the threshold value of selected memory cell.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001375993 | 2001-12-10 | ||
| JP2001375993A JP4027656B2 (en) | 2001-12-10 | 2001-12-10 | Nonvolatile semiconductor memory device and operation method thereof |
| JP2001-375993 | 2001-12-10 |
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| CN1426114A CN1426114A (en) | 2003-06-25 |
| CN1219324C true CN1219324C (en) | 2005-09-14 |
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| JP (1) | JP4027656B2 (en) |
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| JP3998467B2 (en) * | 2001-12-17 | 2007-10-24 | シャープ株式会社 | Nonvolatile semiconductor memory device and operation method thereof |
| DE10321742A1 (en) * | 2003-05-14 | 2004-12-09 | Infineon Technologies Ag | Integrated circuit arrangement with isolation trench and field effect transistor as well as manufacturing process |
| US7119393B1 (en) * | 2003-07-28 | 2006-10-10 | Actel Corporation | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit |
| JP2005101174A (en) * | 2003-09-24 | 2005-04-14 | Hitachi Ltd | Non-volatile semiconductor storage device and method for manufacturing the same |
| JP2006032489A (en) * | 2004-07-13 | 2006-02-02 | Nec Electronics Corp | Nonvolatile semiconductor storage device and its manufacturing method |
| TWI270199B (en) * | 2005-01-31 | 2007-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
| JP2007115773A (en) * | 2005-10-18 | 2007-05-10 | Nec Electronics Corp | Semiconductor memory device and method of manufacturing same |
| KR100742284B1 (en) * | 2006-02-09 | 2007-07-24 | 삼성전자주식회사 | Nonvolatile memory device and method of forming the same |
| KR100919433B1 (en) * | 2006-06-29 | 2009-09-29 | 삼성전자주식회사 | Non volatile memory device and method for fabricating the same |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| JP5572953B2 (en) * | 2009-01-15 | 2014-08-20 | 凸版印刷株式会社 | Nonvolatile semiconductor memory cell and nonvolatile semiconductor memory device |
| US10141327B2 (en) | 2016-03-18 | 2018-11-27 | Toshiba Memory Corporation | Semiconductor memory device |
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|---|---|---|---|---|
| US4267632A (en) * | 1979-10-19 | 1981-05-19 | Intel Corporation | Process for fabricating a high density electrically programmable memory array |
| JP4330670B2 (en) * | 1997-06-06 | 2009-09-16 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| US6151248A (en) * | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
| JP4117998B2 (en) * | 2000-03-30 | 2008-07-16 | シャープ株式会社 | Nonvolatile semiconductor memory device, reading, writing and erasing methods thereof, and manufacturing method thereof |
| JP4087108B2 (en) * | 2001-12-10 | 2008-05-21 | シャープ株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP3998467B2 (en) * | 2001-12-17 | 2007-10-24 | シャープ株式会社 | Nonvolatile semiconductor memory device and operation method thereof |
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2001
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2002
- 2002-12-04 CN CNB021543887A patent/CN1219324C/en not_active Expired - Lifetime
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| US20050239245A1 (en) | 2005-10-27 |
| US6952031B2 (en) | 2005-10-04 |
| CN1426114A (en) | 2003-06-25 |
| KR100501063B1 (en) | 2005-07-18 |
| JP4027656B2 (en) | 2007-12-26 |
| KR20030047805A (en) | 2003-06-18 |
| TW578301B (en) | 2004-03-01 |
| US20040109355A1 (en) | 2004-06-10 |
| TW200301012A (en) | 2003-06-16 |
| US7326991B2 (en) | 2008-02-05 |
| JP2003179167A (en) | 2003-06-27 |
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