CN1218529C

CN1218529C - Multi-progression event synchronizer and its system

Info

Publication number: CN1218529C
Application number: CN 01103816
Authority: CN
Inventors: 苏仁斌; 陈灿辉; 林文相; 吴俊杰; 林昌辅
Original assignee: Silicon Integrated Systems Corp
Current assignee: Silicon Integrated Systems Corp
Priority date: 2001-02-15
Filing date: 2001-02-15
Publication date: 2005-09-07
Anticipated expiration: 2021-02-15
Also published as: CN1369985A

Abstract

The present invention discloses a multi-progression event synchronizing device and a system thereof, which mainly aims at reducing the cost of hardware of a synchronous circuit used for balancing the unequal working frequency of a source region and a destination region. The device combines a party with slower working frequency and an exclusive OR gate by a multi-progression simple synchronous circuit for receiving input signals which are transmitted by a party whose working frequency is higher and generating corresponding event numbers. Thus, the signals which are transmitted by the party whose working frequency is higher can not be missed by the party whose working frequency is lower.

Description

The event synchronization device and the system thereof of multistage number

Technical field

The invention relates to a kind of event synchronization device and system thereof, particularly do not wait or operating frequency equates but in the data transmission procedure in zone, a source place that phase place does not wait and zone, destination, cushions the transmission of these data with the event synchronization Apparatus and system of a multistage number in operating frequency about a kind of.

Background technology

In the design process of digital circuit, often because the operating frequency in the zone, source place (origination agent) of transfer of data and zone, destination is different or operating frequency is identical but phase place does not wait, cause an end to pick up the data that the other end directly imports into and form mistake in the mode of edge-triggered.Fig. 1 is the schematic diagram of transfer of data, wherein comprises a relaying zone 11 between zone 14, the source place of data and zone, destination 15, is used to cushion the transmission data in this zone 14, source place and zone, destination 15.This relaying zone 11 comprises a first in first out module (FIFO) 12 and a control module 13, and wherein this first in first out module 12 is a dual-port structure, is connected to this zone 14, source place and zone, destination 15 with data/address bus 18 and 18 ' respectively; And this control module 13 is to be connected to this zone 14, source place and zone, destination 15 with control bus 19 and 19 '.Between this first in first out module 12 and the control module 13 with a storage interface (producing interface) 16 and one fetch interface (consuming interface) 17 as linking.The operational mode of the structure of Fig. 1 has two kinds, first kind of situation is that this zone, source place 14 is imported data into to this first in first out module 12 via this data/address bus 18, another kind of situation is this first in first out module 12 is read in this zone, destination 15 via this data/address bus 18 ' a storage data, under first kind of situation, this zone, source place 14 notifies this control module 13 will have data to import into via control bus 19, and whether this control module 13 checks the spill-over of this first in first out module 12 via this storage interface 16 earlier.If spill-over, then this control module 13 notifies this zone, source place 14 temporarily not import data into to this first in first out module 12 via this control bus 19.If not spill-over as yet, then this control module 13 notifies this zone, source place 14 to import data into this first in first out module 12 via this control bus 19, and the position when upgrading next record data and import into via this storage interface 16.Under second kind of situation, this control module 13 is notified via control bus 19 ' in this zone, destination 15, and this control module 13 checks via this fetch interface 17 whether this first in first out module 12 is vague and general earlier.If vague and general, then this control module 13 notifies this zone, destination 15 temporarily not read this first in first out module 12 via this control bus 19 '.If not vague and general as yet, this control module 13 data of notifying this zone, destination 15 to read this first in first out module 12 via this control bus 19 ' then, and the position when upgrading next record data reads via this fetch interface 17.

Fig. 2 is the structure chart of the first in first out module known, wherein mainly comprises one and stores end 28, and read end 27 and one first-in first-out buffer 29.This storage end 28 comprises a storage module 24 and first counter 22, and is connected to this and is close to and deposits interface 16 and this first-in first-out buffer 29.This storage module 24 is used to produce the position of a rear end pointer with the present data storing of pointing to this first-in first-out buffer 29, and this first counter 22 is a two-way counter, the number that is used for the data buffering of this first-in first-out buffer 29 of accumulative total, this reads end 27 and comprises a read module 21 and second counter 23, be connected to this fetch interface 17 and this first-in first-out buffer 29, this read module 21 is used to produce the position of a front end pointer with the present data read of pointing to this first-in first-out buffer 29, and this second counter 23 is a two-way counter, is used for the number of the data buffering of this first-in first-out buffer 29 of accumulative total.When this storage end 28 carries out one when pushing incident (push event), when promptly this zone, source place 14 desired to deposit in data to this first-in first-out buffer 29, this stored the value that end 28 is checked this first counter 22 earlier.If its value has reached in the storage of this first-in first-out buffer 29 in limited time, represent this first-in first-out buffer 29 spill-over, then send one " overflow status ", its result for the regional 14 notified storage datas that will temporarily stop in this source place to this first-in first-out buffer 29.If unequal, promptly do not reach the storage upper limit, then this storage module 24 sends this rear end pointer to this first-in first-out buffer 29, and the data in this zone, source place 14 promptly are stored in the position of holding pointer to set after this first-in first-out buffer 29.At this moment, 23 in this first counter 22 and this second counter add the quantity of these zone, source place 14 stored data.Identical principle, when this reads end 27 when carrying out a release incident (pop event), promptly desire when this first-in first-out buffer 29 reads data in this zone, destination 15, and this reads the values that end 27 is checked these second counters 23 earlier.If having reached the storage of this first-in first-out buffer 29, its value prescribes a time limit down, represent this first-in first-out buffer 29 vague and general, then send one " vague and general state ", its result is these zone, destination 15 notified will temporarily stopping from this first-in first-out buffer 29 reading of data, if it is unequal, promptly do not reach the storage lower limit, then this read module 21 sends this front end pointer to this first-in first-out buffer 29, and zone, this destination 15 data that will read promptly are positioned at the position that the front end pointer of this first-in first-out buffer 29 sets.At this moment, this

first counter

22 and 23 in this second counter deduct the quantity of these zone, destination 15 data streams reads.The function class of this first counter 22 and second counter 23 seemingly, so can omit one of them.But because this second counter 23 is to read end 27 in order to control, and this first counter 22 is to store end 28 in order to control, and is for the factor of modularized design, still preferable with both and the mode of depositing.

Fig. 3 is the first-in first-out buffer structure of knowing, this first-in first-out buffer 29 is to be used to store and transmit the data that this zone, source place 14 passes to this zone, destination 15, though particularly unequal or operating frequency equates but phase place when not waiting when the operating frequency in zone 14, this source place and this zone, destination 15, one inlet of this first-in first-out buffer is represented with " * ", represent this inlet to store useful data, and this rear end pointer 32 and front end pointer 31 are represented the starting point and the final position of these a plurality of useful datas respectively.When one pushed the incident generation, this rear end pointer was checked its value earlier if add the value that whether equals this front end pointer 31 after.If answer is sure, represent this first-in first-out buffer 29 spill-over.Otherwise represent not spill-over, and this rear end pointer 32 position of advancing, promptly add one.When a release incident took place, this front end pointer 31 checked earlier whether its value equals the value of this rear end pointer 32.If answer is sure, represent this first-in first-out buffer 29 vague and general.Otherwise represent not vague and generally, and this front end pointer 31 position of advancing promptly adds one.The progression value of this rear end pointer 32 and front end pointer 31 is to calculate in the mode of modulus (modulo).With Fig. 3 totally 16 positions be example, after the value of this rear end pointer 32 and front end pointer 31 accumulative total is to 15, next accumulative total position will begin to calculate by 0.

Though structure shown in Figure 2 can not be applicable to unequal or equate but the situation of out of phase is arranged when the operating frequency in zone 14, this source place and zone, destination 15.In this case, with the number that causes this first counter 22 to judge the number of this release incident that reads end 27 by accident and cause the 3rd counter 23 to judge the incident that pushes of this storages end 28 by accident.Therefore, the corresponding synchronous circuit should be added into to guarantee the correctness of this system when moving.

Fig. 4 be ripe and a circuit structure, what comprise the lower clock signal DCLK (purpose clock zone) of the storage circuit 47 of the higher clock signal SCLK of an operating frequency (source clock) and an operating frequency reads circuit 48.This storage circuit 47 comprises one first buffer 41 and a logic clusters 42.This reads circuit 48 inside two data paths, and wherein first data path comprises one second buffer 43 and the 4th buffer 45, and it is output as 406; And second data path comprises one the 3rd buffer 44 and the 5th buffer 46, and it is output as 407.

Fig. 5 is the sequential chart of Fig. 4, because the phenomenon of clock skew may appear in this circuit, therefore supposes that the clock signal 402 of first data path that this reads circuit 48 and the clock signal 403 of second data path have a deviant on phase place.If the output 401 of this storage circuit 47 just changes state at the rising edge of clock signal 402 that this reads first data path of circuit 48,43 pairs of this second buffers are provided with and the definition of retention time owing to do not satisfy, therefore will produce the pulse of picking up of a failure at the output 404 of this second buffer, this phenomenon is called metastable condition.Relatively, lag behind the clock signal 402 of this first data path because of clock skew because of the clock signal 403 of this second data path, therefore can satisfy being set up and the definition of retention time of the 3rd buffer 44, and make the 3rd buffer 44 can correctly pick up the variation of the output 401 of this storage circuit 47.Via the difference of the sequential of this first data path and second data path relatively, can find time point, the output 406 of the 4th buffer and the output of the 5th buffer 407 and inconsistent at 1T.But behind the time point of 2T beginning both will be consistent, in other words, after through two clock cycle, this output that reads circuit 48 can filter out metastable condition and right value occur.But even so, the circuit of Fig. 4 is only applicable to the pattern that triggers picks up data with level, and the pulse duration of promptly importing data must be greater than the pulse duration of clock signal SCLK and DCLK, and can't be applicable to the pattern with the edge-triggered picks up data.

Fig. 6 is used to explain the reason that can't be applicable to edge-triggered as the structure of Fig. 4.The operating frequency that is higher than the clock signal DCLK in this zone, destination 15 because of the operating frequency of the clock signal SCLK in this zone, source place 14, if this storages end 28 and reading holds 27 all in the rising edge of SCLK and the DCLK mode picks up data with edge-triggered, then for this storage end 28 a plurality of push incident, this storages holds 28 to make edge-triggered and picked up altogether 3 times with the rising edge of clock signal SCLK.Relatively, this reads end 27 and makes edge-triggered and only picked up once with the rising edge of clock signal DCLK.Aforesaid way is called simple synchronization, promptly directly picks up the increase number of the incident that pushes of this storage end with this clock signal DCLK that reads end 27; Or directly hold 28 clock signal SCLK to pick up the increase number that this reads the release incident of end with this storage, pick up two operating frequencies in the mode of a simple synchronization and do not wait the data in zone to make the mistake.

The above-mentioned operating frequency because of zone, source place and zone, destination of another kind of solution is not equal to cause picks up wrong solution in U.S. Patent number 6,055,285, title is that " SYNCHRONIZATION CIRCUIT FOR TRANSFERRING POINTERBETWEEN TWO ASYNCHRONOUS CIRCUITS " is disclosed.This method is to utilize the address bus that writes of one first synchronous circuit to connect a writing controller and a first-in first-out buffer, connects a Read Controller and utilize one of this first synchronous circuit to write pointer synchronously; And a read address bus that utilizes one second synchronous circuit connects this Read Controller and this first-in first-out buffer, and utilizes a synchronous reading pointer of this second synchronous circuit to connect this writing controller.Though the operating frequency that this method can solve because of zone, source place and zone, destination does not wait the problem that causes picks up data number mistake, but because of using one to write address bus, read address bus, reading pointer and write pointer synchronously synchronously simultaneously, so hardware spending is very big.

Summary of the invention

Though the objective of the invention is not to wait or equate but the excessive shortcoming of hardware spending of the synchronous circuits that each other phase place difference is used for reducing at present operating frequency for balance zone, one source place and zone, destination.In order to achieve the above object, the invention provides a kind of event synchronization device of multistage number.This device side that operating frequency is slower receives the event number that the higher side of operating frequency is transmitted with the simple synchronization circuit of multistage number and XOR gate combination.Thus, the side that this operating frequency is lower is the signal that unlikely leakage is transmitted by the higher side of this operating frequency.

The primary and foremost purpose of apparatus of the present invention is to set up a synchronous interface, allows this storage end 28 know that at present this reads the number of the performed release incident of end 27, and allows this read end 27 to know at present the number of should storage holding the 28 performed incidents that push.This reads end 27 and reads in the end 28 respectively has one to add/down counter, can correctly calculate the variation of the data buffering number in this first-in first-out buffer 29.Reached the upper limit if find the number of the data buffering of this first-in first-out buffer 29, then sent the information of one " spill-over ", and suspended this storage and hold 28 to import data again into.Reached lower limit if find the number of the data buffering of this first-in first-out buffer 29, then sent the information of one " vague and general ", and suspended this and read end 27 reading of data again.

Another object of the present invention is to avoid because of phase deviation at this storage end and read and cause metastable state when end picks up the incident of pushing or the incident of release in the edge-triggered mode.

The invention provides a kind of event synchronization device, wherein comprise: a progression generation unit, be used to produce the coding of a value of series, wherein this value of series is greater than the pulse length of the clock signal of the first area integer divided by the pulse length of the clock signal of a second area; One event configuration unit is connected to this progression generation unit, and the number mean allocation that is used for the incident that this second area is performed is in this value of series level data path; And a synchronous unit, be connected to this event configuration unit, comprise at least one D flip-flop, the number that is used to the incident on this value of series level data path of changing is the event number that the clock signal of this first area can be picked up.

The event synchronization device of multistage number of the present invention comprises one first event synchronization device, one second event synchronization device, one second counter and one first counter.This first event synchronization device is used for the event number that a clock signal that number with zone, this destination data streams read is converted to this zone, source place can pick up.This second event synchronization device is used for the event number that a clock signal that number with the stored data in zone, this source place is converted to this zone, destination can pick up.When data were whenever read in this zone, destination, the value of this second counter subtracted one.When this second event synchronization device was whenever sent into an incident, the value of this second counter added one.Prescribe a time limit when the following of data buffering number that the value of this second counter equals this relaying zone and can provide, then send a vague and general signal.When data of this source place every storage in zone, the value of this first counter adds one.When this first event synchronization device was whenever sent into an incident, the value of this first counter subtracted one.Can carry the going up of data buffering number of flood and prescribe a time limit when the value of this first counter equals this relaying zone, then send a spill-over signal.

This second event synchronization device comprises a progression generation unit, an event configuration unit and a synchronous unit, this progression generation unit is used to produce the coding of one-level numerical value of N, and wherein N is greater than the pulse length of the clock signal in this zone, destination integer divided by the value of the pulse length of the clock signal in this zone, source place.This event configuration unit is connected to this progression generation unit, is used for number mean allocation with the stored data in zone, this source place in the data path of N level.This lock unit is connected to this event configuration unit, if the number that any paths has the stored data in zone, this source place in this N level data path, then is converted to the event number that the clock signal in this zone, destination can be picked up.

This first event synchronization device comprises a progression generation unit, an event configuration unit and a synchronous unit.This progression generation unit is used to produce the coding of a value of series M, wherein M is greater than the pulse length of the clock signal in this zone, source place integer divided by the value of the pulse length of the clock signal in this zone, destination, this event configuration unit is connected to this progression generation unit, be used for number mean allocation with zone, this destination data streams read in the data path of M level, this lock unit is connected to this event configuration unit, if any one all has the number of this zone, destination data streams read in this M level data path, then be converted to the event number that the clock signal in this zone, source place can be picked up.

The event synchronization system of multistage number of the present invention is used to cushion the transfer of data in zone, a source place and zone, destination, and wherein this zone, source place and zone, destination have unequal operating frequency or have equal operating frequency but the phase place that does not wait is arranged.The event synchronization system of this multistage number comprises event synchronization device, a read module, a storage module and a control module of a first-in first-out buffer 29 1 multistage numbers.This first-in first-out buffer has an input and an output, and this input is connected to a data/address bus in this zone, source place, and this output is connected to a data/address bus in this zone, destination.The event synchronization device of this multistage number is used for the data buffering number of this first-in first-out buffer of accumulative total, this device is that the number with zone, this destination data streams read is converted to the event number that the clock signal in this zone, source place can pick up, and the number of the stored data in zone, this source place is converted to the event number that the clock signal in this zone, destination can pick up, if the number of the stored data in zone, this source place has reached the upper limit after deducting the event number that a clock signal that the number of these stored data in zone, destination is converted to this zone, source place can pick up, then this device sends a spill-over signal, if the number of the stored data in zone, this source place has reached lower limit after being converted to the number that event number that a clock signal in this zone, destination can pick up deducts this zone, destination data streams read, then this device sends a vague and general signal, this read module is used to produce the position of a front end pointer with the data that are read of pointing to this first-in first-out buffer, this storage module is used to produce the position of a rear end pointer with the data that are stored of pointing to this first-in first-out buffer, and this control module is used to control this first-in first-out buffer, the transfer of data in zone, source place and zone, destination.When this spill-over signal takes place, then stop the data storing in this zone, source place, when this vague and general signal takes place, then stop the data read in this zone, destination.

The accompanying drawing summary

Fig. 1 is the event synchronization schematic representation of apparatus of knowing;

Fig. 2 is the schematic diagram of the first in first out module known;

Fig. 3 is the schematic diagram of the first-in first-out buffer known;

Fig. 4 is a simple synchronization circuit structure of knowing;

Fig. 5 is the sequential chart of Fig. 4;

Fig. 6 is the reason that the structure that is used for key-drawing 4 can't be applicable to edge-triggered;

Fig. 7 is multistage several event synchronization schematic representation of apparatus of the present invention;

Fig. 8 is one embodiment of the invention;

Fig. 9 is the sequential chart of Fig. 8;

Figure 10 is an another embodiment of the present invention; And

Figure 11 is the sequential chart of Figure 10.

Embodiment

Fig. 7 is multistage several event synchronization schematic representation of apparatus of the present invention.With Fig. 2 know technology different be that the present invention has increased by the one first event synchronization device 71 and the second event synchronization device 72 in addition.This first event synchronization device 71 is used for this number that reads the end 27 release incidents that increased is converted to the equal amount that the clock signal SCLK (also being equal to the clock signal in zone, source place 14) that stores end 28 can edge-triggered picks up.The value representation of the renewal of first counter 22 is the number of buffered data in this first-in first-out buffer at present, and its by deducting the synchronous release incident of sending from this first event synchronization device 71 number and by being increased in the incident that pushes that is performed in the source region to be updated.This first counter 22 checks earlier that when the incident that at every turn pushes takes place the situation whether spill-over is arranged takes place, if the situation of no spill-over then increases progressively according to pushing the number of incident.This second event synchronization device 72 is used for this storage end 28 incident that pushes numbers that increased are converted to the relative populations that the clock signal DCLK (also being equal to the clock signal in zone, destination 15) that reads end 27 can edge-triggered picks up.The updating value of second counter 23 is represented the number of the buffered data in present this first-in first-out buffer 27, and it is by the number that increases the synchronous incident of sending from this second event synchronization device 72 that pushes and is increased in the release incident of carrying out in the zone, destination and is updated.Whether this second counter 23 is checked when each release incident takes place has vague and general situation to take place, if no vague and general situation then increases progressively according to the number of the incident of release.Multistage several event synchronization devices 70 of the present invention are to comprise this first event synchronization device 71, the second event synchronization device 72, first counter 22 and second counter 23.Be different from U.S. Patent number 6,055,285 know technology, this first event synchronization device 71 and the second event synchronization device, 72 only transmission incidents push the number of the incident and the incident of release, but not as this know must use as the technology one write address bus, read address bus, reading pointer and write pointer synchronously, so hardware spending is synchronously known technology than this and is saved many.

Suppose to store the operating frequency of the operating frequency of the clock signal SCLK that holds greater than the clock signal DCLK that reads end, the data that promptly store end 28 produce speed greater than reading 27 consumable speed of end.In this case, must in this second event synchronization device 72, increase multiple data paths.Disperse and buffering is held accelerating of 28 the incident that pushes from this storages.

Fig. 8 is one embodiment of the invention, wherein suppose this storage end 28 clock signal SCLK operating frequency and be no more than 3 times of operating frequency of this clock signal DCLK that reads end 27, therefore can utilize a progression (stage) generation unit 81 that is positioned at this second event synchronization 72 to remove 3 and encode to produce one.This progression generation unit 81 comprises JK flip-flop (flip-flop) 82 and 83, is respectively applied for to produce CNT0 and its complement CNNT0NN, and CNT1 and its ones complement CNT1NN.

Fig. 9 is the sequential chart of Fig. 8.If with the value that can obtain behind the value of CNT0 and the CNT1 coding by 0 to 2 continuous circulation.In other words, the circuit of Fig. 8 is to remove 3 counter for producing one.

Figure 10 is an another embodiment of the present invention, wherein comprise an event configuration unit 91 and a lock unit 92 that is positioned at this second event synchronization device 72, it (is the input of the second event synchronization device 72 of Fig. 7 that this event configuration unit 91 is used to make up an input signal, that is the number of this storage end 28 incidents that push that increased) and the CNT1 of the progression generation unit 81 of Fig. 8, the value of CNT0NN and CNT1NN holding wire, and will be scattered in the input 901 in three data paths in regular turn by this input signal, 902 and 903, its sequential chart as shown in figure 11, in other words, the output of this progression generation unit 81 is the clock datas as this event configuration unit 91.Because the operating frequency of the clock signal SCLK of this storages end 28 also is no more than this and reads 3 times of the operating frequency of holding 27 clock signal KCLK, therefore three data paths should be enough to receive the incident that the pushes increase number that this storage end 28 is imported, and unlikely generation leakage.In other words, pick up input signal by this clock signal DCLK that reads end 27 in the mode of edge-triggered, as long as store below three times of operating frequency that the operating frequency of end 28 guarantees to read at this end 27, just be equivalent to read end 28 receives this storages end 27 with three less circuits of flow the flow data of circuit greatly at this, when receiving, can not produce the situation of leakage and make this read end 27, this lock unit 92 comprises three data paths, be used for producing and be positioned at 901,902 and 903 signal click triggering (one shot) signal 907,908 and 909, three data paths of this lock unit 92 are to be one to remove 3 encoder for cooperating this event configuration unit 91, the number of this data path can change with the ratio of the pulse length of DCLK and SCLK, and the present invention does not impose any restrictions this.Arbitrary data path all comprises one first D flip-flop 911, second D flip-flop 912, the 3rd D flip-flop 913 and an XOR gate 914, wherein the input of the clock of this first to the 3rd D flip-flop 911～913 all is connected to the clock signal DCLK in zone, destination 15, and this XOR gate 914 is to click signal for generation.The output 907～909 of this lock unit 92 is the output of the second event synchronization device 72 of Fig. 7, and is connected to this read module 21 and second counter 23.This second counter 23 is received whenever that output 907～909 arbitrary of this second event synchronization device 72 clicks all to carry out behind the signal and is added one action.

Figure 11 is the sequential chart of Figure 10.Wherein show the number of times that on behalf of this input signal, the summation of clicking signal of the output 907,908 utilize this

lock unit

92 and 909 can intactly picked up in the edge-triggered mode by the rising edge of clock signal SCLK at this storages end 28, and successfully be converted to this and read the number of times of holding 27 energy identifications and the leakage that does not have data.

The pulse length of supposing the clock signal SCLK of this storage end 28 is T _Sclk, and this pulse length that reads the clock signal DCLK of end 27 is T _Dclk, progression N then of the present invention, promptly the producing method of the number of the data path of this lock unit 92 is shown in equation (1):

N＞T _dclk/T _sclk (1)

T for example _DclkDivided by T _SclkValue be 2.3, then the progression N of this second event synchronization device 72 selects 3 grades to get final product.It should be noted that if T _DclkDeng T _SclkValue, for fear of the situation that has phase place not wait between the two, the progression of this second event synchronization device 72 is still to select two-stage to be advisable.In addition in the circuit normal occur because of being provided with and retention time deficiency, clock skew or signal jitter caused reads end 27 and store the stationary problem of end 28, utilize the simple synchronization circuit of first to the 3rd D flip-flop 911～913 of this lock unit 92 to be solved.

This first event synchronization device 71 can also above-mentioned mode design, and wherein the producing method of progression M is shown in equation (2):

M＞T _sclk/T _dclk (2)

T for example _SclkDivided by T _DclkValue be 0.7, then the progression M of this first event synchronization device 71 selects 1 grade to get final product.It should be noted that if T _DclkEqual T _SclkValue, for fear of the situation that has phase place not wait between the two, the progression of this first event synchronization device 71 is still to select two-stage to be advisable.

In addition, the above embodiments suppose that all the operating frequency of this storage end 28 reads the operating frequency of end 27 greater than this.But for opposite situation, promptly this reads the situation of the operating frequency of end 27 greater than the operating frequency of this storage end 28, and also applicable according to the principle that the present invention is indicated, the present invention does not have any restriction to this.

Technology contents of the present invention and technical characterstic are open as above; yet the scholar that goes into who is familiar with this technology still may be based on content of the present invention and open and do all replacement and modifications that does not deviate from spirit of the present invention; therefore; it is disclosed that protection scope of the present invention should be not limited to embodiment; and should comprise various do not deviate from replacement of the present invention and modifications, and contained by following claim scope.

Claims

1, a kind of event synchronization device is characterized in that comprising:

One progression generation unit is used to produce the coding of a value of series, and wherein this value of series is greater than the pulse length of the clock signal of the first area integer divided by the pulse length of the clock signal of a second area;

One event configuration unit is connected to this progression generation unit, and the number mean allocation that is used for the incident that this second area is performed is in this value of series level data path; And

One synchronous unit is connected to this event configuration unit, comprises at least one D flip-flop, and the number that is used to the incident on this value of series level data path of changing is the event number that the clock signal of this first area can be picked up.

2. event synchronization device as claimed in claim 1 is characterized in that any paths comprises in this value of series level data path:

One first D flip-flop is connected to the output of this event configuration unit;

One second D flip-flop is connected to the output of this first D flip-flop;

One the 3rd D flip-flop is connected to the output of this second D flip-flop; And

One XOR gate is connected to the output of this second D flip-flop and the 3rd D flip-flop, is used to produce this incident.

3. event synchronization device as claimed in claim 1 is characterized in that described first area is the purpose zone, and second area is for coming source region.

4. the event synchronization device of a multistage number, be used for number in the relaying zone of the transfer of data that cushions a first area and second area cumulative data buffering, this first area and second area have the operating frequency that does not wait or have equal operating frequency but the phase place that does not wait is arranged, and it is characterized in that comprising:

The one first event synchronization device as claimed in claim 1 is used for the event number that a clock signal that number with the performed incident of this second area is converted to this first area can pick up;

The one second event synchronization device as claimed in claim 1 is used for the event number that a clock signal that number with this performed incident in first area is converted to this second area can pick up;

One second counter, its value subtracts one when every execution one incident of this second area, the following number of the synchronous incident sent of its this second event synchronization device of value increase then in limited time that equals data buffering number that this relaying zone can provide when the value of this second counter, and send a vague and general signal; And

One first counter, its value adds one when every execution one incident in this first area, when the value of this first counter equals the number of going up in limited time the synchronous incident that its this first event synchronization device of value minimizing then sends of data buffering number that this relaying zone can provide, and send a spill-over signal.

5, a kind of event synchronization system of multistage number is used to cushion the transfer of data of a first area and second area, and this first area and second area have the operating frequency that does not wait or have equal operating frequency but the phase place that does not wait is arranged, and it is characterized in that comprising:

One first-in first-out buffer has an input and an output, and this input is connected to this first area with a data/address bus, and this output is connected to this second area with a data/address bus;

The event synchronization device of one multistage number as claimed in claim 4 is used for the totally data buffering number of this first-in first-out buffer; One read module is used to produce a front end pointer to point to the position that is read data at present of this first-in first-out buffer;

One storage module is used to produce a rear end pointer to point to the position that is stored data at present of this first-in first-out buffer; And

One control module is used to control the transfer of data of this first-in first-out buffer, first area and second area, then stops the data storing of this first area when this spill-over signal takes place, and then stops the data read of this second area when this vague and general signal takes place.