CN1218484C - Buffer with compensating drive strength - Google Patents
Buffer with compensating drive strength Download PDFInfo
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- CN1218484C CN1218484C CN01814618XA CN01814618A CN1218484C CN 1218484 C CN1218484 C CN 1218484C CN 01814618X A CN01814618X A CN 01814618XA CN 01814618 A CN01814618 A CN 01814618A CN 1218484 C CN1218484 C CN 1218484C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
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Abstract
A compensating buffer providing both course tuning on initialization and fine-tuning during operation is disclosed. The course tuning is provided by a plurality of binary-weithed driver legs which are selected during initialization. The fine-tuning which is selectable during both initialization and during operation is provided through linear-weighted biasing. The linear-weighted biasing is simplified through the use of a digital-to-analog converter.
Description
Technical field
The present invention relates to be used for the compensating buffer field of integrated circuit.
Background technology
Along with PC and other use the system of integrated circuits complicated day by day, also urgent day by day to the needs of the output driver of precision.Drive the signal of 100MHz or higher frequency on often need the be long trace of integrated circuit several inches of printed circuit board.These traces make transfer of data very difficult as transmission line, unless the impedance of buffer can compensate the characteristic of transmission line.Need the buffer of compensation to also have other reasons, for example, temperature and voltage change, cause the characteristic changing of buffer when circuit working.
Known many compensation output buffers, for example United States Patent (USP) 5578971; 5528166; Shown in 4975598 and 4768170.
Application USSN:09/299771 (the submission date 4/26/99 of awaiting the reply at the same time, exercise question is " Method and Apparatus for Dual Mode Output Buffer ImpedanceCompensation " (transferring the application's assignee)) in, a kind of buffer that has for the binary system that resets or select during initialization-weighting compensation driver lead-in wire is disclosed.Use and to draw on the outside or pull down resistor need just can determine those drivers to go between.As what will be appreciated that, the present invention is based upon on the basis of the buffer described in the above-mentioned application.
Summary of the invention
According to a kind of buffer that is used for integrated circuit of the present invention, it comprises: first group of optional device, and in order to output signal to be provided, described output signal has by determined first strength range of the number of the optional device of choosing; Drive circuit, it comprises the transistor that is connected to described first group of optional device, in order to the scalable intensity of output signal to be provided in second strength range, wherein, described second scope is setovered to described transistor by the signal with numerical value at least three numerical value less than described first scope; And, be connected to the control circuit of described first group of optional device and described drive circuit, wherein, described control circuit comes the described optional device of described selection by the device of selecting first group of a certain number in the optional device when described integrated circuit initialization, and the described output signal strength of described control circuit regular monitoring, if described output signal needs compensation, then regulate described drive circuit by regulating described biasing.
According to a kind of buffer that is used for integrated circuit of the present invention, it comprises: a plurality of drive units, when described integrated circuit initialization, select some drive units in described a plurality of drive unit; The drive circuit of drive signal is provided, and described drive signal is used for regularly finely tuning the output intensity of described buffer when work, and the increment of described fine setting is significantly less than the increment that is provided by described drive unit; And, be connected with described drive unit selecting described drive unit and to be connected with described drive circuit controlling the control circuit of described drive circuit, described control circuit is monitored the output intensity of described buffer and is controlled described drive circuit the variation of described output intensity is responded.
According to a kind of method that is used for the buffer of control integrated circuit of the present invention, it comprises: select the output device of a certain number, so that provide predetermined output intensity according to described buffer output when initialization; And, when working, described buffer utilize the analog signal that produces to finely tune described output intensity, simultaneously, to compare with the intensity increment that described output device provides, and the change of described output intensity is limited to less relatively change.
According to the method for the output intensity of a kind of controller buffer of the present invention, it may further comprise the steps: by selecting drive unit to provide when the initialization trend of output area is regulated; Provide regular fine setting according to monitoring, wherein utilize an analog bias signals of adjusting the electric current in the transistor to control described fine setting described output area to described output intensity; And selectable described fine setting is restricted to the gamut less than described fine setting during with initialization.
Description of drawings
Fig. 1 is the electrical schematic diagram that buffer of the present invention and being used for is controlled the control circuit of described buffer operation.
Fig. 2 is used for providing for fixing (anchor) lead-in wire of control chart 1 buffer the electrical schematic diagram of the digital-to-analog converter (DAC) of offset signal.
Fig. 3 A is used for illustrating that binary weighting (BW) drives the relative intensity between the lead-in wire and the sketch of the intensity that provided by linear weighted function (LW) offset signal.
Fig. 3 B is used for illustrating typical B W initial strength and the sketch of the additional strength that provided by the LW offset signal.
Fig. 4 illustrates the method for operating that is used for buffer of the present invention.
Embodiment
The compensating buffer that is used for integrated circuit is disclosed.In order to understand the present invention more thoroughly, many concrete details have been proposed in the following description, for example concrete pin count etc. in the buffer.Clearly also can realize the present invention to the professional and technical personnel without these details.In other examples, known circuit just no longer is described in detail such as digital-to-analog converter (DAC), in order to avoid unnecessarily blured explanation of the present invention.
At first consult Fig. 1, shown in buffer lead-in wire comprise many binary weighting (BW) output drivers lead-in wires as compensation.These lead-in wires provide the trend (course) of output signal strength to regulate.For example, " height " turn-on transistor 34 and " low " turn-on transistor 40 provide maximum intensity (for example 8x), and simultaneously, transistor 36 and 38 provides minimum strength (for example 1x).In a typical embodiment, can use four BW lead-in wires, their relative intensity is shown in Fig. 3 A.Should be pointed out that transistor 34 or 40 provides intensity 73 for the 4th lead-in wire among Fig. 3 A, and for article one lead-in wire, transistor 36 or 38 provides intensity 70.The difference of intensity can provide by selecting the resistance value in transistorized size or these lead-in wire or the combination of transistor size and resistance value.These resistance of known use can make the V-I characteristic of buffer more linear.This just helps quality of signals, particularly when high data rate.But also knownly can use transistorized composite combined with linear characteristic.Like this, each " height " turn-on transistor and " low " turn-on transistor can be taken into account one or more transistors.(transistorized composite combined and use resistance also can be used for the voltage-controlled lead-in wire of LW, discuss below).
As described in above-mentioned patent application, when the integrated circuit initialization, select some BW lead-in wires so that required intensity to be provided.The control circuit that in above-mentioned application, describes in detail 30 use that two counters provide that indication needs on draw binary signal with pull-down strength.In one embodiment, select the quantity of required " height " turn-on transistor on the line 41 by four signals of forming (PENB).Four on the line 42 provide the signal that is used for selecting required " low " turn-on transistor.
Each bar line 41 be connected to " or " (OR) door, as OR door 33 and 35.Other terminals of OR door receive P drive signal (PDRV).The output of OR door is connected to " height " turn-on transistor, and specifically, the output of OR door 33 is connected to the grid of p-channel transistor 34, and the output of OR door 35 is connected to the grid of P-channel transistor 36.Though should be pointed out that and use the OR door, also can use other logical circuits to drive " height " turn-on transistor.
In like manner, each bar line 42 be connected to " with " (AND) door, as AND door 37 and 39.Other terminals of AND door receive N drive signal (NDRV) from line 14.The output of AND door is connected to the n-channel transistor in the BW lead-in wire; Specifically, the output of AND door 37 is connected to the grid of transistor 38, and the output of AND door 39 is connected to the grid of transistor 40.Should also be noted that and to use other logical circuits to drive " low " turn-on transistor.
In the integrated circuit initialization or when resetting, control circuit 30 provides the binary signal of representing desirable strength.These signals are selected suitable output driver.Circuit 30 utilizes one or more non-essential resistances (for example resistance 31) and reference potential to estimate output intensity, as described in above-mentioned application.
The BW output lead provides the relative trend of output intensity to regulate (course tuning).Even the driver with minimum active strength also can be done bigger adjusting to the output intensity of buffer.Therefore, when working, buffer select the BW lead-in wire will cause the error of input once more.Usually, terminal installation does not know that when input signal is changing, thereby also not know when to improve intensity be safe.As described below, the invention provides the fine setting that can when buffer is worked, carry out.
The buffer of Fig. 1 comprises fixing (anchor) lead-in wire 15, and the latter provides the output signal of certain level and the Anhui musical styly is provided when using compensation not.Even at non-selected BW lead-in wire and when LW offset signal " disconnection ", described lead-in wire also provides output signal to pad (pad) 10.Therefore, when making the buffer output signal, " height " turn-on transistor 18 and " low " turn-on transistor 19 always provide certain output signal.These transistors receive p by phase inverter 16 and 17 respectively and drive and the n drive signal.Anchor leg 15 also comprises p-channel transistor 21 and n-channel transistor 22 in addition.These transistors receive offset signal respectively on circuit 24 and 25, they provide the fine setting to output signal.There is not the driving from anchor leg 15 in (PDRV height, NDRV is low) when buffer is in receive mode, and buffer has high input impedance.
When buffer is worked, at first select the BW lead-in wire of right quantity, can select the combination of any " height " conducting or " low " turn-on transistor.The intensity of regular monitoring output signal then, is need to determine whether ancillary relief.For example, after initialization, every several microseconds, control circuit 30 just utilizes and be used to provide the identical mechanism of PENB and NEN signal that similar binary signal is provided on circuit 43 and 44.Be used for being used for once more on circuit 43 and 44, providing signal at pull-up counter that signal is provided on circuit 41 and 42 and pull-down counter.These counters and operating in the above-mentioned application of they have detailed description.In one embodiment, circuit 43 and 44 provides separately with four shown in the form of SELN signal (circuit 43) and SELP signal (circuit 44).
SELN signal and SELP signal can be controlled the independent transistor that is used to finely tune separately.But this may be a kind of comparatively expensive implementation, because each transistor all needs an independent driver.Not as using storbing gate (pass gate) digital-to-analog converter (DAC) among the embodiment shown in the image pattern 2.
Now consult Fig. 2, each DAC realizes with a plurality of resistance and a multiplexer in the lead-in wire 55.Lead-in wire 55 is connected between transistor 52 and 53, and it comprises first group of series resistance that is connected to MUX50 and the second group of series resistance that is connected to MUX51.In one embodiment, 16 resistance that are connected to MUX50 and 16 resistance that are connected to MUX51 are arranged.Transistor 52 and 53 is by the VbiasEn signal enabling on the circuit 60, and circuit 60 is connected to transistor 53 and is connected to transistor 52 by phase inverter 61.Signal on the circuit 60 allows by disconnecting " height " turn-on transistor 56 circuit 25 to be connected with the power supply potential disconnection, and allows to make no longer ground connection of circuit 24 by disconnecting transistor 57, because the grid of transistor 57 is connected to phase inverter 61.The upper limit of power range is used for NBIAS, and lower limit is used for PBIAS, make the even classification of voltage produce the transistor 21 of Fig. 1 and the approximate even classification of 22 intensity.Use the advantage of the voltage of the most approaching full amplitude power source current potential to be that noise is had bigger anti-interference power, not so noise can cause the change of buffer strength.
Storbing gate (pass gate) transistor that binary signal on the circuit 43 makes MUX50 choose in 16 resistance an ohmically current potential to be used for by MUX50 is connected to circuit 25.So the current potential of circuit 25 is exactly in 16 classifications, begins with the potential minimum on maximum potential on the terminal F and the terminal 0.In like manner, MUX51 is by being connected to a terminal in 16 terminals 0 to 16 select to go between in 55 a current potential in 16 current potentials of circuit 24.This also is to finish by the storbing gate transistor among the MUX51.Like this, the signal on the circuit 24 and 25 is actually " simulation ", because each signal all has one of 16 numerical value, and the difference between each classification equates.For example, each classification that equates can be between 20 to 50mV.
The resistance of Fig. 2 and the function of DAC can realize with other modes.For example, can use two independent and overlapping resistance string, or use single resistance string but overlapping tap is arranged.
Get back to Fig. 1, the PBIAS current potential on the circuit 24 is connected to p-channel transistor 21.This bias potential determined in the anchor leg 15 on draw intensity.With in addition minimum effective BW driver compare, each classification provides the less relatively variation of output intensity in the PBIAS signal.In like manner, the signal on the circuit 25, promptly the NBIAS signal has the bias voltage that " low " turn-on transistor 22 is also determined in 16 equal classifications.Compare with the BW pull-down driver of minimum, each classification provides less relatively change in signal strength at o pads (pad) 10 places.
When integrated circuit is worked, the output intensity of regularly indicating renewal from the SELN and the SELP signal of control circuit 30.The DAC of these signals by Fig. 2 regulates the bias voltage on transistor 22 and 21 respectively.Like this, when working, integrated circuit just the signal strength signal intensity on the pad 10 is finely tuned.
With reference to figure 3A, go between and linear weighted function (LW) relative intensity that offset signal provided by binary weighting (BW) driver shown in the figure.In the left side of Fig. 3 A, four kinds of intensity are shown, each is provided by a different BW lead-in wire.Fig. 3 A and 3B representative or on draw or pull-down strength.Should be pointed out that the various combination that to select " height " conducting and " low " turn-on transistor by PENB and NEN signal.In like manner, each SELN can select different classifications with the SELP signal.
In Fig. 3 A, the BW intensity that is provided by the effective BW lead-in wire of minimum is shown with intensity 70.As previously mentioned, this can be provided by transistor 36 or 38.The highest active strength of the next one is shown intensity 71, the 3rd active strength the highest is shown intensity 72.The highest active strength is represented with intensity 73 and can be provided by for example transistor 34 or 40.Fine setting has 16 classifications.Like this, for this embodiment, the BW strength range is (2
nK-1), n=4 in the formula, k is a constant, and the LW strength range is approximately 4k.In general, if the LW scope has the ρ position, and the least significant bit (LSB) of BW is n to the ratio of LW, and then the LW strength range is (2
PK/n-1).
When initialization or reset operation, select the combination of BW lead-in wire so that required intensity to be provided.Select to equal or be reduced to and approach most but less than the level of desirable strength.In Fig. 3 B, suppose that when initialization BW intensity 71 and 73 the most approachingly provides initial output intensity 75.Should be pointed out that the example for Fig. 3 B, if also selected intensity 70, then the BW lead-in wire will provide greater than required initial strength 75.This is undesirable, because there has not been the leeway of fine setting.During initialization, intensity and the difference between the actual needs that the BW lead-in wire provides are remedied by the LW bias voltage.
In one embodiment, the LW bias voltage is limited in the scope of classification 4 to 7 and selects during initialization.That is, initial control circuit 30 changes two least significant bit (LSB)s of SELN and SELP signal only.In Fig. 3 B, fine setting has selected four LW classifications to remedy poor between intensity 71 and 73, thereby has obtained required initial strength 75.
During work, control circuit 30 periodic adjustment SELN and SELP signal.When each periodic adjustment, control circuit allows SELN and SELP signal one or both of that the variation of a classification is arranged at most.This less relatively Strength Changes can be avoided the error detection of signal, and can allow to change at any time intensity.Even can make these little variations smoothly to avoid changed in stages.Electric capacity among Fig. 2 on the circuit 24 and 25 can provide this smoothing effect.Other filtering methods also can be used to make the changed in stages smoothing.
By Fig. 3 B as can be known, in one embodiment, initial strength can reduce by four LW classifications, and improves by reaching 12 LW classifications.Only use a least significant bit (LSB) in the time of also can being chosen in initialization, the LW grading range of broad just can be arranged when working like this.Usually temperature raises and the supply voltage reduction when work, so need additional strength, therefore provides more spaces to improve intensity rather than reduction intensity.And from Fig. 3 A as seen, 16 classifications provide roughly and two related scopes in the effective BW of minimum position.This just allows, and the LW signal has enough scopes when initialization and work.
Fig. 4 shows the step of controller buffer.When the initialization shown in the step 80, select the LW bias voltage of BW lead-in wire and use limited range (for example, 4 to 7).During work, have only the LW signal change, and each cycle of this change a classification only takes place, shown in step 81.
Buffer of the present invention is specially adapted to point-to-point transmission, the I/O device of image card, also can be used on such as in other circuit such as processor.Buffer of the present invention can be in buffer update buffer intensity during as driver or terminal organ.The LW classification is owing to the error detection that relatively can acute variation than the I proof strength cause signal.Provide fine setting to compare with using transistor, use the circuit of DAC comparatively simple.
Claims (18)
1. buffer that is used for integrated circuit, it comprises:
First group of optional device, in order to output signal to be provided, described output signal has by determined first strength range of the number of the optional device of choosing;
Drive circuit, it comprises the transistor that is connected to described first group of optional device, in order to the scalable intensity of output signal to be provided in second strength range, wherein, described second scope is setovered to described transistor by the signal with numerical value at least three numerical value less than described first scope; And
Be connected to the control circuit of described first group of optional device and described drive circuit, wherein, described control circuit comes the described optional device of described selection by the device of selecting first group of a certain number in the optional device when described integrated circuit initialization, and the described output signal strength of described control circuit regular monitoring, if described output signal needs compensation, then regulate described drive circuit by regulating described biasing.
2. buffer as claimed in claim 1, wherein, described optional device is a binary weighting.
3. buffer as claimed in claim 2, wherein, described optional device comprises transistor and resistance.
4. buffer as claimed in claim 3, wherein, described control circuit provides adjusting to described drive circuit by one or more offset signals are provided.
5. buffer as claimed in claim 4, wherein, described control circuit provides two kinds of offset signals, wherein a kind ofly is used for one or more p-channel transistors, and another kind is used for one or more n-channel transistors.
6. buffer as claimed in claim 1, wherein, described control circuit is provided for regulating the offset signal of described drive circuit, and the latter comprises first signal of the grid that is added to one or more n-channel transistors and is added to the secondary signal of the grid of one or more p-channel transistors.
7. buffer as claimed in claim 1, wherein, described control circuit comprises digital-to-analog converter, the latter's output is provided for regulating the offset signal of described drive circuit.
8. buffer as claimed in claim 7 wherein, carries out filtering with level and smooth described offset signal to described offset signal.
9. buffer as claimed in claim 8, wherein, described digital-to-analog converter receives binary signal, to change by described binary signal being transformed to the operation that is used for the analog signal that described drive circuit is setovered is compensated output signal.
10. buffer as claimed in claim 1, wherein, maximum first strength range equals (2
nK-1), and second scope equals about 4k or bigger, and wherein k is a constant, and n is the number of optional pull-down in first group of optional device.
11. buffer as claimed in claim 1, wherein, described second scope comprises a plurality of voltage classifications, and described control circuit is limited in when described integrated circuit work is former carves changeable voltage branch number of stages.
12. buffer as claimed in claim 11, wherein, described second scope comprises 16 classifications, and any one constantly can only change a classification when described integrated circuit is worked.
13. a buffer that is used for integrated circuit, it comprises:
A plurality of drive units are selected some drive units in described a plurality of drive unit when described integrated circuit initialization;
The drive circuit of drive signal is provided, and described drive signal is used for regularly finely tuning the output intensity of described buffer when work, and the increment of described fine setting is significantly less than the increment that is provided by described drive unit; And
Be connected with described drive unit selecting described drive unit and to be connected with described drive circuit controlling the control circuit of described drive circuit, described control circuit is monitored the output intensity of described buffer and is controlled described drive circuit the variation of described output intensity is responded.
14. a method that is used for the buffer of control integrated circuit, it comprises:
Select the output device of a certain number, so that when initialization, provide predetermined output intensity according to described buffer output; And
Utilize the analog signal that produces to finely tune described output intensity when described buffer is worked, simultaneously, compare with the intensity increment that described output device provides, the change of described output intensity is limited to less relatively change.
15. method as claimed in claim 14 wherein, comprises the described selection of described output device and to select the binary weighting output device.
16. method as claimed in claim 15, wherein, described fine setting comprises the selection to linear classification.
17. the method for the output intensity of a controller buffer, it may further comprise the steps:
By selecting when the initialization drive unit to provide the trend of output area is regulated;
Provide regular fine setting according to monitoring, wherein utilize an analog bias signals of adjusting the electric current in the transistor to control described fine setting described output area to described output intensity; And
Selectable described fine setting is restricted to the gamut less than described fine setting during with initialization.
18. method as claimed in claim 17, wherein, described analog signal is produced by digital-to-analog converter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/608,503 | 2000-06-30 | ||
| US09/608,503 US6624662B1 (en) | 2000-06-30 | 2000-06-30 | Buffer with compensating drive strength |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1449597A CN1449597A (en) | 2003-10-15 |
| CN1218484C true CN1218484C (en) | 2005-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN01814618XA Expired - Fee Related CN1218484C (en) | 2000-06-30 | 2001-06-14 | Buffer with compensating drive strength |
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| Country | Link |
|---|---|
| US (1) | US6624662B1 (en) |
| EP (1) | EP1297629B1 (en) |
| KR (1) | KR100511112B1 (en) |
| CN (1) | CN1218484C (en) |
| AT (1) | ATE310336T1 (en) |
| AU (1) | AU2001266969A1 (en) |
| DE (1) | DE60115041T2 (en) |
| HK (1) | HK1052090A1 (en) |
| TW (1) | TW506192B (en) |
| WO (1) | WO2002003553A1 (en) |
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| US6040845A (en) | 1997-12-22 | 2000-03-21 | Compaq Computer Corp. | Device and method for reducing power consumption within an accelerated graphics port target |
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| US6326821B1 (en) * | 1998-05-22 | 2001-12-04 | Agere Systems Guardian Corp. | Linearly-controlled resistive element apparatus |
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| JP3462104B2 (en) * | 1998-12-11 | 2003-11-05 | 株式会社東芝 | Programmable impedance circuit and semiconductor device |
| US6272644B1 (en) | 1999-01-06 | 2001-08-07 | Matsushita Electrical Industrial Co., Ltd. | Method for entering powersave mode of USB hub |
| US6166563A (en) | 1999-04-26 | 2000-12-26 | Intel Corporation | Method and apparatus for dual mode output buffer impedance compensation |
-
2000
- 2000-06-30 US US09/608,503 patent/US6624662B1/en not_active Expired - Lifetime
-
2001
- 2001-05-07 TW TW090110846A patent/TW506192B/en not_active IP Right Cessation
- 2001-06-14 AU AU2001266969A patent/AU2001266969A1/en not_active Abandoned
- 2001-06-14 CN CN01814618XA patent/CN1218484C/en not_active Expired - Fee Related
- 2001-06-14 WO PCT/US2001/019326 patent/WO2002003553A1/en active IP Right Grant
- 2001-06-14 AT AT01944573T patent/ATE310336T1/en not_active IP Right Cessation
- 2001-06-14 KR KR10-2002-7017971A patent/KR100511112B1/en active IP Right Grant
- 2001-06-14 EP EP01944573A patent/EP1297629B1/en not_active Expired - Lifetime
- 2001-06-14 DE DE60115041T patent/DE60115041T2/en not_active Expired - Lifetime
-
2003
- 2003-06-17 HK HK03104341A patent/HK1052090A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US6624662B1 (en) | 2003-09-23 |
| KR100511112B1 (en) | 2005-08-31 |
| TW506192B (en) | 2002-10-11 |
| HK1052090A1 (en) | 2003-08-29 |
| KR20030014289A (en) | 2003-02-15 |
| ATE310336T1 (en) | 2005-12-15 |
| WO2002003553A1 (en) | 2002-01-10 |
| EP1297629B1 (en) | 2005-11-16 |
| DE60115041D1 (en) | 2005-12-22 |
| DE60115041T2 (en) | 2006-07-13 |
| AU2001266969A1 (en) | 2002-01-14 |
| EP1297629A1 (en) | 2003-04-02 |
| CN1449597A (en) | 2003-10-15 |
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