CN1216456C - Method and circuit structure for temperature compensation and frequency calibration of oscillation frequency source - Google Patents
Method and circuit structure for temperature compensation and frequency calibration of oscillation frequency source Download PDFInfo
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- CN1216456C CN1216456C CN 03128198 CN03128198A CN1216456C CN 1216456 C CN1216456 C CN 1216456C CN 03128198 CN03128198 CN 03128198 CN 03128198 A CN03128198 A CN 03128198A CN 1216456 C CN1216456 C CN 1216456C
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Abstract
The present invention relates to a method and a circuit structure for temperature compensation and frequency calibration to an oscillation frequency source. The digital quantity used for expressing ambient temperature is used as a data reading reference value of a memorizer prestored with compensation data by a central processing unit to directly read or calculate in a middle interpolation way, the obtained compensation data is added with reference frequency, an obtained operation result is sent to a phase accumulator and the output of the phase accumulator to carry out add operation, and the operation result is used as an entry address of a sine waveform memorizer; corresponding phase sine wave sampling values are outputted to a D/A converter, the sampling values are converted into analog voltage signals by the D/A converter, and sine waveforms after temperature compensation and frequency calibration can be outputted and obtained by a band-pass filter. The present invention has the advantages of high compensation accuracy, high speed of frequency calibration, high product yield, etc.
Description
Technical field
The present invention relates to a kind of the method for temperature-compensating and frequency correction be carried out in the hunting of frequency source, also relate to a kind of circuit structure according to this method.
Background technology
Using microcontroller that temperature-compensating and frequency correction are carried out in the frequency of oscillation source generally all is variations in temperature according to the frequency of oscillation source, export a corresponding aanalogvoltage by microcontroller in various modes and control the output frequency of voltage controlled oscillator, thereby reach frequency compensated effect.But when using simulation control, the analog parameter of parts can exert an influence to the frequency characteristic of output frequency, thereby influences device quality, makes the decrease in yield of product.
Summary of the invention
Problem to be solved by this invention provides a kind ofly carries out the method for temperature-compensating and frequency correction and realizes the circuit structure of this method the frequency of oscillation source, this method and circuit structure thereof, the control of pure digi-tal has been taked in output to frequency, can avoid of the influence of the analog parameter of parts when using simulation control to the frequency characteristic of output frequency, reduce the factor that influences device quality, thereby improve the rate of finished products of product.
The technical scheme that the present invention also provides is: a kind of the method for temperature-compensating and frequency correction is carried out in the frequency of oscillation source, may further comprise the steps:
(1) outside provides a digital quantity of expressing ambient temperature;
(2) CPU (CPU) is carried out the reference value of reading of data with above-mentioned digital quantity as the memory to the offset data that prestored, and directly reads or carries out the intermediate interpolated computing, draws offset data;
(3) CPU (CPU) is carried out add operation with offset data as deviation frequency and reference frequency, and the operation result that draws is delivered in the frequency register by the frequency buffer, by frequency register output operation result;
(4) operation result of above-mentioned output carries out add operation as the output that the step-length of phase place is sent to phase accumulator and phase accumulator;
(5) operation result of above-mentioned phase accumulator output is as the entry address of the sinusoidal waveform memory of having stored the sinusoidal waveform sampled value, and the sinusoidal waveform sampled value of respective phase is outputed to digital to analog converter;
(6) digital to analog converter converts above-mentioned sampled value to analog voltage signal.
Perhaps, adopt following technical proposals: a kind of the method for temperature-compensating and frequency correction is carried out in the frequency of oscillation source, may further comprise the steps:
(1) outside provides a digital quantity of expressing ambient temperature;
(2) CPU is carried out the reference value of reading of data with above-mentioned digital quantity as the memory to the offset data that prestored, and directly reads or carries out the intermediate interpolated computing, draws offset data;
(3) CPU is delivered to offset data in the deviation frequency register by the deviation frequency buffer, use hardware adder that the value of the frequency register of the reference frequency that prestored and the value of deviation frequency register are carried out add operation, by adder output operation result;
(4) operation result of above-mentioned output carries out add operation as the output that the step-length of phase place is sent to phase accumulator and phase accumulator;
(5) operation result of above-mentioned phase accumulator output is as the entry address of the sinusoidal waveform memory of having stored the sinusoidal waveform sampled value, and the sinusoidal waveform sampled value of respective phase is outputed to digital to analog converter;
(6) digital to analog converter converts above-mentioned sampled value to analog voltage signal.
The present invention also provides a kind of the circuit structure of temperature-compensating and frequency correction is carried out in the frequency of oscillation source, comprising: clock generating circuit, CPU (CPU), program storage, data storage (RAM), offset data memory, multibyte frequency buffer, multibyte frequency register, phase accumulator, sinusoidal waveform memory and digital to analog converter.The frequency of oscillation source that is corrected links to each other with the input end of clock of clock generating circuit; The output of clock generating circuit links to each other with the input end of clock of CPU (CPU), program storage, data storage (RAM), offset data memory, multibyte frequency buffer and multibyte frequency register, provides operating clock to them; The frequency of oscillation source that is compensated directly links to each other with the input end of clock of phase accumulator with the sinusoidal waveform memory, provides operating clock to them; CPU (CPU) links to each other with clock generating circuit, program storage, data storage (RAM), offset data memory and multibyte frequency buffer by address, DCB, and CPU (CPU) can be carried out addressing and read-write operation to them directly or indirectly; Multibyte frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte frequency buffer; The data output end of multibyte frequency buffer is connected to the data input pin of multibyte frequency register; The flag bit of multibyte frequency buffer is connected to the control end that writes of multibyte frequency register; The data output end of multibyte frequency register is connected to a data input of phase accumulator; The data output end of phase accumulator is connected to another data input pin of phase accumulator; The high-end data wire of the data of phase accumulator output be connected to the sinusoidal waveform memory address wire; Stored sine-shaped sampled value in the sinusoidal waveform memory, the data output end of sinusoidal waveform memory is connected to the data input pin of digital to analog converter; Digital to analog converter is exported corresponding analog voltage amount; Address, DCB are connected to the circuit structure outside.
Perhaps, adopt following technical proposals: a kind of the circuit structure of temperature-compensating and frequency correction is carried out in the frequency of oscillation source, comprising: clock generating circuit, CPU, program storage, data storage, offset data memory, multibyte frequency buffer, multibyte frequency register, multibyte deviation frequency buffer, multibyte deviation frequency register, adder, phase accumulator, sinusoidal waveform memory and digital to analog converter; The frequency of oscillation source that is corrected links to each other with the input end of clock of clock generating circuit; The output of clock generating circuit links to each other with the input end of clock of CPU, program storage, data storage, offset data memory, multibyte frequency buffer, multibyte frequency register, multibyte deviation frequency buffer and multibyte deviation frequency register; The frequency of oscillation source that is compensated links to each other with the input end of clock of phase accumulator with the sinusoidal waveform memory; CPU links to each other with clock generating circuit, program storage, data storage, offset data memory, multibyte frequency buffer and multibyte deviation frequency buffer by address, DCB; Multibyte frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte frequency buffer; The data output end of multibyte frequency buffer is connected to the data input pin of multibyte frequency register; The flag bit output of multibyte frequency buffer is connected to the control end that writes of multibyte frequency register; Multibyte deviation frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte deviation frequency buffer; The data output end of multibyte deviation frequency buffer is connected to the data input pin of multibyte deviation frequency register; The flag bit output of multibyte deviation frequency buffer is connected to the control end that writes of multibyte deviation frequency register; The data output end of multibyte deviation frequency register is connected to a data input of adder; The data output end of multibyte frequency register is connected to another data input pin of adder; The data output end of adder is connected to a data input of phase accumulator; The data output end of phase accumulator is connected to another data input pin of phase accumulator; The high-end data wire of the data output of phase accumulator is connected to the address wire of sinusoidal waveform memory; The data output end of sinusoidal waveform memory is connected to the data input pin of digital to analog converter; Digital to analog converter is exported corresponding analog voltage amount; Address, DCB are connected to the circuit structure outside.
The present invention has the compensation precision height, the fireballing advantage of frequency correction, and also phase place is continuous during frequency shift, and frequency characteristic is only relevant with digital parameters.The method and structure that the present invention adopts, the control of pure digi-tal has been taked in output to frequency, has avoided that parameters of operating part has reduced the factor that influences device quality, thereby improved the rate of finished products of product the influence of output frequency when using simulation control.Simultaneously, can different output frequencies be set accurately by software under the situation that does not change internal hardware, this makes and must not change hardware when the product of production different model, has simplified production procedure widely, has increased the flexibility of product.And device involved in the present invention can be finished self-correction, is suitable for producing in enormous quantities.
Description of drawings
Fig. 1 is a circuit structure block diagram of the present invention;
Fig. 2 uses the circuit structure block diagram of hardware adder for the present invention;
The circuit structure block diagram that Fig. 3 uses discrete component to realize for the present invention.
Embodiment
Provided by the invention the method for temperature-compensating and frequency correction is carried out in the frequency of oscillation source, can realize as follows:
At first, gather offset data by one of following two kinds of methods.To place the environment temperature simulation chamber by the device that frequency of oscillation source that is carried out temperature-compensating and frequency correction and circuit structure provided by the invention are formed, the temperature of environment temperature simulation chamber changes in the temperature range of nominal with certain rate of change; The outside digital quantity that an expression variation of ambient temperature is provided of device; Outside test macro accurately reads the ambient temperature digital quantity of said apparatus and the output frequency of this device, and with storage in computer documents; After a temperature simulation cycle finishes, after handling data file, test macro obtains the question blank that a size and offset data memory are complementary; Test macro is written to above-mentioned lookup table data in the offset data memory of this device.
Or will place the environment temperature simulation chamber by the device that the circuit structure that frequency of oscillation source that is carried out temperature-compensating and frequency correction and invention provide is formed, the temperature of environment temperature simulation chamber changes in the temperature range of nominal with certain rate of change; The outside digital quantity that an expression variation of ambient temperature is provided of device; Outer testing system provides a high-precision reference frequency; With after the output frequency frequency multiplication of this device again with the reference frequency mixing, behind low pass filter, obtain a difference frequency; Outer testing system provides a digital quantity of expressing above-mentioned difference frequency to this device, and this device constantly changes the value of frequency register according to this digital quantity, thereby changes the output frequency of device, progressively to be reduced to this difference frequency in the accuracy rating; This device is write the digital quantity of corresponding deviant and expression variations in temperature in the offset data memory.Above three steps are carried out in circulation, finish until a temperature simulation cycle.
Then, when using this circuit structure that temperature-compensating and frequency correction are carried out in the frequency of oscillation source, the digital quantity that the outside expression temperature that provides is provided (for example: the digital quantity that the analog voltage amount of temperature sensor is converted to by analog to digital converter), CPU (CPU) is carried out this digital quantity the reference value of reading of data as the memory to the offset data that prestored, directly read or carry out the intermediate interpolated computing, draw offset data.CPU (CPU) is carried out add operation with this offset data as deviation frequency and reference frequency, draws operation result; Or the use hardware adder, the value of frequency register and the value of deviation frequency register are carried out add operation, draw operation result; This operation result carries out add operation as the output that the step-length of phase place is sent to phase accumulator and phase accumulator.The operation result of phase accumulator output is as the entry address of sinusoidal waveform memory, and the sinusoidal waveform sampled value of respective phase is outputed to digital to analog converter.Digital to analog converter converts above-mentioned sampled value to analog voltage signal again.This voltage signal is through the band pass filter of a respective bandwidth, can obtain the sinusoidal waveform after the frequency compensation.
Referring to Fig. 1, realize that circuit structure of the present invention comprises: clock generating circuit, CPU (CPU), program storage, data storage (RAM), offset data memory, multibyte frequency buffer, multibyte frequency register, phase accumulator, sinusoidal waveform memory and digital to analog converter.The frequency of oscillation source that is corrected links to each other with the input end of clock of clock generating circuit; The output of clock generating circuit and CPU (CPU), program storage, data storage (RAM),
The input end of clock of offset data memory, multibyte frequency buffer and multibyte frequency register links to each other, and provides operating clock to them; The frequency of oscillation source that is compensated directly links to each other with the input end of clock of phase accumulator with the sinusoidal waveform memory, provides operating clock to them; CPU (CPU) links to each other with clock generating circuit, program storage, data storage (RAM), offset data memory and multibyte frequency buffer by address, DCB, and CPU (CPU) can be carried out addressing and read-write operation to them directly or indirectly; Multibyte frequency buffer is exported multibyte data and a flag bit, and this flag bit indication CPU (CPU) is finished to the write operation of all bytes of multibyte frequency buffer; The data output end of multibyte frequency buffer is connected to the data input pin of multibyte frequency register; The flag bit of multibyte frequency buffer is connected to the control end that writes of multibyte frequency register; The data output end of multibyte frequency register is connected to a data input of phase accumulator; The data output end of phase accumulator is connected to another data input pin of phase accumulator; The high-end data wire of the data of phase accumulator output be connected to the sinusoidal waveform memory address wire; Stored sine-shaped sampled value in the sinusoidal waveform memory, the data output end of sinusoidal waveform memory is connected to the data input pin of digital to analog converter; Digital to analog converter is exported corresponding analog voltage amount; Address, DCB are connected to the circuit structure outside.
In preferred embodiments of the present invention, CPU (CPU) can read the digital quantity that the outside provides by address, the DCB that is connected to the circuit structure outside.
In preferred embodiments of the present invention, CPU (CPU) links to each other with multibyte frequency buffer by address, DCB, and CPU (CPU) can be carried out write operation to multibyte frequency buffer.
In preferred embodiments of the present invention, the frequency buffer is multibyte frequency buffer; This multibyte frequency buffer has a flag bit, with indication CPU (CPU) write operation of all bytes of frequency buffer is finished; This flag bit is connected to the control end that writes of multibyte frequency register.
In preferred embodiments of the present invention, also can use hardware adder (referring to Fig. 2), be provided with multibyte deviation frequency buffer, multibyte deviation frequency register and adder.The input end of clock of multibyte deviation frequency buffer, multibyte deviation frequency register links to each other with the output of clock generating circuit; CPU (CPU) links to each other with multibyte deviation frequency buffer by address, DCB; Multibyte deviation frequency buffer is exported multibyte data and a flag bit, and this flag bit indication CPU (CPU) is finished to the write operation of its all bytes; The data output end of multibyte deviation frequency buffer is connected to the data input pin of multibyte deviation frequency register; The flag bit of multibyte deviation frequency buffer is connected to the control end that writes of multibyte deviation frequency register; The data output end of multibyte deviation frequency register is connected to a data input of adder; The data output end of multibyte frequency register is connected to another data input pin of adder; The data output end of adder is connected to a data input of phase accumulator.
In preferred embodiments of the present invention, CPU (CPU) links to each other with multibyte deviation frequency buffer by address, DCB, and CPU (CPU) can be carried out write operation to multibyte deviation frequency buffer.
In preferred embodiments of the present invention, the deviation frequency buffer is multibyte deviation frequency buffer; This multibyte deviation frequency buffer has a flag bit, with indication the write operation of all bytes of deviation frequency buffer is finished; This flag bit is connected to the control end that writes of multibyte deviation frequency register.
For realizing and checking the present invention, ready-made discrete component is formed circuit structure of the present invention on the available markets, referring to Fig. 3, comprise: a temperature compensating crystal oscillator (TCXO), a resistance and the temperature sensor that thermistor is formed, one 8 single-chip microcomputer has analog to digital converter, timer, counter, serial line interface and program internal memory (FLASH) and variable internal memory (RAM), a digital direct frequency synthesizer (DDS) in it.Here the long-term stability of the temperature compensating crystal oscillator of Cai Yonging (TCXO) is 0.2PPM, 8 single-chip microcomputers are the 89C5115 of ATMEL, and it comprises 10 analog to digital converters, 16K byte program internal memory (FLASH), 256 byte variable internal memories (RAM), 2K byte EEPROM, UART serial line interface, a timer and a counter.The counter input of 89C5115 and UART serial line interface are drawn out to the outside of this circuit structure, and 89C5115 links to each other with a common quartz crystal to produce the dominant frequency clock of single-chip microcomputer.DDS adopts the AD9832 of ANALOG, and it comprises 32 phase frequency register and accumulator, 12 sinusoidal waveform memory and 10 digital to analog converter.
The device of above-mentioned composition is placed the environment temperature simulation chamber, and the temperature of environment temperature simulation chamber changes in the temperature range of nominal with certain rate of change; External test facility provides a high-precision reference frequency; 8 single-chip microcomputers are provided with the frequency register of digital direct frequency synthesizer (DDS) by data and clock line, export mutually deserved frequency (according to Lay Qwest theory by digital direct frequency synthesizer, this frequency can not surpass temperature compensating crystal oscillator (TCXO) frequency of oscillation 50%, had better not surpass 40% in actual applications); With after the output frequency frequency multiplication of the device of above-mentioned composition again with the reference frequency mixing, behind low pass filter, obtain a difference frequency; Above-mentioned difference frequency is delivered to the input of counter of 8 single-chip microcomputers of this device, 8 single-chip microcomputers obtain a digital quantity of expressing above-mentioned difference frequency by the timer sum counter, and the value of the frequency register of digital direct frequency synthesizer (DDS) is set according to this digital quantity, thereby change the output frequency of device, progressively to be reduced to this difference frequency in the accuracy rating; 8 single-chip microcomputers are write corresponding deviant and temperature analog-to-digital conversion value among FLASH or the EEPROM.
After finishing above-mentioned offset data collection, when using the variation of ambient temperature of this device, 8 single-chip microcomputers can be according to the temperature variant digital quantity that temperature sensor and analog to digital converter provided, in the offset data memory, find the correspondent frequency offset data, and this offset data done add operation as deviation frequency and reference frequency, this operation result is written in the frequency register of digital direct frequency synthesizer (DDS) by data and clock line then, corresponding sinusoidal waveform sampled analog voltage of digital to analog converter output of DDS can obtain a stabilized frequency with temperature-compensating and frequency correction through a band pass filter.The basic mechanical design feature index of this device is as follows:
The TCXO frequency that is compensated: 20MHz
The TCXO precision that is compensated: 0.2ppm
Compensation temperature range :-40C-+80C
Minimum frequency is adjusted step-length: 0.0047Hz
Offset data memory-size: 800 bytes
Compensation back output frequency: 0.0047Hz-8MHz
Compensation back output frequency precision: little what 2ppb @ 8MHz
Claims (4)
1. one kind to the temperature-compensating in frequency of oscillation source and the method for frequency correction, may further comprise the steps:
(1) outside provides a digital quantity of expressing ambient temperature;
(2) CPU is carried out the reference value of reading of data with above-mentioned digital quantity as the memory to the offset data that prestored, and directly reads or carries out the intermediate interpolated computing, draws offset data;
(3) CPU is carried out add operation with offset data as deviation frequency and reference frequency, and the operation result that draws is delivered in the frequency register by the frequency buffer, by frequency register output operation result;
(4) operation result of above-mentioned output carries out add operation as the output that the step-length of phase place is sent to phase accumulator and phase accumulator;
(5) operation result of above-mentioned phase accumulator output is as the entry address of the sinusoidal waveform memory of having stored the sinusoidal waveform sampled value, and the sinusoidal waveform sampled value of respective phase is outputed to digital to analog converter;
(6) digital to analog converter converts above-mentioned sampled value to analog voltage signal.
2. one kind to the temperature-compensating in frequency of oscillation source and the method for frequency correction, may further comprise the steps:
(1) outside provides a digital quantity of expressing ambient temperature;
(2) CPU is carried out the reference value of reading of data with above-mentioned digital quantity as the memory to the offset data that prestored, and directly reads or carries out the intermediate interpolated computing, draws offset data;
(3) CPU is delivered to offset data in the deviation frequency register by the deviation frequency buffer, use hardware adder that the value of the frequency register of the reference frequency that prestored and the value of deviation frequency register are carried out add operation, by adder output operation result;
(4) operation result of above-mentioned output carries out add operation as the output that the step-length of phase place is sent to phase accumulator and phase accumulator;
(5) operation result of above-mentioned phase accumulator output is as the entry address of the sinusoidal waveform memory of having stored the sinusoidal waveform sampled value, and the sinusoidal waveform sampled value of respective phase is outputed to digital to analog converter;
(6) digital to analog converter converts above-mentioned sampled value to analog voltage signal.
3. one kind is carried out the circuit structure of temperature-compensating and frequency correction to the frequency of oscillation source, comprising: clock generating circuit, CPU, program storage, data storage, offset data memory, multibyte frequency buffer, multibyte frequency register, phase accumulator, sinusoidal waveform memory and digital to analog converter; The frequency of oscillation source that is corrected links to each other with the input end of clock of clock generating circuit; The output of clock generating circuit links to each other with the input end of clock of CPU, program storage, data storage, offset data memory, multibyte frequency buffer and multibyte frequency register; The frequency of oscillation source that is compensated links to each other with the input end of clock of phase accumulator with the sinusoidal waveform memory; CPU links to each other with clock generating circuit, program storage, data storage, offset data memory and multibyte frequency buffer by address, DCB; Multibyte frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte frequency buffer; The data output end of multibyte frequency buffer is connected to the data input pin of multibyte frequency register; The flag bit output of multibyte frequency buffer is connected to the control end that writes of multibyte frequency register; The data output end of multibyte frequency register is connected to a data input of phase accumulator; The data output end of phase accumulator is connected to another data input pin of phase accumulator; The high-end data wire of the data output of phase accumulator is connected to the address wire of sinusoidal waveform memory; The data output end of sinusoidal waveform memory is connected to the data input pin of digital to analog converter; Digital to analog converter is exported corresponding analog voltage amount; Address, DCB are connected to the circuit structure outside.
4. one kind is carried out the circuit structure of temperature-compensating and frequency correction to the frequency of oscillation source, comprising: clock generating circuit, CPU, program storage, data storage, offset data memory, multibyte frequency buffer, multibyte frequency register, multibyte deviation frequency buffer, multibyte deviation frequency register, adder, phase accumulator, sinusoidal waveform memory and digital to analog converter; The frequency of oscillation source that is corrected links to each other with the input end of clock of clock generating circuit; The output of clock generating circuit links to each other with the input end of clock of CPU, program storage, data storage, offset data memory, multibyte frequency buffer, multibyte frequency register, multibyte deviation frequency buffer and multibyte deviation frequency register; The frequency of oscillation source that is compensated links to each other with the input end of clock of phase accumulator with the sinusoidal waveform memory; CPU links to each other with clock generating circuit, program storage, data storage, offset data memory, multibyte frequency buffer and multibyte deviation frequency buffer by address, DCB; Multibyte frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte frequency buffer; The data output end of multibyte frequency buffer is connected to the data input pin of multibyte frequency register; The flag bit output of multibyte frequency buffer is connected to the control end that writes of multibyte frequency register; Multibyte deviation frequency buffer has multibyte data output end and indicates CPU to the completed flag bit output of the write operation of all bytes of multibyte deviation frequency buffer; The data output end of multibyte deviation frequency buffer is connected to the data input pin of multibyte deviation frequency register; The flag bit output of multibyte deviation frequency buffer is connected to the control end that writes of multibyte deviation frequency register; The data output end of multibyte deviation frequency register is connected to a data input of adder; The data output end of multibyte frequency register is connected to another data input pin of adder; The data output end of adder is connected to a data input of phase accumulator; The data output end of phase accumulator is connected to another data input pin of phase accumulator; The high-end data wire of the data output of phase accumulator is connected to the address wire of sinusoidal waveform memory; The data output end of sinusoidal waveform memory is connected to the data input pin of digital to analog converter; Digital to analog converter is exported corresponding analog voltage amount; Address, DCB are connected to the circuit structure outside.
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| CN 03128198 CN1216456C (en) | 2003-06-24 | 2003-06-24 | Method and circuit structure for temperature compensation and frequency calibration of oscillation frequency source |
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| CN 03128198 CN1216456C (en) | 2003-06-24 | 2003-06-24 | Method and circuit structure for temperature compensation and frequency calibration of oscillation frequency source |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100353671C (en) * | 2004-05-26 | 2007-12-05 | 华为技术有限公司 | Clock synthesizing method and system |
| CN100525109C (en) * | 2005-11-01 | 2009-08-05 | 中国科学院半导体研究所 | Direct digital frequency synthesizer of shaped frequency noise |
| CN101315028B (en) * | 2007-05-29 | 2012-05-30 | 中国石油天然气集团公司 | Non-linear temperature compensation method for digital sound wave variable density sonic system |
| CN101076053B (en) * | 2007-06-21 | 2010-10-06 | 吴壬华 | Method and circuit for multi-channel photoelectric isolated voltage |
| CN101272142B (en) * | 2008-05-20 | 2011-05-18 | 曹秀娟 | Frequency synthesizer |
| CN101615051B (en) * | 2008-06-25 | 2011-06-29 | 中国科学院半导体研究所 | Compact direct digital frequency synthesizer used for system on chip |
| CN101488751B (en) * | 2009-01-23 | 2013-01-30 | 凯涛电子（上海）有限公司 | Measurement system and method for temperature frequency correcting apparatus |
| CN102866293B (en) * | 2011-07-05 | 2015-10-21 | 瑞昱半导体股份有限公司 | Oscillation frequency shifts detection method and oscillation frequency shifts testing circuit |
| CN102624331B (en) * | 2012-04-01 | 2015-09-23 | 钜泉光电科技(上海)股份有限公司 | The temperature-compensation circuit of real-time clock and method thereof |
| CN109490839B (en) * | 2018-10-29 | 2022-11-22 | 北京遥感设备研究所 | Temperature feedback phase correction circuit and method |
| CN111474522A (en) * | 2020-04-23 | 2020-07-31 | 西安电子工程研究所 | Compensation circuit with different clock phase synchronization |
| CN116611378A (en) * | 2022-02-08 | 2023-08-18 | 长鑫存储技术有限公司 | Simulation method and device for circuit model, computer equipment and storage medium |
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