CN1212659C - Method for lowering anomaly discharges happened on interconnected wires in plasma procedure - Google Patents
Method for lowering anomaly discharges happened on interconnected wires in plasma procedure Download PDFInfo
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- CN1212659C CN1212659C CN 02101552 CN02101552A CN1212659C CN 1212659 C CN1212659 C CN 1212659C CN 02101552 CN02101552 CN 02101552 CN 02101552 A CN02101552 A CN 02101552A CN 1212659 C CN1212659 C CN 1212659C
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- lead
- interlayer hole
- dielectric layer
- hole connector
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Abstract
The present invention relates to a method for abnormal discharge of plasma processes for lowering interconnected wires. A plurality of first virtual dielectric layer window plugs, a plurality of first dielectric layer window plugs and a plurality of second dielectric layer window plugs are formed in a dielectric layer, wherein the first virtual dielectric layer window plugs and the first dielectric layer window plugs are all connected to a first conducting wire; the second dielectric layer window plugs are all connected to a second conducting wire; the ratio of the sum of the first virtual dielectric layer window plugs and the first dielectric layer window plugs to the area of the first conducting wire is equal to the ratio of the quantity of the second dielectric layer window plugs to the area of the second conducting wire. Then, a plurality of third conducting wires are formed by carrying out the plasma processes on the dielectric layer, and are respectively connected with the first and the second dielectric layer window plugs.
Description
Technical field
The present invention is relevant for a kind of method that reduces the paradoxical discharge of plasma manufacture, particularly relevant for a kind of layout method of interlayer hole connector of paradoxical discharge of the plasma manufacture that reduces intraconnections.
Background technology
When processing procedure entered below 0.18 micron, regular meeting suffered from the situation of paradoxical discharge in the plasma manufacture of intraconnections, promptly so-called electricity slurry arc light (plasma arcing).According to research, the reason that causes arc light is because of the skewness of electric charge between different metal line A and B, thereby at the static charge buildup place arc light phenomenon takes place.As shown in Figure 1, metal wire A accumulates different charge density respectively with metal wire B, therefore, and the current potential V between metal wire A and the metal wire B
AAnd V
BDifference, the closest approach place between metal wire A and the metal wire B then is because of the current potential difference (V between two metal wire A and the B
A≠ V
B), make paradoxical discharge (as label C) takes place between metal wire A and the metal wire B.
The problem of above-mentioned electricity slurry arc light exists when the processing procedure more than 0.18 micron hardly.Yet along with the more and more little trend of element, the problem of electricity slurry arc light is a problem extremely to be solved.
Summary of the invention
In view of this, the invention provides a kind of method of paradoxical discharge of the plasma manufacture that reduces intraconnections, when making processing procedure enter below 0.18 micron, electricity slurry arc light can not take place.
The invention provides a kind of method of paradoxical discharge of the plasma manufacture that reduces intraconnections, its method is as described below.First lead and second lead are provided on wafer, and on first and second leads, form one dielectric layer.Then, in dielectric layer, form the first virtual interlayer hole connector, the first interlayer hole connector and the second interlayer hole connector, wherein the first virtual interlayer hole connector and the first interlayer hole connector all are connected to first lead, the second interlayer hole connector all is connected to second lead, and the first virtual interlayer hole connector and the first true interlayer hole connector are same as the surface density that second interlayer hole plugs in second lead in the surface density of first lead.Afterwards, carry out plasma manufacture and form plural privates on dielectric layer, and be connected with the first and second interlayer hole connectors respectively.
Wherein, the above-mentioned first virtual interlayer hole connector and the first true interlayer hole connector are same as the surface density that second interlayer hole plugs in second lead in the surface density of first lead, particularly, promptly the ratio of the area of the total number of the first virtual interlayer hole connector and the first interlayer hole connector and first lead is same as the ratio of the area of the total number of the second interlayer hole connector and second lead.
Wherein, the above-mentioned first virtual interlayer hole connector and the first true interlayer hole connector are same as the surface density that second interlayer hole plugs in second lead in the surface density of first lead, particularly, promptly the gross area that contacts with first lead of the first virtual interlayer hole connector and the first interlayer hole connector is same as the gross area that the second interlayer hole connector contacts with second lead ratio to the area of second lead to the ratio of the area of first lead.
Description of drawings
Fig. 1 represents the schematic diagram of traditional electricity slurry arc light problem.
Fig. 2 is a profile, and it is the schematic diagram of the method for the paradoxical discharge of the plasma manufacture that reduces intraconnections according to a preferred embodiment of the present invention a kind of.
Symbol description:
Metal wire～A, B; Paradoxical discharge～C;
Wafer～20; First lead～22
Second lead～24; Dielectric layer～26;
First virtual interlayer hole connector～32a; First interlayer hole connector～32b;
Second interlayer hole connector～34.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
In the plasma manufacture of intraconnections, the electric charge in the electricity slurry can flow to the bottom of interlayer hole connector via the interlayer hole connector, and is present in different metal wires.Because electric charge is evenly to distribute in electricity slurry environment, if the distribution total of interlayer hole connector between the different metal line is proportional to the area of lead, then the charge density between the different metal line can be consistent.Because charge density is directly proportional with current potential (electric potential), if the charge density between the different metal line is consistent, then the current potential between the different metal line can be identical, so can eliminate the arc light problem.
Yet, in the design of integrated circuit (IC), can't consider whether the distribution of interlayer hole connector is even usually.In the present invention, in order to make the electric charge that flows into the interlayer hole connector in the electricity slurry environment can be uniformly distributed to different metal wires, and make different metal wires have identical charge density, therefore when the position of configuration interlayer hole connector, need to consider whether the number of interlayer hole connector is proportional to the area of the metal wire that is connected, so, must set up virtual interlayer hole connector at the low metal wire of interlayer hole connector distribution density according to the size of different metal line.Make whereby and can make the electric charge that is accumulated in metal wire that current potential everywhere is all identical so that uniform mode is mobile, and be avoided the problem of electricity slurry arc light to take place.
Below especially exemplified by an embodiment explanation.The formation method of right interlayer hole connector and lead is not limited to the method for the following stated, also applicable to the processing procedure of dual damascene (dual damascene).
Embodiment
As shown in Figure 2, first lead 22 and second lead 24 are provided on wafer 20, first lead 22 and second lead 24 electrically do not communicate each other, and wherein the material of first lead 22 and second lead 24 can be the metal wire of aluminum metal or other metal materials that are fit to.Connect and below first lead 22 and second lead 24, have the interlayer hole connector that is formed in the dielectric layer 16 to be attached thereto.Wherein the material of dielectric layer 16 can be silicon dioxide, and it is other metal materials that are fit to that the material of interlayer hole connector 18 can be aluminum metal, tungsten metal or copper metal.
Then, form one dielectric layer 26 on first lead 22 and second lead 24, its material can be silicon dioxide.
Then, form the first virtual interlayer hole connector 32a, first true interlayer hole connector (hereinafter to be referred as the first interlayer hole connector) 32b and the second true interlayer hole connector (hereinafter to be referred as the second interlayer hole connector) 34 in dielectric layer 26, its material can be aluminum metal, tungsten metal or other metal materials that is fit to.
Wherein the first virtual interlayer hole connector 32a and the first interlayer hole connector 32b all are connected to line 22, the second interlayer hole connectors 34 such as first and all are connected to second lead 24.And the surface density that the first virtual interlayer hole connector 32a and the first interlayer hole connector 32b are distributed in first lead 22 is same as the surface density that the second interlayer hole connector 34 is distributed in second lead 24.
Wherein, the surface density that the above-mentioned first virtual interlayer hole connector 32a and the first interlayer hole connector 32b are distributed in first lead 22 is same as the surface density that the second interlayer hole connector 34 is distributed in second lead 24, particularly, i.e. number (the N of the first virtual interlayer hole connector 32a
A1) and the number (N of the first interlayer hole connector 32b
B1) both summation (N
A1+ N
B1) with the area (A of first lead 22
L1) ratio be same as the number (N of the second interlayer hole connector 34
2) with the area (A of second lead 24
L2) ratio, i.e. (N
A1+ N
B1)/A
L1=N
2/ A
L2
Wherein, the surface density that the above-mentioned first virtual interlayer hole connector 32a and the first interlayer hole connector 32b are distributed in first lead 22 is same as the surface density that the second interlayer hole connector 34 is distributed in second lead 24, particularly, i.e. the gross area (the A that contacts with first lead 22 of the first virtual interlayer hole connector 32a and the first interlayer hole connector 32b
V1) to the area (A of first lead 22
L1) ratio be same as the gross area (A that the second interlayer hole connector 34 contacts with second lead 24
V2) to the area (A of second lead 24
L2) ratio be A
V1/ A
L1=A
V2/ A
L2
Then, carrying out plasma manufacture forms plural privates 42 and is connected with the second interlayer hole connector 34 with the first interlayer hole connector 32b respectively on dielectric layer 26 with 44.Though be connected with first lead 22 as for the first virtual interlayer hole connector 32a one end, its other end then is not connected with other leads.
Electric charge in plasma manufacture can via the first virtual interlayer hole connector 32a, the first interlayer hole connector 32b and the second interlayer hole connector 34 flow to its bottom and be present in be not connected first lead the system 22 and second lead 24.Owing to be evenly distributed with the interlayer hole connector (32a, 32b and 34) that first lead 22 is connected with second lead 24, make the lead 22 of winning more consistent with the charge density of second lead 24, therefore first lead 22 is identical with VB with the current potential VA of second lead 24, so can avoid the closest approach place between first lead 22 and second lead 24 that paradoxical discharge (i.e. electricity slurry arc light) takes place in plasma manufacture.
Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; change and retouching when doing, thus protection scope of the present invention when with appended claim the person of being defined be as the criterion.
Claims (4)
1. the method for the paradoxical discharge of a plasma manufacture that reduces intraconnections is characterized in that, comprising:
One first lead and one second lead are provided on a wafer;
On this first and second lead, form a dielectric layer;
In this dielectric layer, form a plurality of first virtual interlayer hole connector, a plurality of first interlayer hole connector and a plurality of second interlayer hole connector, wherein those first virtual interlayer hole connectors and those first interlayer hole connectors all are connected to this first lead, those second interlayer hole connectors all are connected to this second lead, and the ratio of the area of total number of those first virtual interlayer hole connectors and those first interlayer hole connectors and this first lead is same as the ratio of the area of total number of those second interlayer hole connectors and this second lead; And
Carrying out plasma manufacture forms plural privates and is connected with those first and second interlayer holes connectors respectively on this dielectric layer.
2. the method for the paradoxical discharge of the plasma manufacture of reduction intraconnections according to claim 1 is characterized in that, wherein this first and second lead is a metal wire.
3. the method for the paradoxical discharge of a plasma manufacture that reduces intraconnections is characterized in that, comprising:
One first lead and one second lead are provided on a wafer;
On this first and second lead, form a dielectric layer;
In this dielectric layer, form a plurality of first virtual interlayer hole connector, a plurality of first interlayer hole connectors, with a plurality of second interlayer hole connectors, wherein those first virtual interlayer hole connectors and those first interlayer hole connectors all are connected to this first lead, those second interlayer hole connectors all are connected to this second lead, and the gross area that contacts with this first lead of those first virtual interlayer hole connectors and those first interlayer hole connectors is same as the gross area that those second interlayer hole connectors contact with second lead ratio to the area of this second lead to the ratio of the area of this first lead; And
Carrying out plasma manufacture forms a plurality of privates and is connected with those first and second interlayer holes connectors respectively on this dielectric layer.
4. the method for the paradoxical discharge of the plasma manufacture of reduction intraconnections according to claim 3 is characterized in that, wherein this first and second lead is a metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101552 CN1212659C (en) | 2002-01-09 | 2002-01-09 | Method for lowering anomaly discharges happened on interconnected wires in plasma procedure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101552 CN1212659C (en) | 2002-01-09 | 2002-01-09 | Method for lowering anomaly discharges happened on interconnected wires in plasma procedure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1431703A CN1431703A (en) | 2003-07-23 |
| CN1212659C true CN1212659C (en) | 2005-07-27 |
Family
ID=4739561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02101552 Expired - Fee Related CN1212659C (en) | 2002-01-09 | 2002-01-09 | Method for lowering anomaly discharges happened on interconnected wires in plasma procedure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1212659C (en) |
-
2002
- 2002-01-09 CN CN 02101552 patent/CN1212659C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1431703A (en) | 2003-07-23 |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111121 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050727 Termination date: 20190109 |
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| CF01 | Termination of patent right due to non-payment of annual fee |