CN1211853A

CN1211853A - Clock recovery circuit

Info

Publication number: CN1211853A
Application number: CN98120012A
Authority: CN
Inventors: 佐伯贵範
Original assignee: NEC Corp
Current assignee: Renesas Electronics Corp
Priority date: 1997-09-18
Filing date: 1998-09-18
Publication date: 1999-03-24
Anticipated expiration: 2018-09-18
Also published as: EP0903885A2; EP0903885A3; DE69833715D1; JPH1198132A; US6275547B1; EP0903885B1; TW437154B; KR100295121B1; DE69833715T2; CN1089504C; KR19990029900A; JP3019814B2

Abstract

A clock recovery circuit capable of shortening time needed to obtain a synchronized state includes a first synchronous delay circuit to which a reference clock and data are input and which outputs a first clock, and a second synchronous delay circuit to which the reference clock and a signal obtained by inverting the data by an inverter are input and which outputs a second clock. The first and second clocks are combined by a pulse combining circuit for producing an extracted clock. The extracted clock serves as the latch timing of a latch circuit.

Description

Clock recovery circuitry

The present invention relates to a kind of clock recovery circuitry, particularly a kind ofly be used to shorten data and the clock recovery circuitry of clock synchronization time.

In the prior art, in order to carry out burst mode (burst-mode) transition, adopted the clock recovery circuitry that is used to produce with the clock of data precise synchronization.Below with reference to Fig. 6 the clock recovery circuitry that is used for the transmission of this burst mode according to prior art is described, wherein Fig. 6 is the block diagram that shows conventional clock recovery circuitry.

At electronics mail (Electronics Letters), Nov.5th 1992, Vol.28, and No.23 discloses the clock recovery circuitry that shows in Fig. 6 among the pp.2127-2129.As shown in Figure 6, this clock recovery circuitry comprises that data 301 are input to the delay circuit (delay) 305 on it; Data 301 are input to the control gate input oscillator (GVCO) 307 on it; One is used for the data 301 that are input on it are carried out anti-phase inverter 315; A control gate input oscillator (GVCO) 309, the oppisite phase data of inverter 315 outputs is input on it; A mlultiplying circuit (MUX) 308 is used to merge the output of control gate input oscillator 307,309 and exports the gained result as extracting clock; A data-type flip-flop (hereinafter being called " D-F/F ") 306, have the data terminal of input by the extraction clock 303 of mlultiplying circuit 308 outputs, by the delayed data 301 of this trigger locking by delay circuit 305 outputs, and as playback of data 302 outputs; Reference clock 304 is input to the phase detecting circuit (PD) 311 on it; An and loop filter (LF)/charge pump (CP) 312, signal by phase detecting circuit 311 outputs is input on it, and output signal is from being sent to control gate input 307,309 and control gate input oscillators of oscillator (GVCO) 310 here, and the latter is sent to phase detecting circuit 311 based on the signal by loop filter (LF)/charge pump (CP) 312 outputs with its output signal.

Phase detecting circuit 311 in this clock recovery circuitry, loop filter (LF)/charge pump (CP) 312 and control gate input oscillator (GVCO) 310 have constituted a phase-locked loop (hereinafter being called " PLL ").

So, the clock recovery circuitry that shows in Fig. 6 is made up of the PLL fundametal component, comprises single loop filter (LF)/charge pump 312, single phase detecting circuit 311, mlultiplying circuit 308, single delay circuit 305, single D-F/F306 and three control gate input oscillators 307,309,310 as lock-in circuit.

Below with the operation of the clock recovery circuitry of the routine that shows in the key diagram 6.

According to connection, a common PLL is made of loop filter (LF)/charge pump 312, phase detecting circuit 311 and a control gate input oscillator 310.Reference clock 304 is input to phase detecting circuit 311, and this phase detecting circuit 311 becomes with reference clock 304 synchronous, and its output is sent to loop filter (LF)/charge pump 312.The output signal of loop filter (LF)/charge pump 312 is input to control gate input oscillator 307,309 and 310.Therefore, free in institute, control

gate input oscillator

307 and 309 output and reference clock 304 are synchronous.

The sequential of the various signals that interrelate below with reference to the conventional clock restore circuit that shows among Fig. 7 explanation and Fig. 6, Fig. 7 is the sequential chart that shows these signals.

As shown in Figure 7, control gate input oscillator 307 is according to clock A of rising edge output of data 301, and control gate input oscillator 309 is according to clock B of trailing edge output of data 301.Two clock A and B multiply each other by mlultiplying circuit 308, produce to extract clock 303.Further, owing to extract the data terminal that clock 303 is input to D-F/F306, the data 301 of delay circuit 305 have been passed through in the D-F/F306 locking, and produce playback of data 302.As a result, the prior art that shows according to Fig. 6 can acquisition and the synchronous extraction clock 303 of data and playback of data 302 by this clock recovery circuitry.

Further, disclose a kind of clock recovery circuitry that adopts similar technique about the VLSI circuit engineering paper 122-123 page or leaf that collects, replaced reference clock 304 with data 301 in 1996.

The problem that conventional clock recovery circuitry exists is to make single control gate input oscillator 307 and single control gate input oscillator 309 among the PLL remain on synchronous state.As a result, need this several of system wait even more clock pulse, up to reaching synchronous regime.This makes and is difficult to shorten lock in time.

Therefore, an object of the present invention is to provide and a kind ofly can shorten the clock recovery circuitry that reaches synchronous required time.

Other purposes of the present invention will become obvious in whole open text.

According to first aspect of the present invention, by providing following clock recovery circuitry to reach aforementioned purpose, this circuit comprises: reference clock and data are input to first synchronous delay circuit (so-called " multilevel delay circuit synchronously ") on it, are used to export first clock; An inverter that is used for and output oppisite phase data anti-phase to described data; One second synchronous delay circuit, reference clock and the oppisite phase data of being exported by inverter are input on it, and this circuit is used to export second clock; Data are input to the delay circuit on it, are used to postpone these input data and output; A pulse merges circuit, is input on it by first clock of first synchronous delay circuit output and the second clock of being exported by second synchronous delay circuit, and this circuit is used to merge these input clocks, and the output result, as extracting clock; And a data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data that postpone in the delay circuit, and exports this locking data, as playback of data.

First synchronous delay circuit has (1) first delay line, and reference clock is input on it, and this first delay line is made up of at least one first single delay circuit; Select gate array for (2) one first, form by at least one second single selection circuit, reference clock by each first single delay circuit output of forming first delay line is input on the second single selection circuit, and the second single selection circuit is based on the data conduction (so that the first generation reference clock to be provided) that becomes; And (3) one the one NAND doors, data and select (first produces) reference clock of data array output to be input on it by first, a NAND door is used to export first clock.

Second synchronous delay circuit has (1) second delay line, and reference clock is input on it, and this second delay line is made up of at least one the 3rd single delay circuit; Select gate array for (2) one second, form by at least one the 4th single selection circuit, reference clock by each the 3rd single delay circuit output of forming second delay line is input on the 4th single selection circuit, and the 4th single selection circuit is based on the oppisite phase data conduction (so that the second generation reference clock to be provided) that becomes; And (3) one the 2nd NAND doors, select (second produces) reference clock of gate array output to be input on it by the anti-phase data of inverter with by second, the 2nd NAND door is used to export second clock.

Therefore, according to first aspect of the present invention,, postpone reference clock by reference clock being input to first delay line of first synchronous delay circuit.If data are in high logic level, select gate array by entering data into first of first synchronous delay circuit, the reference clock of delay and the rising edge of data are synchronous, and export as first clock.By reference clock being input to second delay line of second synchronous delay circuit, postpone reference clock.If data are in low logic level, that is,, select gate array by being input to second of second synchronous delay circuit by the anti-phase oppisite phase data of inverter if oppisite phase data is in high logic level, the reference clock that postpones and the trailing edge of data are synchronous, and export as second clock.Merge circuit by apply pulse and merge first and second clocks acquisition extraction clock.On the basis of extracting clock, the locking of data type trigger is by the data of delay circuit delays, and the output locking data, as playback of data.This makes might shorten the required time of clock synchronization.

Below the operation of first aspect of the present invention will be described in further detail.

Because first and second synchronous delay circuits are provided, so two delay lines that are used for fixing with the delay time difference that equates to the time difference between two inputs of each synchronous delay circuit are arranged.An input in two inputs is a reference clock, and another input is data.The time difference between the rising edge of reference clock and data is fixing by an output in two the delay line output, and the time difference between the trailing edge of reference clock and data is fixing by another output in two the delay line output, and reasonable time is postponed to be applied on the reference clock.As a result, between each high level and low period of data, produced the clock pulse with the edge homophase of data, the pulse that produces has been merged obtaining extracting clock, and data are regenerated.

In a most preferred embodiment, pulse merges circuit and is made of the 3rd NAND door.

According to this embodiment, obtained the effect of first aspect of the present invention, in addition, pulse merges circuit and is made of the 3rd NAND door.As a result, can more accurate and more easily carry out the merging of first and second clock.

According to second aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises: reference clock and data are input to first synchronous delay circuit on it, are used to export first clock; An inverter that is used for and output oppisite phase data anti-phase to data; One second synchronous delay circuit, reference clock and the oppisite phase data of being exported by inverter are input on it, and this circuit is used to export second clock; Data are input to the delay circuit on it, are used to postpone these input data and output; A pulse merges circuit, is input on it by first clock of first synchronous delay circuit output and the second clock of being exported by second synchronous delay circuit, and this circuit is used to merge these input clocks, and the output result, as extracting clock; And a data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data that postpone in the delay circuit, and exports this locking data, as playback of data.

First synchronous delay circuit has one the 11st delay line, and reference clock is input on it, and the 11st delay line is made up of at least one the 5th single delay circuit; Select gate array for one first, form by at least one the 6th single selection circuit, reference clock and the reference clock of being exported by each the 5th single delay circuit of forming the 11st delay line are input on the 6th single selection circuit, and the 6th single selection circuit becomes conduction to provide first to produce reference clock based on data; One the 12nd delay line selects the clock of each the 6th single selection circuit output of gate array to be input on it by forming first, and the 12nd delay line is made up of at least one the 7th single delay circuit; And one the one NAND door, data and be input on it by (first produces) reference clock of the 12nd delay line output.

Second synchronous delay circuit has one the 21st delay line, and reference clock is input on it, and the 21st delay line is made up of at least one the 8th single delay circuit; Select gate array for one second, form by at least one the 9th single selection circuit, reference clock and the reference clock of being exported by each the 8th single delay circuit of forming the 12nd delay line are input on the 9th single selection circuit, and the 9th single selection circuit is based on the conduction that become by the anti-phase oppisite phase data of inverter (producing reference clock to provide second); One the 22nd delay line selects the reference clock of each the 9th single selection circuit output of gate array to be input on it by forming second, and the 22nd delay line is made up of at least one the tenth single delay circuit; And one the 2nd NAND door, be input on it by the anti-phase data of inverter with by the reference clock of the 22nd delay line output.

Therefore, according to second aspect of the present invention,, postpone reference clock by reference clock being input to the 11st delay line of first synchronous delay circuit.Select gate array by entering data into first, the reference clock of delay is by the first clock output of the 12nd delay line conduct corresponding to the clock of the rising edge of data.Further, by reference clock being input to the 21st delay line of second synchronous delay circuit, postpone reference clock.Select gate array by being input to second by the anti-phase data of inverter, with the trailing edge of data synchronously, just export as second clock by the 22nd delay line with the synchronous reference clock of the rising edge of oppisite phase data.Merge circuit in pulse first clock and second clock are merged, and the output combined signal is as extracting clock.By extracting the data terminal that clock outputs to the data type trigger, the locking of data type trigger is by the data of delay circuit delays, and the output locking data, as playback of data.This makes might shorten the required time of clock synchronization.

Below the operation of second aspect of the present invention will be described in further detail.

Because first and second synchronous delay circuits are provided, so two delay circuits that comprise relative delay line are respectively arranged, its function is the delay time difference that equates the time difference between two inputs that are used for fixing with each synchronous delay circuit.An input in two inputs is a reference clock, and another input is data.When data are high level, allow two outputs in the delay circuit output, and when data are low level, allow two another outputs in the delay circuit output.Be fixed at the rising edge of reference clock and data and the time difference between the trailing edge, and reasonable time is postponed to be applied on the reference clock.As a result, between each high level and low period of data, produced the clock pulse with the edge homophase of data, the pulse that produces has been merged obtaining extracting clock, and data are regenerated.In a most preferred embodiment, pulse merges circuit and is made of the 3rd NAND door.

According to this embodiment, obtained the effect of second aspect of the present invention, in addition, pulse merges circuit and is made of the 3rd NAND door.As a result, can more accurate and more easily carry out the merging of first and second clock.

According to the 3rd aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises: reference clock is input to the synchronous delay circuit on it; Data are input to first oscillator on it, are used to export first clock; An inverter that is used for and output oppisite phase data anti-phase to data; One second oscillator, the oppisite phase data of being exported by inverter is input on it, and this second oscillator is used to export second clock; A pulse merges circuit, is used to merge first clock of first oscillator output and the second clock of being exported by second oscillator, and the output result, as extracting clock; Data are input to the delay circuit on it, are used to postpone these input data and output; And a data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data that postpone in the delay circuit, and exports this locking data, as playback of data.

Synchronous delay circuit has one first delay line, and reference clock is input on it, and this first delay line is made up of at least one the 11st (the first) single delay circuit; And one first selection gate array, to form by at least one the 12nd (the first) single selection circuit, reference clock and the reference clock of being exported by each the 11st single delay circuit of forming first delay line are input on the 12nd (the first) the single selection circuit.

First oscillator has one the 11st (the first) and selects gate array, form first by each and select the reference clock of the 12nd (the first) single selection circuit output of gate array to be input on it, the 11st (the first) selects gate array to be made up of at least one the 13rd (the first) single selection circuit; One the 11st (the first) delay line, form the 11st (the first) by each and select the reference clock of the 13rd (the first) single selection circuit output of gate array to be input on it, the 11st (the first) delay line is made up of at least one the 14th (the first) single delay circuit; And one the one NAND door, data and the reference clock of being exported by the 11st (the first) delay line are input on it, are used for forming the 11st (the first) to each and select the 13rd (the first) single selection circuit of gate array and pulse merging circuit to export first clock.

Second oscillator has one the 12nd (the second) and selects gate array, form first by each and select the reference clock of the 12nd (the second) single selection circuit output of gate array to be input on it, the 12nd (the second) selects gate array to be made up of at least one the 15th (the second) single selection circuit; One the 12nd (the second) delay line, form the 12nd (the second) by each and select the reference clock of the 15th (the second) single selection circuit output of gate array to be input on it, the 12nd (the second) delay line is made up of at least one the 16th (the second) single delay circuit; And one the 2nd NAND door, be input on it by the anti-phase oppisite phase data of inverter with by the reference clock of the 12nd (the second) delay line output, be used for forming the 12nd (the second) and select the 15th (the second) single selection circuit of gate array and pulse to merge circuit output second clock to each.

Therefore, according to the 3rd aspect of the present invention,, postpone reference clock by reference clock being input to first delay line of synchronous delay circuit.Select gate array by reference clock being input to first of synchronous delay circuit, by the reference clock of the first delay line output delay.To select the delay reference clock of gate array output to output to the 11st of first oscillator by first of synchronous delay circuit and select gate array, and select the output signal of gate array to be input to the 11st delay line of first oscillator with the 11st, export first clock by first oscillator by the 11st delay line.Similarly, to output to the 12nd of second oscillator by the first delay reference clock of selecting gate array to export and select gate array, and select the output signal of gate array to be input to the 12nd delay line of second oscillator with the 12nd, by the 12nd delay line by second oscillator output second clock.Merge circuit in pulse first clock and second clock are merged, and the output combined signal is as extracting clock.By extracting the data terminal that clock is input to the data type trigger, the data type trigger is locked in the data that postpone in the delay circuit, and the output locking data, as playback of data.This makes might shorten the required time of clock synchronization.

The operation of the 3rd aspect of the present invention will be described below in further detail.

Because the synchronous delay circuit and first and second oscillators are provided, so have two be used for fixing with two inputs that comprise the continuous clock pulse between the delay line of the delay time difference that equates of the time difference, thereby and determined the number of the structural detail in two oscillators.When data are high logic level, allow an oscillator, and when data are low logic level, allow another oscillator, thus the synchronous clock pulse in edge of generation and data.

According to this embodiment, obtained the effect of the 3rd aspect of the present invention, in addition, pulse merges circuit and is made of the 3rd NAND door.As a result, can more accurate and more easily carry out the merging of first and second clock.

According to the 4th aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises: data are input to the synchronous delay circuit on it; Data are input to first oscillator on it, are used to export first clock; Data are input to the inverter on it, are used to export oppisite phase data; One second oscillator, the oppisite phase data of being exported by inverter is input on it, and this second oscillator is used to export second clock; A pulse merges circuit, is input on it by first clock of first oscillator output and the second clock of being exported by second oscillator, and this pulse merges circuit and is used to merge these two input clocks and exports the result, as extracting clock; Data are input to the delay circuit on it, are used to postpone these input data and output; And a data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data that postpone in the delay circuit, and exports this locking data, as playback of data.

Synchronous delay circuit has one first delay line, and data are input on it, and this first delay line is made up of at least one the 17th (the first) single delay circuit; And one first selection gate array, to form by at least one the 18th (the first) single selection circuit, data and the data of being exported by each the 17th (the first) single delay circuit of forming first delay line are input on the 18th (the first) the single selection circuit.

First oscillator has one the 11st (the first) and selects gate array, form first by each and select the data of the 18th (the first) single selection circuit output of gate array to be input on it, the 11st (the first) selects gate array to be made up of at least one the 19th (the first) single selection circuit; Two the 11st (the first) delay lines are formed the 11st (the first) by each and are selected the data of the 19th (the first) single selection circuit output of gate array to be input on it, and the 11st (the first) delay line is made up of at least one the 20th (the first) single delay circuit; And one the one NAND door, data and the data of being exported by two the 11st (the first) delay lines are input on it, are used for forming the 11st (the first) to each and select the 19th (the first) single selection circuit of gate array and pulse merging circuit to export first clock.

Second oscillator has one the 12nd (the second) and selects gate array, form first by each and select the data of the 18th (the second) single selection circuit output of gate array to be input on it, the 12nd (the second) selects gate array to be made up of at least one the 21st (the second) single selection circuit; Two the 12nd (the second) delay lines are formed the 12nd (the second) by each and are selected the data of the 21st (the second) single selection circuit output of gate array to be input on it, and the 12nd (the second) delay line is made up of at least one the 22nd (the second) single delay circuit; And one the 2nd NAND door, be input on it by the anti-phase oppisite phase data of inverter with by the data of two the 12nd (the second) delay lines outputs, be used for forming the 12nd (the second) and select the 21st (the second) single selection circuit of gate array and pulse to merge circuit output second clock to each.

Therefore, according to the 4th aspect of the present invention,, postpone this data by entering data into first delay line of synchronous delay circuit.Select gate array by entering data into first of synchronous delay circuit, by the data of the first delay line output delay.To select the delayed data of gate array output to be input to the 11st of first oscillator by first of synchronous delay circuit and select gate array, and the 11st delayed data of selecting gate array to export is input to the 11st delay line, exports first clock by first oscillator by the 11st delay line.Similarly, to select the delayed data of gate array output to be input to the 12nd of second oscillator by first of synchronous delay circuit and select gate array, and the 12nd delayed data of selecting gate array to export is input to the 12nd delay line, exports second clock by second oscillator by the 12nd delay line.Merge circuit in pulse first clock and second clock are merged, and the output combined signal is as extracting clock.And, on the basis of the extraction clock of the data terminal that is input to the data type trigger, be locked in the data and the output that postpone in the delay circuit, as playback of data.This makes might shorten the required time of clock synchronization.

The operation of the 4th aspect of the present invention will be described below in further detail.

According to this embodiment, obtained the effect of the 4th aspect of the present invention, in addition, pulse merges circuit and is made of the 3rd NAND door.As a result, can more accurate and more easily carry out the merging of first and second clock.

According to the 5th aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises:

(a) one first synchronous delay circuit, a data-signal is input on it, and this circuit is used to export first clock (A);

(b) inverter is used for the anti-phase and output anti-phase data signal to data-signal;

(c) one second synchronous delay circuit, anti-phase data signal is input on it, and this circuit is used to export second clock (B);

(d) delay circuit, data-signal is input on it, and this circuit is used to postpone this input data signal and output;

(e) pulse merges circuit, and first clock (A) and second clock (B) are input on it, and this circuit is used to merge these input clocks, and the output result, as extracting clock; And

(f) data type flip-flop, have the data terminal of input by the extraction clock of described pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data-signal that postpones in the delay circuit, and export this locking data signal, as regenerated data signal;

(g) wherein, first and second synchronous delay circuits are complementary synchronous multilevel delay circuit, be used for exporting and the first and second synchronous output signals of data-signal corresponding to first state of data-signal and a time cycle of second state respectively, as the pulse signal that has than the pulse period of the minimum period much shorter of the state of described data-signal, so that make the time cycle that reaches synchronously required the shortest.

In aspect this, synchronous delay circuit receives a reference clock that is used for the synchronous pulse period with pulse signal.The pulse period of pulse signal is preferably half of minimum period of the state of data-signal.

Each synchronous multilevel delay circuit preferably includes a single delay circuit array, and each grade of this single delay circuit array is connected to the corresponding stage of a single selection gate array.

Data-signal is provided to each level of single selection gate array, so that allow the reference clock of a generation of arbitrary grade of output, the reference clock that produces is provided to a NAND, NAND further receives data-signal, and export first and second clocks (A, B) in any respectively.

Single selection gate array can connect with the order identical with single delay circuit array.Perhaps, single selection gate array also can connect with the order opposite with single delay circuit array.

According to the 6th aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises:

(a) synchronous multilevel delay circuit, a reference clock is input on it;

(b) one first oscillator, a data-signal is input on it, and this first oscillator is used to export first clock (A);

(c) inverter is used for the anti-phase anti-phase data signal of exporting then of data-signal;

(d) one second oscillator, the anti-phase data signal of being exported by inverter is input on it, and this second oscillator is used to export second clock (B);

(e) pulse merges circuit, be used to merge by first clock (A) of described first oscillator output and the second clock of exporting by second oscillator (B), and the output result, as extracting clock;

(f) delay circuit, data-signal is input on it, is used to postpone this input data signal and output; And

(g) data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data-signal that postpones in the delay circuit, and export this locking data signal, as regenerated data signal.

In aspect this, the multilevel delay circuit comprises a single delay circuit array synchronously, and each grade of this single delay circuit array provides the reference clock of a generation, and the reference clock of generation is provided to each level of first and second oscillators.

First and second oscillators are complementary synclators, be used for exporting and the first and second synchronous output signals of data-signal corresponding to first state of data-signal and a time cycle of second state respectively, as the pulse signal that has than the pulse period of the minimum period much shorter of the state of described data-signal, so that make the time cycle that reaches synchronously required the shortest.

According to the 7th aspect of the present invention, a kind of clock recovery circuitry is provided, this circuit comprises:

(a) synchronous multilevel delay circuit, a data-signal is input on it;

(b) one first oscillator, data-signal is input on it, and this first oscillator is used to export first clock (A);

(c) inverter, data-signal is input on it, is used to export an anti-phase data signal;

(e) pulse merges circuit, and first clock (A) and second clock (B) are input on it, and this circuit is used to merge this two input clocks, and the output result, as extracting clock;

(g) data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the locking of data type trigger is by the delayed data signal of delay circuit output, and export this locking data, as regenerated data signal.

By below in conjunction with the description of the drawings, other features and advantages of the present invention will become obviously, and in the accompanying drawings, similar label is represented same or analogous part.

Fig. 1 shows a kind of block diagram of realizing according to the pattern of clock recovery circuitry of the present invention;

Fig. 2 A is the circuit diagram that shows according to first embodiment of clock recovery circuitry of the present invention;

Fig. 2 B is the sequential chart of various signals relevant with the clock recovery circuitry shown in Fig. 2 A;

Fig. 3 A is the circuit diagram that shows according to second embodiment of clock recovery circuitry of the present invention;

Fig. 3 B is the sequential chart of various signals relevant with the clock recovery circuitry shown in Fig. 3 A;

Fig. 4 A is the circuit diagram that shows according to the 3rd embodiment of clock recovery circuitry of the present invention;

Fig. 4 B is the sequential chart of various signals relevant with the clock recovery circuitry shown in Fig. 4 A;

Fig. 5 A is the circuit diagram that shows according to the 4th embodiment of clock recovery circuitry of the present invention;

Fig. 5 B is the sequential chart of various signals relevant with the clock recovery circuitry shown in Fig. 5 A;

Fig. 6 is the block diagram that shows according to the clock recovery circuitry of prior art; And

Fig. 7 is the sequential chart of various signals relevant with the clock recovery circuitry according to prior art shown in Fig. 6.

Explanation realizes the pattern according to a kind of clock recovery circuitry of the present invention below with reference to the accompanying drawings.

Fig. 1 is the block diagram of demonstration according to the structure of first and second embodiment (hereinafter will describe) of clock recovery circuitry of the present invention.

As shown in Figure 1, clock recovery circuitry comprises one first synchronous delay circuit 101, and reference clock 108 and data 107 are input on it, is used for merging circuit 5 outputs one first clock A to a pulse; An inverter 15, data 107 are input on it, are used for data 107 anti-phase and output oppisite phase datas; One second synchronous delay circuit 102, reference clock 108 and the oppisite phase data of being exported by inverter are input on it, are used for merging circuit 5 outputs one second clock B to pulse; A delay circuit 105, data 107 are input on it, are used for postponing input data 107 and export these data to a lock-in circuit 106; Pulse merges circuit 5, is input on it by first clock A of first synchronous delay circuit, 101 outputs and the first clock B that is exported by second synchronous delay circuit 102, is used to merge these input clocks, and the output result, as extracting clock 110; And lock-in circuit 106, on the basis of the signal that pulse merging circuit 5 is exported, these lock-in circuit 106 lockings are by the inhibit signal of delay circuit 105 outputs, and output playback of data 109.

So in this clock recovery circuitry, data 107 enter first synchronous delay circuit 101, and are undertaken anti-phase by inverter 15 before entering second synchronous delay circuit 102.In addition, reference clock 108 enters first and second synchronous delay circuits 101,102.When data 107 are high level pulse, first synchronous delay circuit, 101 outputs, the first clock A, it is regularly synchronous with the rising edge of data 107.When data 107 are low level pulse, second synchronous delay circuit, 101 output second clock B, it is regularly synchronous with the trailing edge of data 107.Pulse merges circuit 5 and merges the first and second clock A, B, and the output combined signal, as extracting clock 110.

Extract clock 110 and output to lock-in circuit 106, the data 107 that postpone by delay circuit 105 also are input on the lock-in circuit 106.The data of input are locked by lock-in circuit 106 based on the timing of extracting clock 110, and output to next stage as playback of data 109 with extracting clock 110.

It should be noted that the clock recovery circuitry that shows among Fig. 1 can be realized by the combination of a synchronous delay circuit and ring oscillator.

First embodiment of foundation clock recovery circuitry of the present invention is described below with reference to Fig. 2.[first embodiment]

Fig. 2 A is the circuit diagram that shows according to first embodiment of clock recovery circuitry of the present invention, and Fig. 2 B is the sequential chart of various signals relevant with the clock recovery circuitry that shows among Fig. 2 A.Element identical to those shown in Fig. 1 among Fig. 2 A is represented by similar label with signal.

Shown in Fig. 2 A, the clock recovery circuitry of foundation first embodiment of the present invention comprises first synchronous delay circuit 101, and reference clock 108 and data 107 are input on it, is used for merging the circuit 5 outputs first clock A to pulse; Inverter 15, data 107 are input on it, are used for data 107 anti-phase and output oppisite phase datas; Second synchronous delay circuit 102, reference clock 108 and the signal of being exported by inverter 15 are input on it, are used for merging circuit 5 outputs one second clock B to pulse; Delay circuit 105, data 107 are input on it, are used for the input data are outputed to lock-in circuit 106; Pulse merges circuit 5, is input on it by first clock A of first synchronous delay circuit, 101 outputs and the first clock B that is exported by second synchronous delay circuit 102, is used to merge these input clocks, and the output result, as extracting clock 110; And the lock-in circuit 106 that comprises D-F/F, D-F/F locks by the inhibit signal of delay circuit 105 outputs on the basis of the signal of pulse merging circuit 5 outputs and exports playback of data 109.

First synchronous delay circuit 101 comprises one first delay line 101A, is made up of at least one first single delay circuit 101AT; Select gate array 103, form for one first by at least one first single selection circuit 103T; And one the one NAND door 51, be used to carry out the NAND computing.Pulse merges circuit 5 preferably to be implemented by a NAND door that is used to carry out the NAND computing, so that accurately and easily carry out the pulse union operation.

Reference clock 108 is input to the first delay line 101A, and postpones back output by this delay line.

Data 107 are input to first and select gate array 103.If data 107 are in high logic level, each is formed first and selects the first single selection circuit 103T of gate array 103 conduction that becomes, permission is passed through this gate array 103 by each reference clock 108 of forming the first single delay circuit 101AT output of the first delay line 101A, and outputs to NAND door 51.

NAND door 51 in data 107 and by first reference clock of selecting gate array 103 outputs (promptly, the first generation reference clock that comes from reference clock 108 by first delay line) carries out NAND between, and the result of NAND computing is outputed to pulse merging circuit 5 as the first clock A.

Second synchronous delay circuit 102 comprises one second delay line 102A, is made up of at least one second single delay circuit 102AT; Select gate array 104, form for one second by at least one second single selection circuit 104T; And one the 2nd NAND door 52, be used to carry out the NAND computing.

Reference clock 108 is input to the second delay line 102A, and postpones back output by this delay line.

The signal (oppisite phase data) that is carried out anti-phase acquisition by 15 pairs of data of inverter 107 is input to the second selection gate array 104.If input signal is high, promptly, if data 107 are in low logic level, each is formed second and selects the second single selection circuit 104T of gate array 104 conduction that becomes, permission is passed through this gate array 104 by each reference clock 108 of forming the second single delay circuit 102AT output of the second delay line 102A, and outputs to NAND door 52.

NAND door 52 carries out NAND between by the reference clock 108 that data 107 is carried out the anti-phase signal that obtains (oppisite phase data) and exported by the second selection gate array 104, and the result of NAND computing is outputed to pulse merging circuit 5 as second clock B.

So among first embodiment that shows in Fig. 2 A, clock recovery circuitry comprises first synchronous delay circuit 101, second synchronous delay circuit 102, delay circuit 105 and the lock-in circuit of being made up of a D-F/F 106.Data 107 are input to first synchronous delay circuit 101, are undertaken anti-phasely by inverter 15, are input to second synchronous delay circuit 102 then.

Reference clock 108 is input to first synchronous delay circuit 101 and second synchronous delay circuit 102.When data are high level pulse, first synchronous delay circuit, 101 outputs, the first clock A, it is regularly synchronous with the rising edge of data 107.When data 107 are low level pulse, second synchronous delay circuit, 102 output second clock B, it is regularly synchronous with the trailing edge of data 107.Pulse merges circuit 5 the first and second clock A, B is merged, and the output combined signal, as extracting clock 110.

As mentioned above, first synchronous delay circuit 101 selects gate array 103 to form by the first delay line 101A and first, and second synchronous delay circuit 102 selects gate array 104 to form by the second delay line 102A and second.Therefore, because first synchronous delay circuit 101 is quite similar with operation upper part in structure with second synchronous delay circuit 102, so following operation that describes first synchronous delay circuit 101 in detail.

As previously mentioned, reference clock 108 and data 107 are input to first synchronous delay circuit 101.Reference clock 108 is input to the first delay line 101A, and by the first delay line 101A.During this period, when data 107 through the low level of associating during to the transition of high level, be arranged in the conduction that becomes of (first select gate array 103) first single selection circuit 103T of the current location of reference clock 108.As a result, reference clock 108 outputs to NAND door 51 from this position of selecting gate array.Be between high period in data 107, the NAND door 51 that is used to carry out the NAND computing allow reference clocks 108 (more properly, be first produce reference clock) by and output to pulse and merge circuit 5.

The extraction clock 110 that is merged circuit 5 outputs by pulse is sent to lock-in circuit 106, and data 107 also are input on this lock-in circuit 106 by delay circuit 105.Based on extracting clock 110, lock-in circuit 106 is consistent with extraction clock 110, locking data 107, and data are sent to next stage as playback of data 109.

Below with reference to the sequential of each signal among first embodiment of the foundation clock recovery circuitry of the present invention that shows among Fig. 2 B key diagram 2A, wherein Fig. 2 B is the sequential chart of relevant signal.

Fig. 2 B has shown reference clock 108, data 107, the first clock A, second clock B, has extracted the sequential of clock 110 and playback of data 109.

Shown in Fig. 2 B, when data 107 are in high logic level, export the first clock A synchronously with the rising edge of reference clock 108, and when data 107 are in low logic level, export second clock B synchronously with the trailing edge of reference clock 108.It is synchronous with data 107 to extract clock 110, and playback of data 109 is also synchronous with data 107.

Therefore, according to first embodiment, the extraction clock 110 in clock recovery circuitry is realized by logical circuit synchronously with data 107.As a result, be difficult for the timing error of generation, and can shorten lock in time owing to appearance such as voltage fluctuations.[second embodiment]

Second embodiment below with reference to Fig. 3 A and 3B explanation foundation clock recovery circuitry of the present invention.Fig. 3 A is the circuit diagram that shows according to second embodiment of clock recovery circuitry of the present invention, and Fig. 3 B is the sequential chart of various signals relevant with clock recovery circuitry shown in Fig. 3 A.In Fig. 3 A and 3B, represent with similar label with signal with part identical among first embodiment that shows among Fig. 2 A and the 2B.

As shown in Figure 3A, the clock recovery circuitry according to second embodiment of the present invention comprises; First synchronous delay circuit 101, reference clock 108 and data 107 are input on it; Second synchronous delay circuit 102, reference clock 108 and anti-phase by 15 pairs of data of inverter 107 and signal that obtain is input on it; Inverter 15 is used for input data 107 anti-phase and output oppisite phase datas; Pulse merges circuit 5, is used to merge by first clock A of first synchronous delay circuit, 101 outputs and the first clock B that exports by second synchronous delay circuit 102, and the output result, as extracting clock 110; Delay circuit 105, input data 107 are input on it, are used for input data delay and output; And the lock-in circuit 106 that comprises D-F/F, according to the timing of extracting clock 110, lock the inhibit signal of exporting by delay circuit 105 and export playback of data 109.

First synchronous delay circuit 101 comprises the first delay line 101A (being connected in series with normal sequence), is made up of at least one first single delay circuit 101AT; First selects gate array 103, is made up of at least one first single selection circuit 103T; One first delay line 101B (being connected in series with reverse order) is made up of at least one first single delay circuit 101BT; And a NAND door 51, be used to carry out the NAND computing.Pulse merges circuit 5 preferably to be implemented by a NAND door that is used to carry out the NAND computing, so that accurately and easily carry out the pulse union operation.

Reference clock 108 is input to the first delay line 101A of first synchronous delay circuit 101, and postpones back output by this delay line.

Data 107 and reference clock 108 are input to first and select gate array 103.If data 107 are in high logic level, each is formed first and selects the first single selection circuit 103T of gate array 103 conduction that becomes, pass through this gate array 103 by each reference clock 108 of forming the first single delay circuit 101AT output of the first delay line 101A (normal sequence is connected in series), output to the first delay line 101B (reverse order is connected in series).

Output to the reference clock 108 delayed back outputs of the first delay line 101B, the output signal of the first single delay line 101B is sent to NAND door 51.The first single delay circuit that connects (Far Left among Fig. 3 A) by the afterbody that connects corresponding to the first order of the first single delay circuit passes the signal to NAND door 51.

NAND door 51 carries out NAND between the output signal that is input to the data 107 on it and the first delay line 101B, and the result of NAND computing is outputed to pulse as the first clock A merges circuit 5.

Second synchronous delay circuit 102 comprises the second delay line 102A, is made up of at least one second single delay circuit 102AT; Second selects gate array 104, is made up of at least one second single selection circuit 104T; One second delay line 102B is made up of at least one second single delay circuit 102BT; And NAND door 52, be used to carry out the NAND computing.

Reference clock 108 is input to the second single delay line 102A of second synchronous delay circuit 102, and postpones back output by this delay line.

The signal that carries out anti-phase acquisition by 15 pairs of data of inverter 107 is input to the second selection gate array 104.If input signal is high, that is, if data 107 are in low logic level, each is formed second and selects the second single selection circuit 104T of gate array 104 conduction that becomes,

Pass through this gate array 104 by each reference clock 108 of forming the second single delay circuit 102AT output of the second delay line 102A, and output to the second delay line 102B.

The reference clock 108 that outputs to the second delay line 102B is exported through the second delay line 102B, and the output of the second delay line 102B is sent to NAND door 52.

NAND door 52 carries out NAND between the output signal of data 107 being carried out anti-phase and the signal that obtains and the second single delay line 102B by inverter that is input on it, and the result of NAND computing is outputed to pulse as second clock B merges circuit 5.

So similar with first embodiment among second embodiment that shows in Fig. 3 A, clock recovery circuitry comprises first synchronous delay circuit 101, second synchronous delay circuit 102, delay circuit 105 and lock-in circuit 106.As for the H/L relation of data, second synchronous delay circuit 102 and first synchronous delay circuit 101 are complimentary fashion.

Data 107 are input to first synchronous delay circuit 101, are undertaken anti-phasely by inverter 15, are input to second synchronous delay circuit 102 then.Reference clock 108 is input to first and second synchronous delay circuits 101,102.When data 107 are high level pulse, first synchronous delay circuit, 101 outputs, the first clock A, it is regularly synchronous with the rising edge of data 107.When data 107 are low level pulse, second synchronous delay circuit, 102 output second clock B, it is regularly synchronous with the trailing edge of data 107.Pulse merges circuit 5 the first and second clock A, B is merged, and the output combined signal, as extracting clock 110.

According to second embodiment, first synchronous delay circuit 101 selects the gate array 103 and the first delay line 101B to form by the first delay line 101A, first, and second synchronous delay circuit 102 selects the gate array 104 and the second delay line 102B to form by the second delay line 102A, second.Therefore, because first synchronous delay circuit 101 and second synchronous delay circuit 102 are in structure and operation all quite similar (order of connection of supposing single delay circuit is opposite), so the operation of following detailed description first synchronous delay circuit 101.

As previously mentioned, reference clock 108 and data 107 are input to first synchronous delay circuit 101.Reference clock 108 is input to the first delay line 101A, and by the first delay line 101A.During this period, when data 107 through the low level of associating during to the transition of high level, be positioned at reference clock 108 current location first select one first single selection circuit 103T of gate array 103 conduction that becomes.

The reference clock 108 by the first delay line 101A does not output to NAND door 51 by the first delay line 101B from the above-mentioned position of selecting gate array 103.Be between high period in data 107, NAND door 51 allow reference clocks 108 by and the first clock A outputed to pulse merge circuit 5.

Pulse merges circuit 5 outputs and extracts clock 110, is sent to the lock-in circuit of being made up of D-F/F 106 with extracting clock 110.

Data 107 also are input to this lock-in circuit 106 by delay circuit 105, and locked based on extracting clock 110.Locking data is sent to next stage as playback of data 109 with extracting clock 110.

Below with reference to the sequential of each signal among second embodiment of the foundation clock recovery circuitry of the present invention that shows among Fig. 3 B key diagram 3A, wherein Fig. 3 B is the sequential chart of relevant signal.

Fig. 3 B has shown reference clock 108, data 107, the first clock A, second clock B, has extracted the sequential of clock 110 and playback of data 109.

Shown in Fig. 3 B, when data 107 are in high logic level, export the first clock A synchronously with the rising edge of reference clock 108, and when data 107 are in low logic level, export second clock B synchronously with the trailing edge of reference clock 108.Therefore, it is synchronous with data 107 to extract clock 110, and playback of data 109 is also synchronous with data 107.

Therefore, according to second embodiment, the extraction clock 110 in clock recovery circuitry is realized by logical circuit synchronously with data 107.As a result, be difficult for the timing error of generation, and can shorten lock in time owing to appearance such as voltage fluctuations.[the 3rd embodiment]

The 3rd embodiment below with reference to Fig. 4 A and 4B explanation foundation clock recovery circuitry of the present invention.Fig. 4 A is the circuit diagram that shows according to the 3rd embodiment of clock recovery circuitry of the present invention, and Fig. 4 B is the sequential chart of various signals relevant with clock recovery circuitry shown in Fig. 4 A.In Fig. 4 A and 4B, represent with similar label with signal with part identical among first embodiment that shows among Fig. 2 A and the 2B.

Shown in Fig. 4 A, the clock recovery circuitry of foundation the 3rd embodiment of the present invention comprises: synchronous delay circuit 100, and reference clock 108 is input on it; One first oscillator 101H, data 107 are input on it, are used to export the first clock A; One second oscillator 102H, the signal (oppisite phase data) that is carried out anti-phase acquisition by 15 pairs of data of inverter 107 is input on it, is used to export second clock B; Inverter 15, data 107 are input on it, are used for the anti-phase and output oppisite phase data to data; Pulse merges circuit 5, is used to merge the first clock A and second clock B, and the output result, as extracting clock 110; Delay circuit 105, data 107 are input on it, are used to postpone these input data and output; And the lock-in circuit 106 that comprises a data type flip-flop, have the data terminal of input by the extraction clock 110 of pulse merging circuit 5 outputs, extract clock 110 in response to this, the locking of data type trigger is by the data of delay circuit 105 outputs, and export this locking data, as playback of data.

Synchronous delay circuit 100 comprises one first delay line 100A, is made up of at least one first single delay circuit 100T; And one first selection gate array 100S, form by at least one first single selection circuit 100ST.Pulse merges circuit 5 preferably to be implemented by a NAND door that is used to carry out the NAND computing, so that accurately and easily carry out the pulse union operation.

The first oscillator 101H comprises that first selects gate array 103, forms (normal sequence is connected in series) by at least one first single selection circuit 103T; The first delay line 101A is made up of at least one first single delay circuit 101AT; And a NAND door 53, be used to carry out the NAND computing.

The second oscillator 102H comprises that second selects gate array 104, forms (reverse order is connected in series) by at least one second single selection circuit 104T; The second delay line 102A is made up of at least one second single delay circuit 102AT; And NAND door 54, be used to carry out the NAND computing.

Reference clock 108 is input to the first delay line 100A of synchronous delay circuit 100, and postpones back output by this first delay line 100A.And, reference clock 108 also is input to first of synchronous delay circuit 100 and selects gate array 100S, and forms first by each and select the signal of the first single selection circuit 100ST output of gate array 100S to be input to the first and second oscillator 101H, 102H.

Data 107 are input to the NAND door 53 of the first oscillator 101H.And, form first of synchronous delay circuit 100 by each and select the signal of the first single selection circuit 100ST output of gate array 100S to be input to the first single selection circuit 103T that each forms the first selection gate array 103 of the first oscillator 101H.The output signal of NAND door 53 also is input to each and forms the first single selection circuit 103T that first of the first oscillator 101H selects gate array 103.Forming first of the first oscillator 101H by each selects the signal of the first single selection circuit 103T output of gate array 103 to be input to the first delay line 101A that is made up of at least one first single delay circuit 101AT.The signal that is input to the first delay line 101A is outputed to NAND door 53.

Be input to NAND door 53 with data 107 with by the signal of first delay line 101A output, NAND door 53 carries out the NAND computing between these signals, and merges the circuit 5 outputs first clock A to pulse.

Be input to the NAND door 54 of the second oscillator 102H by the signal (oppisite phase data) of 15 pairs of data 107 anti-phase acquisitions of inverter.And, select the signal of gate array 100S output to be input to the second selection gate array of forming by at least one second single selection circuit 104T 104 of the second oscillator 102H by first of synchronous delay circuit 100.In addition, the output signal with NAND door 54 is input to the second single selection circuit 104T that forms the second selection gate array 104.

Select the signal of gate array 104 outputs to be input to the second delay line 102A by second.Signal on the second delay line 102A outputs to NAND door 54.

So some is different with first and second embodiment in some aspects for the 3rd embodiment, it is made up of synchronous delay circuit 100, the first oscillator 101H, the second oscillator 102H, delay circuit 105 and lock-in circuit 106.

Describe operation below in detail according to the clock recovery circuitry of the 3rd embodiment.

Data 107 are input to the first oscillator 101H, and will be input to the second oscillator 102H by the signal that data 107 are carried out anti-phase acquisition.Reference clock 108 is input to synchronous delay circuit 100.Forming number of unit and its cycle of oscillation of the first and second oscillator 101H, 102H was determined by the pulse spacing of two continuous impulses.

When data 107 were high level pulse, the first oscillator 101H exported the first clock A, and it is regularly synchronous with the rising edge of data 107.When data 107 are low level pulse, second oscillator 102H output second clock B, it is regularly synchronous with the trailing edge of data 107.Pulse merges circuit 5 the first and second clock A, B is merged, and the output combined signal, as extracting clock 110.

With identical in first and second embodiment, output to the lock-in circuit of forming by D-F/F 106 with extracting clock 110, data 107 also are input on the lock-in circuit 106 by delay circuit 105.The input data are locked according to extracting clock 110 by lock-in circuit 106, and as playback of data 109, output to next stage with extracting clock 110.

Below with reference to the sequential of each signal among the 3rd embodiment of the foundation clock recovery circuitry of the present invention that shows among Fig. 4 B key diagram 4A, wherein Fig. 4 B is the sequential chart of relevant signal.

Fig. 4 B has shown reference clock 108, data 107, the first clock A, second clock B, has extracted the sequential of clock 110 and playback of data 109.

Shown in Fig. 4 B, when data 107 are in high logic level, export the first clock A synchronously with the rising edge of reference clock 108, and when data 107 are in low logic level, export second clock B synchronously with the trailing edge of reference clock 108.Therefore, it is synchronous with data 107 to extract clock 110, and playback of data 109 is also synchronous with data 107.

Therefore, according to the 3rd embodiment, the extraction clock 110 in clock recovery circuitry is realized by logical circuit synchronously with data 107.As a result, be difficult for the timing error of generation, and can shorten lock in time owing to appearance such as voltage fluctuations.[the 4th embodiment]

The 4th embodiment below with reference to Fig. 5 A and 5B explanation foundation clock recovery circuitry of the present invention.Fig. 5 A is the circuit diagram that shows according to the 4th embodiment of clock recovery circuitry of the present invention, and Fig. 5 B is the sequential chart of various signals relevant with clock recovery circuitry shown in Fig. 5 A.In Fig. 5 A and 5B, represent with similar label with signal with part identical among the 3rd embodiment that shows among Fig. 4 A and the 4B.

Shown in Fig. 5 A, the clock recovery circuitry of foundation the 4th embodiment of the present invention comprises: synchronous delay circuit 100, and data 107 are input on it; The first oscillator 101H, data 107 are input on it, are used to export the first clock A; Inverter 15 is used for data 107 anti-phase and outputs; The second oscillator 102H, the signal that carries out anti-phase acquisition by 15 pairs of data of inverter 107 is input on it, is used to export second clock B; Pulse merges circuit 5, is used to merge the first clock A and second clock B, and the output result, as extracting clock 110; Delay circuit 105, data 107 are input on it, are used to postpone these input data and output; And the lock-in circuit 106 that comprises the data type trigger, have input is merged the extraction clock 110 of circuit 5 outputs by pulse data terminal.

Synchronous delay circuit 100 comprises the first delay line 100A, is made up of at least one first single delay circuit 100T; And first select gate array 100S, is input on it by each signal of forming the first single delay circuit 100T output of the first delay line 100A, is made up of at least one first single selection circuit 100ST.Pulse merges circuit 5 preferably to be implemented by a NAND door that is used to carry out the NAND computing, so that accurately and easily carry out the pulse union operation.

The first oscillator 101H comprises that first selects gate array 103, is made up of at least one first single selection circuit 103T; Two first delay line 101A form first by each and select the signal of the first single selection circuit 103T output of gate array 103 to be input on it, and each first delay line 101A is made up of at least one first single delay circuit 101AT; And NAND door 55, be used to carry out the NAND computing.

The second oscillator 102H comprises that second selects gate array 104, is input on it by first signal of selecting gate array 100S to export, is made up of at least one second single selection circuit 104T; Two second delay line 102A form second by each and select the signal of the second single selection circuit 104T output of gate array 104 to be input on it, and each second delay line 102A is made up of at least one second single delay circuit 102AT; And NAND door 56, be used to carry out the NAND computing.

Data 107 are input to the first delay line 100A of synchronous delay circuit 100, and postpone back output by this first delay line 100A.And, also be input to the first selection gate array 100S by each signal and data 107 of forming the single delay circuit 100T output of the first delay line 100A, and each composition first selects the first single selection circuit 100ST of gate array 100S that its signal is outputed to the first and second oscillator 101H, 102H.

Data 107 are input to the NAND door 55 of the first oscillator 101H.And, select each signal of gate array 100S output to be input to first of the first oscillator 101H by first of synchronous delay circuit 100 and select gate array 103, and, select the signal of the first single selection circuit 103T output of gate array 103 alternately to be input to two first delay line 101A by forming first.Signal on two first delay line 101A outputs to NAND door 55.The latter merges the circuit 5 outputs first clock A to pulse.

The order of connection of first and second delay lines order of connection with the first and second single selection circuit respectively is opposite.So last of the first or second single delay circuit is corresponding to first of the first single selection circuit.Similar among this order of connection and Fig. 3 A and Fig. 4 A.Therefore, the change of first appearance will cause the change in corresponding steps.

Signal (oppisite phase data) by 15 pairs of data 107 anti-phase acquisitions of inverter is input to the second oscillator 102H.And, select each signal of gate array 100S output to be input to second of the second oscillator 102H by first of synchronous delay circuit 100 and select gate array 104, and select the signal of the second single selection circuit 104T output of gate array 104 alternately to be input to two second delay line 102A by forming second.Signal on two second delay line 102A outputs to NAND door 56.The latter merges circuit 5 output second clock B to pulse.

Be input to pulse merging circuit 5 by the first clock A of first oscillator 101H output with by the second clock B that the second oscillator 102H exports, pulse merges circuit 5 these clocks is merged, and the output result, as extraction clock 110.

So identical with the situation of the 3rd embodiment, the clock recovery circuitry of the 4th embodiment of foundation comprises synchronous delay circuit 100, the first oscillator 101H, the second oscillator 102H, delay circuit 105 and lock-in circuit 106.Data are input to the first oscillator 101H, after anti-phase, are input to the second oscillator 102H.

Yet, in the 4th embodiment, do not have reference clock 108.Determine to form the number and cycle of oscillation of unit of the first and second delay line 101A, the 102A of the first and second oscillator 101H, 102H, so that obtain to equal to be input to half cycle (in the embodiment that shows) of minimum spacing (pitch) of the data 107 of synchronous delay circuit 100.Yet the cycle shorter than this cycle also can be selected in the unit of the more a plurality of numbers of employing.

Describe operation below in detail according to the clock recovery circuitry of the 4th embodiment.

With identical in first to the 3rd embodiment, the extraction clock 110 in the 4th embodiment outputs to lock-in circuit 106, and data 107 also are input on the lock-in circuit 106 by delay circuit 105.The input data lock by extracting clock 110, and as playback of data 109, output to next stage with extracting clock 110.

Below with reference to the sequential of each signal among the 4th embodiment of the foundation clock recovery circuitry of the present invention that shows among Fig. 5 B key diagram 5A, wherein Fig. 5 B is the sequential chart of relevant signal.

Fig. 5 B has shown data 107, the first clock A, second clock B, has extracted the sequential of clock 110 and playback of data 109.

Shown in Fig. 5 B, when data 107 are in high logic level, export the first clock A synchronously with the rising edge of reference clock 108, and when data 107 are in low logic level, export second clock B synchronously with the trailing edge of reference clock 108.It is synchronous with data 107 to extract clock 110, and playback of data 109 is also synchronous with data 107.In addition, data 107 have one preposition section (preamble).

Therefore, according to the 4th embodiment, the extraction clock 110 in clock recovery circuitry is realized by logical circuit synchronously with data 107.As a result, be difficult for the timing error of generation, and can shorten lock in time owing to appearance such as voltage fluctuations.

Therefore, as mentioned above,, in synchronous delay circuit, bear a clock again from the minimum pulse of a reference clock and data-signal or from the minimum pulse spacing of data-signal according to the present invention.As a result, can provide a kind of clock recovery circuitry, in this circuit, synchronous regime can be obtained by a single minimum data pulse, thereby can shorten lock in time.

According to whole open text and subsidiary claims, under situation without departing from the spirit and scope of the present invention, can draw many significantly different widely embodiment of the present invention, therefore should be appreciated that the present invention is not limited in these certain embodiments.

Claims

1. a clock recovery circuitry comprises:

(a) one first synchronous delay circuit, reference clock and data are input on it, are used to export first clock;

(b) inverter is used for the anti-phase and output oppisite phase data to described data;

(c) one second synchronous delay circuit, reference clock and the oppisite phase data of being exported by described inverter are input on it, are used to export second clock;

(d) delay circuit, described data are input on it, are used to postpone these input data and output;

(e) pulse merges circuit, is input on it by first clock of described first synchronous delay circuit output and the second clock of being exported by described second synchronous delay circuit, is used to merge these input clocks, and the output result, as extracting clock; And

(f) data type flip-flop, have the data terminal of input by the extraction clock of described pulse merging circuit output, extract clock in response to this, described data type trigger is locked in the data that postpone in the described delay circuit, and export this locking data, as playback of data;

(g) wherein, described first synchronous delay circuit has:

(g1) one first delay line, reference clock is input on it, and this first delay line is made up of at least one first single delay circuit;

(g2) select gate array for one first, form by at least one second single selection circuit, reference clock by each first single delay circuit output of forming described first delay line is input on the second single selection circuit, and the second single selection circuit produces reference clock based on the data conduction that becomes to provide first; And

(g3) one the one NAND door, described data and the first generation reference clock of being exported by the described first selection data array are input on it, are used to export first clock; And

(h) described second synchronous delay circuit has:

(h1) one second delay line, reference clock is input on it, and this second delay line is made up of at least one the 3rd single delay circuit;

(h2) select gate array for one second, form by at least one the 4th single selection circuit, reference clock by each the 3rd single delay circuit output of forming described second delay line is input on the 4th single selection circuit, and the 4th single selection circuit produces reference clock based on the oppisite phase data conduction that becomes to produce second; And

(h3) one the 2nd NAND door is by the anti-phase data of described inverter with select second of gate array output to produce reference clock by described second to be input on it, to be used to export second clock.

2. clock recovery circuitry as claimed in claim 1 is characterized in that: described pulse merges circuit and is made of one the 3rd NAND door.

3. clock recovery circuitry comprises:

(g) wherein, described first synchronous delay circuit has:

(g1) one the 11st delay line, reference clock is input on it, and the 11st delay line is made up of at least one the 5th single delay circuit;

(g2) select gate array for one first, form by at least one the 6th single selection circuit, reference clock and the reference clock of being exported by each the 5th single delay circuit of forming described the 11st delay line are input on the 6th single selection circuit, and the 6th single selection circuit produces reference clock based on the data conduction that becomes to provide first;

(g3) one the 12nd delay line selects the clock of each the 6th single selection circuit output of gate array to be input on it by forming described first, and the 12nd delay line is made up of at least one the 7th single delay circuit; And

(g4) one the one NAND door, data and produce reference clock by first of the 12nd delay line output and be input on it; And

(h) described second synchronous delay circuit has:

(h1) one the 21st delay line, reference clock is input on it, and the 21st delay line is made up of at least one the 8th single delay circuit;

(h2) select gate array for one second, form by at least one the 9th single selection circuit, reference clock and the reference clock of being exported by each the 8th single delay circuit of forming described the 12nd delay line are input on the 9th single selection circuit, and the 9th single selection circuit produces reference clock based on the conduction that become by the anti-phase oppisite phase data of described inverter to produce second;

(h3) one the 22nd delay line selects the reference clock of each the 9th single selection circuit output of gate array to be input on it by forming described second, and the 22nd delay line is made up of at least one the tenth single delay circuit; And

(h4) one the 2nd NAND door is by the anti-phase data of inverter with produce reference clock by second of the 22nd delay line output and be input on it.

4. clock recovery circuitry as claimed in claim 3 is characterized in that: described pulse merges circuit and is made of one the 3rd NAND door.

5. clock recovery circuitry comprises:

(a) synchronous delay circuit, reference clock is input on it;

(b) one first oscillator, data are input on it, are used to export first clock;

(c) inverter is used for the anti-phase and output oppisite phase data to data;

(d) one second oscillator, the oppisite phase data of being exported by described inverter is input on it, is used to export second clock;

(e) pulse merges circuit, be used to merge by first clock of described first oscillator output and the second clock of exporting by described second oscillator, and the output result, as extracting clock;

(f) delay circuit, data are input on it, are used to postpone these input data and output; And

(g) data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data that postpone in the described delay circuit, and export this locking data, as playback of data;

(h) wherein, described synchronous delay circuit has:

(h1) one first delay line, reference clock is input on it, and this first delay line is made up of at least one the 11st single delay circuit; And

(h2) select gate array for one first, be made up of at least one the 12nd single selection circuit, reference clock and the reference clock of being exported by each the 11st single delay circuit of forming described first delay line are input on the 12nd single selection circuit;

(i) described first oscillator has:

(i1) select gate array for one the 11st, form described first by each and select the reference clock of the 12nd single selection circuit output of gate array to be input on it, the 11st selects gate array to be made up of at least one the 13rd single selection circuit;

(i2) one the 11st delay line is formed the described the 11st by each and is selected the reference clock of the 13rd single selection circuit output of gate array to be input on it, and the 11st delay line is made up of at least one the 14th single delay circuit; And

(i3) one the one NAND door, data and the reference clock of being exported by the 11st delay line are input on it, are used for forming the described the 11st to each and select the 13rd single selection circuit of gate array and described pulse merging circuit to export first clock; And

(j) described second oscillator has:

(j1) select gate array for one the 12nd, form described first by each and select the reference clock of the 12nd single selection circuit output of gate array to be input on it, the 12nd selects gate array to be made up of at least one the 15th single selection circuit;

(j2) one the 12nd delay line is formed the described the 12nd by each and is selected the reference clock of the 15th single selection circuit output of gate array to be input on it, and the 12nd delay line is made up of at least one the 16th single delay circuit; And

(j3) one the 2nd NAND door, be input on it by the anti-phase oppisite phase data of described inverter with by the reference clock of described the 12nd delay line output, be used for forming the described the 12nd and select the 15th single selection circuit of gate array and described pulse to merge circuit output second clock to each.

6. clock recovery circuitry as claimed in claim 5 is characterized in that: described pulse merges circuit and is made of one the 3rd NAND door.

7. clock recovery circuitry comprises:

(a) synchronous delay circuit, data are input on it;

(b) one first oscillator, data are input on it, are used to export first clock;

(c) inverter, data are input on it, are used to export oppisite phase data;

(e) pulse merges circuit, is input on it by first clock of described first oscillator output and the second clock of being exported by described second oscillator, is used to merge these two input clocks and exports the result, as extracting clock;

(g) data type flip-flop, have the data terminal of input by the extraction clock of described pulse merging circuit output, extract clock in response to this, described data type trigger locking is by the delayed data of described delay circuit output, and export this locking data, as playback of data;

(h) wherein, described synchronous delay circuit has:

(h1) one first delay line, data are input on it, and this first delay line is made up of at least one the 17th single delay circuit; And

(h2) select gate array for one first, be made up of at least one the 18th single selection circuit, data and the data of being exported by each the 17th single delay circuit of forming described first delay line are input on the 18th single selection circuit;

(i) described first oscillator has:

(i1) select gate array for one the 11st, form described first by each and select the data of the 18th single selection circuit output of gate array to be input on it, the 11st selects gate array to be made up of at least one the 19th single selection circuit;

(i2) two the 11st delay lines are formed the described the 11st by each and are selected the data of the 19th single selection circuit output of gate array to be input on it, and the 11st delay line is made up of at least one the 20th single delay circuit; And

(i3) one the one NAND door, oppisite phase data and the data of being exported by described two the 11st delay lines are input on it, are used for forming the described the 11st to each and select the 19th single selection circuit of gate array and described pulse merging circuit to export first clock; And

(j) described second oscillator has:

(j1) select gate array for one the 12nd, form described first by each and select the data of the 18th single selection circuit output of gate array to be input on it, the 12nd selects gate array to be made up of at least one the 21st single selection circuit;

(j2) two the 12nd delay lines are formed the described the 12nd by each and are selected the data of the 21st single selection circuit output of gate array to be input on it, and the 12nd delay line is made up of at least one the 22nd single delay circuit; And

(j3) one the 2nd NAND door, data and the data of being exported by described two the 12nd delay lines are input on it, are used for forming the described the 12nd to each and select the 21st single selection circuit of gate array and described pulse to merge circuit output second clock.

8. clock recovery circuitry as claimed in claim 7 is characterized in that: described pulse merges circuit and is made of one the 3rd NAND door.

9. clock recovery circuitry comprises:

(a) one first synchronous delay circuit, a data-signal is input on it, is used to export first clock (A);

(c) one second synchronous delay circuit, described anti-phase data signal is input on it, is used to export second clock (B);

(d) delay circuit, described data-signal is input on it, is used to postpone this input data signal and output;

(e) pulse merges circuit, and first clock (A) and second clock (B) are input on it, are used to merge these input clocks, and the output result, as extracting clock; And

(f) data type flip-flop, have the data terminal of input by the extraction clock of described pulse merging circuit output, extract clock in response to this, described data type trigger is locked in the data-signal that postpones in the described delay circuit, and export this locking data signal, as regenerated data signal;

(g) wherein, first and second synchronous delay circuits are complementary multilevel delay circuit synchronously, be used for exporting and the first and second synchronous output signals of described data-signal corresponding to first state of described data-signal and a time cycle of second state, as the pulse signal that has than the pulse period of the minimum period much shorter of the state of described data-signal, so that make the time cycle that reaches synchronously required the shortest.

10. clock recovery circuitry as claimed in claim 9 is characterized in that: described synchronous delay circuit receives the reference clock of the pulse period with described pulse signal, is used for synchronously.

11. clock recovery circuitry as claimed in claim 9 is characterized in that: the pulse period of described pulse signal is half of minimum period of the state of data-signal.

12. clock recovery circuitry as claimed in claim 10, it is characterized in that: each described synchronous multilevel delay circuit comprises a single delay circuit array, each grade of this single delay circuit array is connected to the corresponding stage of a single selection gate array, and

Wherein, described data-signal is provided to each level of described single selection gate array, so that allow the reference clock of a generation of arbitrary grade of output, the reference clock that produces is provided to a NAND, NAND further receives described data-signal, and export first and second clocks (A, B) in any respectively.

13. clock recovery circuitry as claimed in claim 12 is characterized in that: described single selection gate array can connect with the order identical with single delay circuit array.

14. clock recovery circuitry as claimed in claim 12 is characterized in that: described single selection gate array can connect with the order opposite with single delay circuit array.

15. a clock recovery circuitry comprises:

(a) synchronous multilevel delay circuit, a reference clock is input on it;

(b) one first oscillator, a data-signal is input on it, is used to export first clock (A);

(d) one second oscillator, the anti-phase data signal of being exported by described inverter is input on it, is used to export second clock (B);

(e) pulse merges circuit, be used to merge by first clock (A) of described first oscillator output and the second clock of exporting by described second oscillator (B), and the output result, as extracting clock;

(g) data type flip-flop, have the data terminal of input by the extraction clock of pulse merging circuit output, extract clock in response to this, the data type trigger is locked in the data-signal that postpones in the described delay circuit, and export this locking data signal, as regenerated data signal;

(h) wherein, described synchronous multilevel delay circuit comprises a single delay circuit array, and each grade of this single delay circuit array provides the reference clock of a generation, and the reference clock of generation is provided to each level of first and second oscillators,

(i) wherein, described first and second oscillators are complementary synclators, be used for exporting and synchronous difference first and second output signals of described data-signal corresponding to first state of described data-signal and a time cycle of second state, as the pulse signal that has than the pulse period of the minimum period much shorter of the state of described data-signal, so that make the time cycle that reaches synchronously required the shortest.

16. a clock recovery circuitry comprises:

(a) synchronous multilevel delay circuit, a data-signal is input on it;

(b) one first oscillator, data-signal is input on it, is used to export first clock (A);

(c) inverter, data-signal is input on it, is used to export anti-phase data signal;

(e) pulse merges circuit, and first clock (A) and second clock (B) are input on it, are used to merge this two input clocks, and the output result, as extracting clock;

(g) data type flip-flop, have the data terminal of input by the extraction clock of described pulse merging circuit output, extract clock in response to this, described data type trigger locking is by the delayed data signal of described delay circuit output, and export this locking data, as regenerated data signal;